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Commit | Line | Data |
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3f0606ad AL |
1 | /* |
2 | * U-boot - Configuration file for BF533 EZKIT board | |
3 | */ | |
4 | ||
cf6f469e MF |
5 | #ifndef __CONFIG_BF533_EZKIT_H__ |
6 | #define __CONFIG_BF533_EZKIT_H__ | |
3f0606ad | 7 | |
f7ce12cb MF |
8 | #include <asm/blackfin-config-pre.h> |
9 | ||
3f0606ad | 10 | |
cf6f469e MF |
11 | /* |
12 | * Processor Settings | |
13 | */ | |
14 | #define CONFIG_BFIN_CPU bf533-0.3 | |
15 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS | |
3f0606ad | 16 | |
3f0606ad | 17 | |
cf6f469e MF |
18 | /* |
19 | * Clock Settings | |
20 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV | |
21 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV | |
22 | */ | |
23 | /* CONFIG_CLKIN_HZ is any value in Hz */ | |
24 | #define CONFIG_CLKIN_HZ 27000000 | |
25 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ | |
26 | /* 1 = CLKIN / 2 */ | |
27 | #define CONFIG_CLKIN_HALF 0 | |
28 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ | |
29 | /* 1 = bypass PLL */ | |
30 | #define CONFIG_PLL_BYPASS 0 | |
31 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ | |
32 | /* Values can range from 0-63 (where 0 means 64) */ | |
33 | #define CONFIG_VCO_MULT 22 | |
34 | /* CCLK_DIV controls the core clock divider */ | |
35 | /* Values can be 1, 2, 4, or 8 ONLY */ | |
36 | #define CONFIG_CCLK_DIV 1 | |
37 | /* SCLK_DIV controls the system clock divider */ | |
38 | /* Values can range from 1-15 */ | |
39 | #define CONFIG_SCLK_DIV 5 | |
3f0606ad | 40 | |
3f0606ad | 41 | |
cf6f469e MF |
42 | /* |
43 | * Memory Settings | |
44 | */ | |
45 | #define CONFIG_MEM_SIZE 32 | |
46 | /* Early EZKITs had 32megs, but later have 64megs */ | |
47 | #if (CONFIG_MEM_SIZE == 64) | |
48 | # define CONFIG_MEM_ADD_WDTH 10 | |
3f0606ad | 49 | #else |
cf6f469e | 50 | # define CONFIG_MEM_ADD_WDTH 9 |
3f0606ad AL |
51 | #endif |
52 | ||
cf6f469e MF |
53 | #define CONFIG_EBIU_SDRRC_VAL 0x398 |
54 | #define CONFIG_EBIU_SDGCTL_VAL 0x91118d | |
3f0606ad | 55 | |
cf6f469e MF |
56 | #define CONFIG_EBIU_AMGCTL_VAL 0xFF |
57 | #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 | |
58 | #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 | |
3f0606ad | 59 | |
cf6f469e MF |
60 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
61 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) | |
3f0606ad AL |
62 | |
63 | ||
079a136c | 64 | /* |
cf6f469e | 65 | * Network Settings |
079a136c | 66 | */ |
cf6f469e MF |
67 | #define ADI_CMDS_NETWORK 1 |
68 | #define CONFIG_DRIVER_SMC91111 1 | |
69 | #define CONFIG_SMC91111_BASE 0x20310300 | |
70 | #define SMC91111_EEPROM_INIT() \ | |
71 | do { \ | |
72 | *pFIO_DIR |= PF1; \ | |
73 | *pFIO_FLAG_S = PF1; \ | |
74 | SSYNC(); \ | |
75 | } while (0) | |
76 | #define CONFIG_HOSTNAME bf533-ezkit | |
77 | /* Uncomment next line to use fixed MAC address */ | |
78 | /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ | |
079a136c JL |
79 | |
80 | ||
ba2351f9 | 81 | /* |
cf6f469e | 82 | * Flash Settings |
ba2351f9 | 83 | */ |
6d0f6bcf | 84 | #define CONFIG_SYS_FLASH_BASE 0x20000000 |
cf6f469e MF |
85 | #define CONFIG_SYS_MAX_FLASH_BANKS 3 |
86 | #define CONFIG_SYS_MAX_FLASH_SECT 40 | |
87 | #define CONFIG_ENV_IS_IN_FLASH | |
0e8d1586 | 88 | #define CONFIG_ENV_ADDR 0x20020000 |
cf6f469e | 89 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
3f0606ad | 90 | #define FLASH_TOT_SECT 40 |
3f0606ad | 91 | |
3f0606ad AL |
92 | |
93 | /* | |
cf6f469e | 94 | * I2C Settings |
3f0606ad AL |
95 | * By default PF1 is used as SDA and PF0 as SCL on the Stamp board |
96 | */ | |
cf6f469e MF |
97 | #define CONFIG_SOFT_I2C |
98 | #ifdef CONFIG_SOFT_I2C | |
99 | #define PF_SCL PF0 | |
100 | #define PF_SDA PF1 | |
101 | #define I2C_INIT \ | |
102 | do { \ | |
103 | *pFIO_DIR |= PF_SCL; \ | |
104 | SSYNC(); \ | |
105 | } while (0) | |
106 | #define I2C_ACTIVE \ | |
107 | do { \ | |
108 | *pFIO_DIR |= PF_SDA; \ | |
109 | *pFIO_INEN &= ~PF_SDA; \ | |
110 | SSYNC(); \ | |
111 | } while (0) | |
112 | #define I2C_TRISTATE \ | |
113 | do { \ | |
114 | *pFIO_DIR &= ~PF_SDA; \ | |
115 | *pFIO_INEN |= PF_SDA; \ | |
116 | SSYNC(); \ | |
117 | } while (0) | |
118 | #define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0) | |
119 | #define I2C_SDA(bit) \ | |
120 | do { \ | |
121 | if (bit) \ | |
122 | *pFIO_FLAG_S = PF_SDA; \ | |
123 | else \ | |
124 | *pFIO_FLAG_C = PF_SDA; \ | |
125 | SSYNC(); \ | |
126 | } while (0) | |
127 | #define I2C_SCL(bit) \ | |
128 | do { \ | |
129 | if (bit) \ | |
130 | *pFIO_FLAG_S = PF_SCL; \ | |
131 | else \ | |
132 | *pFIO_FLAG_C = PF_SCL; \ | |
133 | SSYNC(); \ | |
134 | } while (0) | |
135 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
8db13d63 | 136 | |
6d0f6bcf | 137 | #define CONFIG_SYS_I2C_SPEED 50000 |
be853bf8 | 138 | #define CONFIG_SYS_I2C_SLAVE 0 |
cf6f469e | 139 | #endif |
3f0606ad | 140 | |
3f0606ad | 141 | |
cf6f469e MF |
142 | /* |
143 | * Misc Settings | |
144 | */ | |
145 | #define CONFIG_MISC_INIT_R | |
146 | #define CONFIG_RTC_BFIN | |
147 | #define CONFIG_UART_CONSOLE 0 | |
148 | ||
9171fc81 | 149 | |
cf6f469e MF |
150 | /* |
151 | * Pull in common ADI header for remaining command/environment setup | |
152 | */ | |
153 | #include <configs/bfin_adi_common.h> | |
9171fc81 MF |
154 | |
155 | #include <asm/blackfin-config-post.h> | |
3f0606ad AL |
156 | |
157 | #endif |