[people/ms/u-boot.git] / include / configs / bf533-stamp.h

/*
 * U-boot - Configuration file for BF533 STAMP board
 */

#ifndef __CONFIG_STAMP_H__
#define __CONFIG_STAMP_H__

#define CONFIG_STAMP			1
#define CONFIG_RTC_BFIN			1
#define CONFIG_BF533			1
/*
 * Boot Mode Set
 * Blackfin can support several boot modes
 */
#define BF533_BYPASS_BOOT	0x0001	/* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
#define BF533_PARA_BOOT		0x0002	/* Bootmode 1: Boot from 8-bit or 16-bit flash */
#define BF533_SPI_BOOT		0x0004	/* Bootmode 3: Boot from SPI flash */
/* Define the boot mode */
#define BFIN_BOOT_MODE		BF533_BYPASS_BOOT
/* #define BFIN_BOOT_MODE	BF533_SPI_BOOT */

#define CONFIG_PANIC_HANG 1

#define ADSP_BF531		0x31
#define ADSP_BF532		0x32
#define ADSP_BF533		0x33
#define BFIN_CPU		ADSP_BF533

/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
#define CONFIG_DCACHE_ON

/* Define where the uboot will be loaded by on-chip boot rom */
#define APP_ENTRY 0x00001000

/*
 * Stringize definitions - needed for environmental settings
 */
#define STRINGIZE2(x) #x
#define STRINGIZE(x) STRINGIZE2(x)

/*
 * Board settings
 */
#define CONFIG_DRIVER_SMC91111	1
#define CONFIG_SMC91111_BASE	0x20300300

/* FLASH/ETHERNET uses the same address range */
#define SHARED_RESOURCES 	1

/* Is I2C bit-banged? */
#define CONFIG_SOFT_I2C		1

/*
 * Software (bit-bang) I2C driver configuration
 */
#define PF_SCL			PF3
#define PF_SDA			PF2

/*
 * Video splash screen support
 */
#define  CONFIG_VIDEO		0

#define CONFIG_VDSP		1

/*
 * Clock settings
 */

/* CONFIG_CLKIN_HZ is any value in Hz				*/
#define CONFIG_CLKIN_HZ		11059200
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
/*						    1=CLKIN/2	*/
#define CONFIG_CLKIN_HALF	0
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	*/
/*						 1=bypass PLL	*/
#define CONFIG_PLL_BYPASS	0
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	*/
/* Values can range from 1-64					*/
#define CONFIG_VCO_MULT		36
/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
/* Values can be 1, 2, 4, or 8 ONLY				*/
#define CONFIG_CCLK_DIV		1
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
/* Values can range from 1-15					*/
#define CONFIG_SCLK_DIV		5
/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
/* Values can range from 2-65535				*/
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
#define CONFIG_SPI_BAUD		2

#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#define CONFIG_SPI_BAUD_INITBLOCK	4
#endif

/*
 * Network settings
 */

#if (CONFIG_DRIVER_SMC91111)
#if 0
#define	CONFIG_MII
#endif

/* network support */
#define CONFIG_IPADDR		192.168.0.15
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_GATEWAYIP	192.168.0.1
#define CONFIG_SERVERIP		192.168.0.2
#define CONFIG_HOSTNAME		STAMP
#define CONFIG_ROOTPATH		/checkout/uClinux-dist/romfs

/* To remove hardcoding and enable MAC storage in EEPROM  */
/* #define CONFIG_ETHADDR		02:80:ad:20:31:b8 */
#endif /* CONFIG_DRIVER_SMC91111 */

/*
 * Flash settings
 */

#define CFG_FLASH_CFI		/* The flash is CFI compatible  */
#define CFG_FLASH_CFI_DRIVER	/* Use common CFI driver	*/
#define	CFG_FLASH_CFI_AMD_RESET

#define CFG_FLASH_BASE		0x20000000
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */

#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR		0x20004000
#define	CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#define CFG_ENV_IS_IN_EEPROM	1
#define CFG_ENV_OFFSET		0x4000
#define CFG_ENV_HEADER		(CFG_ENV_OFFSET + 0x12A)	/* 0x12A is the length of LDR file header */
#endif

#define	CFG_ENV_SIZE		0x2000
#define CFG_ENV_SECT_SIZE 	0x2000	/* Total Size of Environment Sector */
#define	ENV_IS_EMBEDDED

#define CFG_FLASH_ERASE_TOUT	30000	/* Timeout for Chip Erase (in ms) */
#define CFG_FLASH_ERASEBLOCK_TOUT	5000	/* Timeout for Block Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms) */

/* JFFS Partition offset set  */
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_NUM_BANKS  1
/* 512k reserved for u-boot */
#define CFG_JFFS2_FIRST_SECTOR 	11

/*
 * following timeouts shall be used once the
 * Flash real protection is enabled
 */
#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */

/*
 * SDRAM settings & memory map
 */

#define CONFIG_MEM_SIZE		128	/* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH     11	/* 8, 9, 10, 11    */
#define CONFIG_MEM_MT48LC64M4A2FB_7E	1

#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CFG_MEMTEST_START	0x00000000	/* memtest works on */
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#endif

#define	CFG_SDRAM_BASE		0x00000000

#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 *1024)
#define CFG_MEMTEST_END		(CFG_MAX_RAM_SIZE - 0x80000 - 1)
#define CONFIG_LOADADDR		0x01000000

#define CFG_LOAD_ADDR 		CONFIG_LOADADDR
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)     /* Reserve 128 kB for malloc()	*/
#define CFG_GBL_DATA_SIZE	0x4000		/* Reserve 16k for Global Data  */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */

#define CFG_MONITOR_BASE		(CFG_MAX_RAM_SIZE - 0x40000)
#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)

/* Check to make sure everything fits in SDRAM */
#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
	#error Memory Map does not fit into configuration
#endif

#if ( CONFIG_CLKIN_HALF == 0 )
#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
#else
#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
#endif

#if (CONFIG_PLL_BYPASS == 0)
#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
#else
#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
#endif

#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
#else
#undef CONFIG_SPI_FLASH_FAST_READ
#endif
#endif

/*
 * Command settings
 */

#define CFG_LONGHELP		1
#define CONFIG_CMDLINE_EDITING	1

#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CFG_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */
#endif

/* configuration lookup from the BOOTP/DHCP server, */
/* but not try to load any image using TFTP	    */

#define CONFIG_BOOTDELAY	5
#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CONFIG_BOOTCOMMAND	"run ramboot"
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#define CONFIG_BOOTCOMMAND 	"eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
#endif

#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw console=ttyBF0,57600"


#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#if (CONFIG_DRIVER_SMC91111)
#define CONFIG_EXTRA_ENV_SETTINGS \
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
		"$(rootpath) console=ttyBF0,57600\0" \
	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
		"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
	"ramboot=tftpboot $(loadaddr) linux; " \
		"run ramargs;run addip;bootelf\0" \
	"nfsboot=tftpboot $(loadaddr) linux; " \
		"run nfsargs;run addip;bootelf\0" \
	"flashboot=bootm 0x20100000\0" \
	"update=tftpboot $(loadaddr) u-boot.bin; " \
		"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
		"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
	""
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	"flashboot=bootm 0x20100000\0" \
	"
#endif

#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#define CONFIG_EXTRA_ENV_SETTINGS \
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
		"$(rootpath) console=ttyBF0,57600\0"	\
	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
		"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
	"ramboot=tftpboot $(loadaddr) linux; " \
		"run ramargs;run addip;bootelf\0" \
	"nfsboot=tftpboot $(loadaddr) linux; "	\
		"run nfsargs;run addip;bootelf\0" \
	"flashboot=bootm 0x20100000\0" \
	"update=tftpboot $(loadaddr) u-boot.ldr;"	\
		"eeprom write $(loadaddr) 0x0 $(filesize);\0"\
	""
#endif

#ifdef CONFIG_SOFT_I2C
#if (!CONFIG_SOFT_I2C)
#undef CONFIG_SOFT_I2C
#endif
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ELF
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_DATE

#if (CONFIG_DRIVER_SMC91111)
#define CONFIG_CMD_PING
#endif

#if (CONFIG_SOFT_I2C)
#define CONFIG_CMD_I2C
#endif

#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CONFIG_CMD_DHCP
#endif


/*
 * Console settings
 */

#define CONFIG_BAUDRATE		57600
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#if (BFIN_CPU == ADSP_BF531)
#define	CFG_PROMPT	"serial_bf531> "	/* Monitor Command Prompt */
#elif (BFIN_CPU == ADSP_BF532)
#define	CFG_PROMPT	"serial_bf532> "	/* Monitor Command Prompt */
#else
#define	CFG_PROMPT	"serial_bf533> "	/* Monitor Command Prompt */
#endif
#else
#if (BFIN_CPU == ADSP_BF531)
#define	CFG_PROMPT	"bf531> "	/* Monitor Command Prompt */
#elif (BFIN_CPU == ADSP_BF532)
#define	CFG_PROMPT	"bf532> "	/* Monitor Command Prompt */
#else
#define	CFG_PROMPT	"bf533> "	/* Monitor Command Prompt */
#endif
#endif

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_LOADS_ECHO	1

/*
 * I2C settings
 * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
 */
#if (CONFIG_SOFT_I2C)

#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
#define I2C_SDA(bit)	if(bit) { \
				*pFIO_FLAG_S = PF_SDA; \
				asm("ssync;"); \
				} \
			else	{ \
				*pFIO_FLAG_C = PF_SDA; \
				asm("ssync;"); \
				}
#define I2C_SCL(bit)	if(bit) { \
				*pFIO_FLAG_S = PF_SCL; \
				asm("ssync;"); \
				} \
			else	{ \
				*pFIO_FLAG_C = PF_SCL; \
				asm("ssync;"); \
				}
#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */

#define CFG_I2C_SPEED		50000
#define CFG_I2C_SLAVE		0xFE
#endif /* CONFIG_SOFT_I2C */

/*
 * Compact Flash settings
 */

/* Enabled below option for CF support */
/* #define CONFIG_STAMP_CF	1 */

#if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE)

#define CONFIG_MISC_INIT_R	1
#define CONFIG_DOS_PARTITION	1
/*
 * IDE/ATA stuff
 */
#undef  CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef  CONFIG_IDE_LED			/* no led for ide supported */
#undef  CONFIG_IDE_RESET		/* no reset for ide supported */

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses */
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	0x20200000
#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
#define CFG_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
#define CFG_ATA_ALT_OFFSET	0x0007	/* Offset for alternate registers */

#define CFG_ATA_STRIDE		2
#endif

/*
 * Miscellaneous configurable options
 */

#define	CFG_HZ			1000	/* 1ms time tick */

#define CFG_BOOTM_LEN		0x4000000/* Large Image Length, set to 64 Meg */

#define CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs */

#define CONFIG_SPI

#ifdef  CONFIG_VIDEO
#if (CONFIG_VIDEO)
#define CONFIG_SPLASH_SCREEN	1
#define CONFIG_SILENT_CONSOLE	1
#else
#undef CONFIG_VIDEO
#endif
#endif

/*
 * FLASH organization and environment definitions
 */
#define	CFG_BOOTMAPSZ		(8 << 20)/* Initial Memory map for Linux */

/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
/*#define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
#define AMBCTL0VAL		(B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
				B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
#define AMBCTL1VAL   		(B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
				B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
*/
#define AMGCTLVAL		0xFF
#define AMBCTL0VAL		0xBBC3BBC3
#define AMBCTL1VAL		0x99B39983
#define CF_AMBCTL1VAL		0x99B3ffc2

#ifdef CONFIG_VDSP
#define ET_EXEC_VDSP		0x8
#define SHT_STRTAB_VDSP		0x1
#define ELFSHDRSIZE_VDSP	0x2C
#define VDSP_ENTRY_ADDR		0xFFA00000
#endif

#endif
Commit	Line	Data
3f0606ad AL	1	/*
	2	* U-boot - Configuration file for BF533 STAMP board
	3	*/
	4
	5	#ifndef __CONFIG_STAMP_H__
	6	#define __CONFIG_STAMP_H__
	7
	8	#define CONFIG_STAMP 1
	9	#define CONFIG_RTC_BFIN 1
	10	#define CONFIG_BF533 1
	11	/*
	12	* Boot Mode Set
	13	* Blackfin can support several boot modes
	14	*/
8db13d63 AL	15	#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
	16	#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
	17	#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
3f0606ad AL	18	/* Define the boot mode */
3f0606ad AL	19	#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
8db13d63	20	/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */
3f0606ad AL	21
	22	#define CONFIG_PANIC_HANG 1
	23
	24	#define ADSP_BF531 0x31
	25	#define ADSP_BF532 0x32
	26	#define ADSP_BF533 0x33
	27	#define BFIN_CPU ADSP_BF533
	28
	29	/* This sets the default state of the cache on U-Boot's boot */
	30	#define CONFIG_ICACHE_ON
	31	#define CONFIG_DCACHE_ON
	32
	33	/* Define where the uboot will be loaded by on-chip boot rom */
	34	#define APP_ENTRY 0x00001000
	35
	36	/*
	37	* Stringize definitions - needed for environmental settings
	38	*/
	39	#define STRINGIZE2(x) #x
	40	#define STRINGIZE(x) STRINGIZE2(x)
	41
	42	/*
	43	* Board settings
3f0606ad	44	*/
8db13d63 AL	45	#define CONFIG_DRIVER_SMC91111 1
8db13d63 AL	46	#define CONFIG_SMC91111_BASE 0x20300300
3f0606ad AL	47
3f0606ad AL	48	/* FLASH/ETHERNET uses the same address range */
8db13d63	49	#define SHARED_RESOURCES 1
3f0606ad AL	50
3f0606ad AL	51	/* Is I2C bit-banged? */
8db13d63	52	#define CONFIG_SOFT_I2C 1
3f0606ad AL	53
	54	/*
	55	* Software (bit-bang) I2C driver configuration
	56	*/
8db13d63 AL	57	#define PF_SCL PF3
8db13d63 AL	58	#define PF_SDA PF2
3f0606ad AL	59
	60	/*
	61	* Video splash screen support
	62	*/
8db13d63	63	#define CONFIG_VIDEO 0
3f0606ad	64
8db13d63	65	#define CONFIG_VDSP 1
3f0606ad AL	66
	67	/*
	68	* Clock settings
3f0606ad AL	69	*/
3f0606ad AL	70
8db13d63 AL	71	/* CONFIG_CLKIN_HZ is any value in Hz */
	72	#define CONFIG_CLKIN_HZ 11059200
	73	/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
	74	/* 1=CLKIN/2 */
	75	#define CONFIG_CLKIN_HALF 0
	76	/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
	77	/* 1=bypass PLL */
	78	#define CONFIG_PLL_BYPASS 0
	79	/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
	80	/* Values can range from 1-64 */
	81	#define CONFIG_VCO_MULT 36
	82	/* CONFIG_CCLK_DIV controls what the core clock divider is */
	83	/* Values can be 1, 2, 4, or 8 ONLY */
	84	#define CONFIG_CCLK_DIV 1
	85	/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
	86	/* Values can range from 1-15 */
	87	#define CONFIG_SCLK_DIV 5
	88	/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
	89	/* Values can range from 2-65535 */
	90	/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
	91	#define CONFIG_SPI_BAUD 2
3f0606ad AL	92
3f0606ad AL	93	#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
8db13d63	94	#define CONFIG_SPI_BAUD_INITBLOCK 4
3f0606ad AL	95	#endif
3f0606ad AL	96
3f0606ad AL	97	/*
3f0606ad AL	98	* Network settings
3f0606ad AL	99	*/
	100
	101	#if (CONFIG_DRIVER_SMC91111)
	102	#if 0
	103	#define CONFIG_MII
	104	#endif
	105
	106	/* network support */
8db13d63 AL	107	#define CONFIG_IPADDR 192.168.0.15
	108	#define CONFIG_NETMASK 255.255.255.0
	109	#define CONFIG_GATEWAYIP 192.168.0.1
	110	#define CONFIG_SERVERIP 192.168.0.2
	111	#define CONFIG_HOSTNAME STAMP
	112	#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
3f0606ad AL	113
3f0606ad AL	114	/* To remove hardcoding and enable MAC storage in EEPROM */
8db13d63	115	/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
3f0606ad AL	116	#endif /* CONFIG_DRIVER_SMC91111 */
	117
	118	/*
	119	* Flash settings
3f0606ad AL	120	*/
3f0606ad AL	121
8db13d63	122	#define CFG_FLASH_CFI /* The flash is CFI compatible */
0d93de11	123	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
3f0606ad AL	124	#define CFG_FLASH_CFI_AMD_RESET
3f0606ad AL	125
8db13d63 AL	126	#define CFG_FLASH_BASE 0x20000000
	127	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	128	#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
3f0606ad AL	129
3f0606ad AL	130	#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
8db13d63 AL	131	#define CFG_ENV_IS_IN_FLASH 1
	132	#define CFG_ENV_ADDR 0x20004000
	133	#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
3f0606ad	134	#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
8db13d63 AL	135	#define CFG_ENV_IS_IN_EEPROM 1
	136	#define CFG_ENV_OFFSET 0x4000
	137	#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */
3f0606ad AL	138	#endif
3f0606ad AL	139
8db13d63 AL	140	#define CFG_ENV_SIZE 0x2000
8db13d63 AL	141	#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
3f0606ad AL	142	#define ENV_IS_EMBEDDED
3f0606ad AL	143
8db13d63	144	#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
3f0606ad	145	#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
8db13d63	146	#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
3f0606ad AL	147
	148	/* JFFS Partition offset set */
	149	#define CFG_JFFS2_FIRST_BANK 0
	150	#define CFG_JFFS2_NUM_BANKS 1
	151	/* 512k reserved for u-boot */
8db13d63	152	#define CFG_JFFS2_FIRST_SECTOR 11
3f0606ad AL	153
	154	/*
	155	* following timeouts shall be used once the
	156	* Flash real protection is enabled
	157	*/
8db13d63 AL	158	#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
8db13d63 AL	159	#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
3f0606ad AL	160
	161	/*
	162	* SDRAM settings & memory map
3f0606ad AL	163	*/
3f0606ad AL	164
8db13d63 AL	165	#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
8db13d63 AL	166	#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
3f0606ad AL	167	#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
	168
	169	#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
8db13d63	170	#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
3f0606ad	171	#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
8db13d63	172	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
3f0606ad AL	173	#endif
3f0606ad AL	174
8db13d63	175	#define CFG_SDRAM_BASE 0x00000000
3f0606ad AL	176
	177	#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024)
	178	#define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1)
	179	#define CONFIG_LOADADDR 0x01000000
	180
8db13d63 AL	181	#define CFG_LOAD_ADDR CONFIG_LOADADDR
	182	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	183	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	184	#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
	185	#define CONFIG_STACKSIZE (1281024) / regular stack */
3f0606ad AL	186
3f0606ad AL	187	#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - 0x40000)
8db13d63 AL	188	#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
	189	#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
	190	#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
3f0606ad AL	191
	192	/* Check to make sure everything fits in SDRAM */
	193	#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
	194	#error Memory Map does not fit into configuration
	195	#endif
	196
	197	#if ( CONFIG_CLKIN_HALF == 0 )
8db13d63	198	#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
3f0606ad	199	#else
8db13d63	200	#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
3f0606ad AL	201	#endif
	202
	203	#if (CONFIG_PLL_BYPASS == 0)
8db13d63 AL	204	#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
8db13d63 AL	205	#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
3f0606ad	206	#else
8db13d63 AL	207	#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
8db13d63 AL	208	#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
3f0606ad AL	209	#endif
	210
	211	#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
	212	#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
	213	#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
	214	#else
	215	#undef CONFIG_SPI_FLASH_FAST_READ
	216	#endif
	217	#endif
8db13d63	218
3f0606ad AL	219	/*
3f0606ad AL	220	* Command settings
3f0606ad AL	221	*/
3f0606ad AL	222
8db13d63 AL	223	#define CFG_LONGHELP 1
8db13d63 AL	224	#define CONFIG_CMDLINE_EDITING 1
3f0606ad AL	225
3f0606ad AL	226	#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
8db13d63	227	#define CFG_AUTOLOAD "no" /rarpb, bootp or dhcp commands will perform only a /
3f0606ad	228	#endif
3f0606ad	229
8db13d63	230	/* configuration lookup from the BOOTP/DHCP server, */
0d93de11	231	/* but not try to load any image using TFTP */
8db13d63 AL	232
	233	#define CONFIG_BOOTDELAY 5
	234	#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
3f0606ad	235	#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
8db13d63	236	#define CONFIG_BOOTCOMMAND "run ramboot"
3f0606ad	237	#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
8db13d63	238	#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
3f0606ad AL	239	#endif
3f0606ad AL	240
8db13d63	241	#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
3f0606ad	242
3f0606ad AL	243
	244	#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
	245	#if (CONFIG_DRIVER_SMC91111)
	246	#define CONFIG_EXTRA_ENV_SETTINGS \
8db13d63 AL	247	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	248	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
	249	"$(rootpath) console=ttyBF0,57600\0" \
	250	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
	251	"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
	252	"ramboot=tftpboot $(loadaddr) linux; " \
3f0606ad	253	"run ramargs;run addip;bootelf\0" \
8db13d63	254	"nfsboot=tftpboot $(loadaddr) linux; " \
3f0606ad	255	"run nfsargs;run addip;bootelf\0" \
8db13d63 AL	256	"flashboot=bootm 0x20100000\0" \
	257	"update=tftpboot $(loadaddr) u-boot.bin; " \
	258	"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
	259	"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
	260	""
3f0606ad AL	261	#else
3f0606ad AL	262	#define CONFIG_EXTRA_ENV_SETTINGS \
8db13d63 AL	263	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	264	"flashboot=bootm 0x20100000\0" \
	265	"
3f0606ad AL	266	#endif
	267
	268	#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
	269	#define CONFIG_EXTRA_ENV_SETTINGS \
	270	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	271	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
	272	"$(rootpath) console=ttyBF0,57600\0" \
	273	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
	274	"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
0d93de11	275	"ramboot=tftpboot $(loadaddr) linux; " \
3f0606ad AL	276	"run ramargs;run addip;bootelf\0" \
	277	"nfsboot=tftpboot $(loadaddr) linux; " \
	278	"run nfsargs;run addip;bootelf\0" \
	279	"flashboot=bootm 0x20100000\0" \
	280	"update=tftpboot $(loadaddr) u-boot.ldr;" \
	281	"eeprom write $(loadaddr) 0x0 $(filesize);\0"\
	282	""
	283	#endif
	284
	285	#ifdef CONFIG_SOFT_I2C
	286	#if (!CONFIG_SOFT_I2C)
	287	#undef CONFIG_SOFT_I2C
	288	#endif
	289	#endif
	290
ba2351f9	291
079a136c JL	292	/*
	293	* BOOTP options
	294	*/
	295	#define CONFIG_BOOTP_BOOTFILESIZE
	296	#define CONFIG_BOOTP_BOOTPATH
	297	#define CONFIG_BOOTP_GATEWAY
	298	#define CONFIG_BOOTP_HOSTNAME
	299
	300
ba2351f9 JL	301	/*
	302	* Command line configuration.
	303	*/
	304	#include <config_cmd_default.h>
	305
	306	#define CONFIG_CMD_ELF
	307	#define CONFIG_CMD_CACHE
	308	#define CONFIG_CMD_JFFS2
	309	#define CONFIG_CMD_EEPROM
	310	#define CONFIG_CMD_DATE
	311
	312	#if (CONFIG_DRIVER_SMC91111)
	313	#define CONFIG_CMD_PING
	314	#endif
	315
3f0606ad	316	#if (CONFIG_SOFT_I2C)
ba2351f9 JL	317	#define CONFIG_CMD_I2C
ba2351f9 JL	318	#endif
3f0606ad AL	319
3f0606ad AL	320	#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
ba2351f9	321	#define CONFIG_CMD_DHCP
3f0606ad AL	322	#endif
3f0606ad AL	323
3f0606ad AL	324
	325	/*
	326	* Console settings
3f0606ad AL	327	*/
3f0606ad AL	328
8db13d63 AL	329	#define CONFIG_BAUDRATE 57600
8db13d63 AL	330	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
3f0606ad AL	331
	332	#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
	333	#if (BFIN_CPU == ADSP_BF531)
8db13d63	334	#define CFG_PROMPT "serial_bf531> " /* Monitor Command Prompt */
3f0606ad	335	#elif (BFIN_CPU == ADSP_BF532)
8db13d63	336	#define CFG_PROMPT "serial_bf532> " /* Monitor Command Prompt */
3f0606ad	337	#else
8db13d63	338	#define CFG_PROMPT "serial_bf533> " /* Monitor Command Prompt */
3f0606ad AL	339	#endif
	340	#else
	341	#if (BFIN_CPU == ADSP_BF531)
8db13d63	342	#define CFG_PROMPT "bf531> " /* Monitor Command Prompt */
3f0606ad	343	#elif (BFIN_CPU == ADSP_BF532)
8db13d63	344	#define CFG_PROMPT "bf532> " /* Monitor Command Prompt */
3f0606ad	345	#else
8db13d63	346	#define CFG_PROMPT "bf533> " /* Monitor Command Prompt */
3f0606ad AL	347	#endif
	348	#endif
	349
ba2351f9	350	#if defined(CONFIG_CMD_KGDB)
8db13d63	351	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
3f0606ad	352	#else
8db13d63	353	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
3f0606ad	354	#endif
8db13d63 AL	355	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	356	#define CFG_MAXARGS 16 /* max number of command args */
	357	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
3f0606ad	358
8db13d63	359	#define CONFIG_LOADS_ECHO 1
3f0606ad AL	360
	361	/*
	362	* I2C settings
	363	* By default PF2 is used as SDA and PF3 as SCL on the Stamp board
	364	*/
	365	#if (CONFIG_SOFT_I2C)
	366
8db13d63 AL	367	#define I2C_INIT (*pFIO_DIR \|= PF_SCL); asm("ssync;")
	368	#define I2C_ACTIVE (pFIO_DIR \|= PF_SDA); pFIO_INEN &= ~PF_SDA; asm("ssync;")
	369	#define I2C_TRISTATE (pFIO_DIR &= ~PF_SDA); pFIO_INEN \|= PF_SDA; asm("ssync;")
	370	#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
	371	#define I2C_SDA(bit) if(bit) { \
	372	*pFIO_FLAG_S = PF_SDA; \
	373	asm("ssync;"); \
	374	} \
	375	else { \
	376	*pFIO_FLAG_C = PF_SDA; \
	377	asm("ssync;"); \
	378	}
	379	#define I2C_SCL(bit) if(bit) { \
	380	*pFIO_FLAG_S = PF_SCL; \
	381	asm("ssync;"); \
	382	} \
	383	else { \
	384	*pFIO_FLAG_C = PF_SCL; \
	385	asm("ssync;"); \
	386	}
	387	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	388
	389	#define CFG_I2C_SPEED 50000
	390	#define CFG_I2C_SLAVE 0xFE
3f0606ad AL	391	#endif /* CONFIG_SOFT_I2C */
	392
	393	/*
	394	* Compact Flash settings
	395	*/
	396
	397	/* Enabled below option for CF support */
8db13d63	398	/* #define CONFIG_STAMP_CF 1 */
3f0606ad	399
ba2351f9	400	#if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE)
3f0606ad	401
8db13d63 AL	402	#define CONFIG_MISC_INIT_R 1
8db13d63 AL	403	#define CONFIG_DOS_PARTITION 1
3f0606ad AL	404	/*
	405	* IDE/ATA stuff
	406	*/
8db13d63 AL	407	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	408	#undef CONFIG_IDE_LED /* no led for ide supported */
	409	#undef CONFIG_IDE_RESET /* no reset for ide supported */
3f0606ad	410
8db13d63 AL	411	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
8db13d63 AL	412	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS1) / max. 1 drives per IDE bus */
3f0606ad	413
8db13d63 AL	414	#define CFG_ATA_BASE_ADDR 0x20200000
8db13d63 AL	415	#define CFG_ATA_IDE0_OFFSET 0x0000
3f0606ad	416
8db13d63 AL	417	#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
	418	#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
	419	#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
3f0606ad	420
8db13d63	421	#define CFG_ATA_STRIDE 2
3f0606ad AL	422	#endif
	423
	424	/*
	425	* Miscellaneous configurable options
	426	*/
	427
8db13d63	428	#define CFG_HZ 1000 /* 1ms time tick */
3f0606ad	429
8db13d63	430	#define CFG_BOOTM_LEN 0x4000000/* Large Image Length, set to 64 Meg */
3f0606ad	431
8db13d63	432	#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
3f0606ad AL	433
	434	#define CONFIG_SPI
	435
	436	#ifdef CONFIG_VIDEO
	437	#if (CONFIG_VIDEO)
8db13d63 AL	438	#define CONFIG_SPLASH_SCREEN 1
8db13d63 AL	439	#define CONFIG_SILENT_CONSOLE 1
3f0606ad AL	440	#else
	441	#undef CONFIG_VIDEO
	442	#endif
	443	#endif
	444
	445	/*
	446	* FLASH organization and environment definitions
	447	*/
8db13d63	448	#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */
3f0606ad AL	449
3f0606ad AL	450	/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
8db13d63 AL	451	/*#define AMGCTLVAL (AMBEN_P0 \| AMBEN_P1 \| AMBEN_P2 \| AMCKEN)
	452	#define AMBCTL0VAL (B1WAT_11 \| B1RAT_11 \| B1HT_3 \| B1ST_4 \| B1TT_4 \| B1RDYPOL \| \
	453	B1RDYEN \| B0WAT_11 \| B0RAT_11 \| B0HT_3 \| B0ST_4 \| B0TT_4 \| B0RDYPOL \| B0RDYEN)
	454	#define AMBCTL1VAL (B3WAT_9 \| B3RAT_9 \| B3HT_2 \| B3ST_3 \| B3TT_4 \| B3RDYPOL \| \
	455	B3RDYEN \| B2WAT_9 \| B2RAT_9 \| B2HT_2 \| B2ST_4 \| B2TT_4 \| B2RDYPOL \| B2RDYEN)
3f0606ad	456	*/
8db13d63 AL	457	#define AMGCTLVAL 0xFF
	458	#define AMBCTL0VAL 0xBBC3BBC3
	459	#define AMBCTL1VAL 0x99B39983
	460	#define CF_AMBCTL1VAL 0x99B3ffc2
3f0606ad AL	461
	462	#ifdef CONFIG_VDSP
	463	#define ET_EXEC_VDSP 0x8
	464	#define SHT_STRTAB_VDSP 0x1
	465	#define ELFSHDRSIZE_VDSP 0x2C
	466	#define VDSP_ENTRY_ADDR 0xFFA00000
	467	#endif
	468
3f0606ad	469	#endif