[people/ms/u-boot.git] / include / configs / bf537-stamp.h

/*
 * U-boot - Configuration file for BF537 STAMP board
 */

#ifndef __CONFIG_BF537_H__
#define __CONFIG_BF537_H__

#include <asm/blackfin-config-pre.h>

#define CONFIG_SYS_LONGHELP		1
#define CONFIG_CMDLINE_EDITING	1
#define CONFIG_BAUDRATE		57600
/* Set default serial console for bf537 */
#define CONFIG_UART_CONSOLE	0
#define CONFIG_BOOTDELAY	5
/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
/*#define CONFIG_BF537_STAMP_LEDCMD	1*/

#define CONFIG_PANIC_HANG 1

#define CONFIG_BFIN_CPU	bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS

#define CONFIG_BFIN_MAC

/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
#define CONFIG_DCACHE_ON

/* Define if want to do post memory test */
#undef CONFIG_POST_TEST

#define CONFIG_RTC_BFIN		1
#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */

/* CONFIG_CLKIN_HZ is any value in Hz				*/
#define CONFIG_CLKIN_HZ		25000000
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
/*						    1=CLKIN/2	*/
#define CONFIG_CLKIN_HALF	0
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
/*						    1=bypass PLL*/
#define CONFIG_PLL_BYPASS	0
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	*/
/* Values can range from 1-64					*/
#define CONFIG_VCO_MULT			20
/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
/* Values can be 1, 2, 4, or 8 ONLY				*/
#define CONFIG_CCLK_DIV			1
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
/* Values can range from 1-15					*/
#define CONFIG_SCLK_DIV			5
/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
/* Values can range from 2-65535				*/
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
#define CONFIG_SPI_BAUD			2
#define CONFIG_SPI_BAUD_INITBLOCK	4

#if ( CONFIG_CLKIN_HALF == 0 )
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
#else
#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
#endif

#if (CONFIG_PLL_BYPASS == 0)
#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
#else
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
#endif

#define CONFIG_MEM_SIZE			64	/* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH		10	/* 8, 9, 10, 11 */
#define CONFIG_MEM_MT48LC32M8A2_75	1

#define CONFIG_LOADS_ECHO		1

/*
 * rarpb, bootp or dhcp commands will perform only a
 * configuration lookup from the BOOTP/DHCP server
 * but not try to load any image using TFTP
 */
#define CONFIG_SYS_AUTOLOAD			"no"

/*
 * Network Settings
 */
/* network support */
#ifdef CONFIG_BFIN_MAC
#define CONFIG_IPADDR		192.168.0.15
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_GATEWAYIP	192.168.0.1
#define CONFIG_SERVERIP		192.168.0.2
#define CONFIG_HOSTNAME		BF537
#endif

#define CONFIG_ROOTPATH		/romfs
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */

#define CONFIG_SYS_LONGHELP		1
#define CONFIG_BOOTDELAY	5
#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
#define CONFIG_BOOTCOMMAND	"run ramboot"

#if defined(CONFIG_POST_TEST)
/* POST support */
#define CONFIG_POST		( CONFIG_SYS_POST_MEMORY | \
				  CONFIG_SYS_POST_UART	  | \
				  CONFIG_SYS_POST_FLASH  | \
				  CONFIG_SYS_POST_ETHER  | \
				  CONFIG_SYS_POST_LED	  | \
				  CONFIG_SYS_POST_BUTTON)
#else
#undef CONFIG_POST
#endif

#ifdef CONFIG_POST
#define FLASH_START_POST_BLOCK	11	/* Should > = 11 */
#define FLASH_END_POST_BLOCK	71	/* Should < = 71 */
#endif

/* CF-CARD IDE-HDD Support */

/* #define CONFIG_BFIN_TRUE_IDE */	/* Add CF flash card support */
/* #define CONFIG_BFIN_CF_IDE */	/* Add CF flash card support */
/* #define CONFIG_BFIN_HDD_IDE */	/* Add IDE Disk Drive (HDD) support */

#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
# define CONFIG_BFIN_IDE	1
#endif

/*#define CONFIG_BF537_NAND */		/* Add nand flash support */

#define CONFIG_NETCONSOLE	1
#define CONFIG_NET_MULTI	1

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_DATE

#ifndef CONFIG_BFIN_MAC
#undef CONFIG_CMD_NET
#else
#define CONFIG_CMD_PING
#endif

#if defined(CONFIG_BFIN_CF_IDE) \
	|| defined(CONFIG_BFIN_HDD_IDE) \
	|| defined(CONFIG_BFIN_TRUE_IDE)
#define CONFIG_CMD_IDE
#endif

#define CONFIG_CMD_DHCP

#if defined(CONFIG_POST)
#define CONFIG_CMD_DIAG
#endif

#ifdef CONFIG_BF537_NAND
#define CONFIG_CMD_NAND
#endif


#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
#define CONFIG_LOADADDR	0x1000000

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
	"nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
	"addip=setenv bootargs $(bootargs) "			\
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
	":$(hostname):eth0:off\0"				\
	"ramboot=tftpboot $(loadaddr) linux;"			\
	"run ramargs;run addip;bootelf\0"			\
	"nfsboot=tftpboot $(loadaddr) linux;"			\
	"run nfsargs;run addip;bootelf\0"			\
	"flashboot=bootm 0x20100000\0"				\
	"update=tftpboot $(loadaddr) u-boot.bin;"		\
	"protect off 0x20000000 0x2007FFFF;"			\
	"erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0"	\
	""

#define	CONFIG_SYS_PROMPT		"bfin> "	/* Monitor Command Prompt */

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
#else
#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024*1024)
#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START	0x0	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024*1024)	/* 1 ... 63 MB in DRAM */
#define	CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR	/* default load address */
#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 10 ms ticks */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
#define	CONFIG_SYS_SDRAM_BASE		0x00000000

#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver */
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	71	/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */

#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_GBL_DATA_SIZE	0x4000
#define CONFIG_SYS_GBL_DATA_ADDR	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_STACKBASE	(CONFIG_SYS_GBL_DATA_ADDR  - 4)

#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_EEPROM	1
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_HEADER		(CONFIG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
#else
#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		0x20004000
#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#endif
#define CONFIG_ENV_SIZE		0x2000
#define	CONFIG_ENV_SECT_SIZE	0x2000	/* Total Size of Environment Sector */
#define ENV_IS_EMBEDDED

/* JFFS Partition offset set  */
#define CONFIG_SYS_JFFS2_FIRST_BANK	0
#define CONFIG_SYS_JFFS2_NUM_BANKS	1
/* 512k reserved for u-boot */
#define CONFIG_SYS_JFFS2_FIRST_SECTOR	15

#define CONFIG_SPI

/*
 * Stack sizes
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */

#define POLL_MODE		1
#define FLASH_TOT_SECT		71
#define FLASH_SIZE		0x400000
#define CONFIG_SYS_FLASH_SIZE		0x400000

/*
 * Board NAND Infomation
 */

#define CONFIG_SYS_NAND_ADDR		0x20212000
#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_NAND_ADDR
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define SECTORSIZE		512
#define ADDR_COLUMN		1
#define ADDR_PAGE		2
#define ADDR_COLUMN_PAGE	3
#define NAND_ChipID_UNKNOWN	0x00
#define NAND_MAX_FLOORS		1
#define NAND_MAX_CHIPS		1
#define BFIN_NAND_READY		PF3

#define NAND_WAIT_READY(nand)			\
	do {					\
		int timeout = 0;		\
		while(!(*pPORTFIO & PF3))	\
			if (timeout++ > 100000)	\
				break;		\
	} while (0)

#define BFIN_NAND_CLE		(1<<2)	/* A2 -> Command Enable */
#define BFIN_NAND_ALE		(1<<1)	/* A1 -> Address Enable */

#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))

/*
 * Initialize PSD4256 registers for using I2C
 */
#define CONFIG_MISC_INIT_R

#define CONFIG_SYS_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */

/*
 * I2C settings
 * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
 */
/* #define CONFIG_SOFT_I2C	1*/	/* I2C bit-banged */
#define CONFIG_HARD_I2C		1	/* I2C TWI */
#if defined CONFIG_HARD_I2C
#define CONFIG_TWICLK_KHZ	50
#endif

#define CONFIG_EBIU_SDRRC_VAL  0x306
#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
#define CONFIG_EBIU_SDBCTL_VAL 0x25

#define CONFIG_EBIU_AMGCTL_VAL		0xFF
#define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0

#if defined CONFIG_SOFT_I2C
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PF_SCL			PF0
#define PF_SDA			PF1

#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
#define I2C_SDA(bit)		if(bit) { \
					*pFIO_FLAG_S = PF_SDA; \
					asm("ssync;"); \
					} \
				else    { \
					*pFIO_FLAG_C = PF_SDA; \
					asm("ssync;"); \
					}
#define I2C_SCL(bit)		if(bit) { \
					*pFIO_FLAG_S = PF_SCL; \
					asm("ssync;"); \
					} \
				else    { \
					*pFIO_FLAG_C = PF_SCL; \
					asm("ssync;"); \
					}
#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
#endif

#define CONFIG_SYS_I2C_SPEED		50000
#define CONFIG_SYS_I2C_SLAVE		0xFE

/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
/* #define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
#define AMBCTL0VAL		(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
				~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
#define AMBCTL1VAL		(B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
				B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
*/

#define AMGCTLVAL		0xFF
#define AMBCTL0VAL		0x7BB07BB0
#define AMBCTL1VAL		0xFFC27BB0

#if defined(CONFIG_BFIN_IDE)

#define CONFIG_DOS_PARTITION	1
/*
 * IDE/ATA stuff
 */
#undef  CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
#undef  CONFIG_IDE_LED		/* no led for ide supported */
#undef  CONFIG_IDE_RESET	/* no reset for ide supported */

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses */
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1)	/* max. 1 drives per IDE bus */

#undef  AMBCTL1VAL
#define AMBCTL1VAL		0xFFC3FFC3

#define CONFIG_CF_ATASEL_DIS	0x20311800
#define CONFIG_CF_ATASEL_ENA	0x20311802

#if defined(CONFIG_BFIN_TRUE_IDE)
/*
 * Note that these settings aren't for the most part used in include/ata.h
 * when all of the ATA registers are setup
 */
#define CONFIG_SYS_ATA_BASE_ADDR	0x2031C000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* Offset for alternate registers */
#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.Ax */
#endif				/* CONFIG_BFIN_TRUE_IDE */

#if defined(CONFIG_BFIN_CF_IDE)	/* USE CompactFlash Storage Card in the common memory space */
#define CONFIG_SYS_ATA_BASE_ADDR	0x20211800
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x000E	/* Offset for alternate registers */
#define CONFIG_SYS_ATA_STRIDE		1	/* CF.A0 --> Blackfin.Ax */
#endif				/* CONFIG_BFIN_CF_IDE */

#if defined(CONFIG_BFIN_HDD_IDE)	/* USE TRUE IDE */
#define CONFIG_SYS_ATA_BASE_ADDR	0x20314000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* Offset for alternate registers */
#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A1 */

#undef  CONFIG_SCLK_DIV
#define CONFIG_SCLK_DIV		8
#endif				/* CONFIG_BFIN_HDD_IDE */

#endif				/*CONFIG_BFIN_IDE */

#include <asm/blackfin-config-post.h>

#endif
Commit	Line	Data
26bf7dec AL	1	/*
	2	* U-boot - Configuration file for BF537 STAMP board
	3	*/
	4
	5	#ifndef __CONFIG_BF537_H__
	6	#define __CONFIG_BF537_H__
	7
f7ce12cb MF	8	#include <asm/blackfin-config-pre.h>
f7ce12cb MF	9
6d0f6bcf	10	#define CONFIG_SYS_LONGHELP 1
26bf7dec AL	11	#define CONFIG_CMDLINE_EDITING 1
	12	#define CONFIG_BAUDRATE 57600
	13	/* Set default serial console for bf537 */
	14	#define CONFIG_UART_CONSOLE 0
26bf7dec AL	15	#define CONFIG_BOOTDELAY 5
	16	/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
	17	/#define CONFIG_BF537_STAMP_LEDCMD 1/
	18
26bf7dec AL	19	#define CONFIG_PANIC_HANG 1
26bf7dec AL	20
f7ce12cb	21	#define CONFIG_BFIN_CPU bf537-0.2
9171fc81 MF	22	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
9171fc81 MF	23
f7ce12cb	24	#define CONFIG_BFIN_MAC
26bf7dec AL	25
	26	/* This sets the default state of the cache on U-Boot's boot */
	27	#define CONFIG_ICACHE_ON
	28	#define CONFIG_DCACHE_ON
	29
	30	/* Define if want to do post memory test */
	31	#undef CONFIG_POST_TEST
	32
26bf7dec AL	33	#define CONFIG_RTC_BFIN 1
	34	#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
	35
	36	/* CONFIG_CLKIN_HZ is any value in Hz */
	37	#define CONFIG_CLKIN_HZ 25000000
	38	/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
	39	/* 1=CLKIN/2 */
	40	#define CONFIG_CLKIN_HALF 0
	41	/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
	42	/* 1=bypass PLL*/
	43	#define CONFIG_PLL_BYPASS 0
	44	/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
	45	/* Values can range from 1-64 */
	46	#define CONFIG_VCO_MULT 20
	47	/* CONFIG_CCLK_DIV controls what the core clock divider is */
	48	/* Values can be 1, 2, 4, or 8 ONLY */
	49	#define CONFIG_CCLK_DIV 1
	50	/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
	51	/* Values can range from 1-15 */
	52	#define CONFIG_SCLK_DIV 5
	53	/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
	54	/* Values can range from 2-65535 */
	55	/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
	56	#define CONFIG_SPI_BAUD 2
26bf7dec	57	#define CONFIG_SPI_BAUD_INITBLOCK 4
26bf7dec AL	58
	59	#if ( CONFIG_CLKIN_HALF == 0 )
	60	#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
	61	#else
	62	#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
	63	#endif
	64
	65	#if (CONFIG_PLL_BYPASS == 0)
	66	#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
	67	#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
	68	#else
	69	#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
	70	#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
	71	#endif
	72
26bf7dec AL	73	#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
	74	#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
	75	#define CONFIG_MEM_MT48LC32M8A2_75 1
	76
	77	#define CONFIG_LOADS_ECHO 1
	78
	79	/*
	80	* rarpb, bootp or dhcp commands will perform only a
	81	* configuration lookup from the BOOTP/DHCP server
	82	* but not try to load any image using TFTP
	83	*/
6d0f6bcf	84	#define CONFIG_SYS_AUTOLOAD "no"
26bf7dec AL	85
	86	/*
	87	* Network Settings
	88	*/
	89	/* network support */
f7ce12cb	90	#ifdef CONFIG_BFIN_MAC
26bf7dec AL	91	#define CONFIG_IPADDR 192.168.0.15
	92	#define CONFIG_NETMASK 255.255.255.0
	93	#define CONFIG_GATEWAYIP 192.168.0.1
	94	#define CONFIG_SERVERIP 192.168.0.2
	95	#define CONFIG_HOSTNAME BF537
	96	#endif
	97
	98	#define CONFIG_ROOTPATH /romfs
	99	/* Uncomment next line to use fixed MAC address */
	100	/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
	101	/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
	102
6d0f6bcf	103	#define CONFIG_SYS_LONGHELP 1
26bf7dec AL	104	#define CONFIG_BOOTDELAY 5
26bf7dec AL	105	#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
53677ef1	106	#define CONFIG_BOOTCOMMAND "run ramboot"
26bf7dec	107
9171fc81	108	#if defined(CONFIG_POST_TEST)
26bf7dec	109	/* POST support */
6d0f6bcf JCPV	110	#define CONFIG_POST ( CONFIG_SYS_POST_MEMORY \| \
	111	CONFIG_SYS_POST_UART \| \
	112	CONFIG_SYS_POST_FLASH \| \
	113	CONFIG_SYS_POST_ETHER \| \
	114	CONFIG_SYS_POST_LED \| \
	115	CONFIG_SYS_POST_BUTTON)
26bf7dec AL	116	#else
	117	#undef CONFIG_POST
	118	#endif
	119
	120	#ifdef CONFIG_POST
26bf7dec AL	121	#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
26bf7dec AL	122	#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
26bf7dec AL	123	#endif
	124
	125	/* CF-CARD IDE-HDD Support */
	126
	127	/* #define CONFIG_BFIN_TRUE_IDE / / Add CF flash card support */
	128	/* #define CONFIG_BFIN_CF_IDE / / Add CF flash card support */
	129	/* #define CONFIG_BFIN_HDD_IDE / / Add IDE Disk Drive (HDD) support */
	130
	131	#if defined(CONFIG_BFIN_CF_IDE) \|\| defined(CONFIG_BFIN_HDD_IDE) \|\| defined(CONFIG_BFIN_TRUE_IDE)
	132	# define CONFIG_BFIN_IDE 1
26bf7dec AL	133	#endif
	134
	135	/#define CONFIG_BF537_NAND / /* Add nand flash support */
	136
26bf7dec AL	137	#define CONFIG_NETCONSOLE 1
	138	#define CONFIG_NET_MULTI 1
	139
079a136c JL	140	/*
	141	* BOOTP options
	142	*/
	143	#define CONFIG_BOOTP_BOOTFILESIZE
	144	#define CONFIG_BOOTP_BOOTPATH
	145	#define CONFIG_BOOTP_GATEWAY
	146	#define CONFIG_BOOTP_HOSTNAME
	147
	148
ba2351f9 JL	149	/*
	150	* Command line configuration.
	151	*/
	152	#include <config_cmd_default.h>
	153
ba2351f9 JL	154	#define CONFIG_CMD_ELF
	155	#define CONFIG_CMD_I2C
	156	#define CONFIG_CMD_CACHE
	157	#define CONFIG_CMD_JFFS2
	158	#define CONFIG_CMD_EEPROM
	159	#define CONFIG_CMD_DATE
	160
f7ce12cb	161	#ifndef CONFIG_BFIN_MAC
ba2351f9	162	#undef CONFIG_CMD_NET
26bf7dec	163	#else
ba2351f9 JL	164	#define CONFIG_CMD_PING
	165	#endif
	166
	167	#if defined(CONFIG_BFIN_CF_IDE) \
	168	\|\| defined(CONFIG_BFIN_HDD_IDE) \
	169	\|\| defined(CONFIG_BFIN_TRUE_IDE)
	170	#define CONFIG_CMD_IDE
26bf7dec AL	171	#endif
26bf7dec AL	172
ba2351f9	173	#define CONFIG_CMD_DHCP
af075ee9 JL	174
	175	#if defined(CONFIG_POST)
	176	#define CONFIG_CMD_DIAG
	177	#endif
ba2351f9 JL	178
	179	#ifdef CONFIG_BF537_NAND
	180	#define CONFIG_CMD_NAND
26bf7dec AL	181	#endif
26bf7dec AL	182
ba2351f9	183
26bf7dec AL	184	#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
	185	#define CONFIG_LOADADDR 0x1000000
	186
26bf7dec AL	187	#define CONFIG_EXTRA_ENV_SETTINGS \
	188	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	189	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	190	"nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
	191	"addip=setenv bootargs $(bootargs) " \
	192	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	193	":$(hostname):eth0:off\0" \
	194	"ramboot=tftpboot $(loadaddr) linux;" \
	195	"run ramargs;run addip;bootelf\0" \
	196	"nfsboot=tftpboot $(loadaddr) linux;" \
	197	"run nfsargs;run addip;bootelf\0" \
	198	"flashboot=bootm 0x20100000\0" \
	199	"update=tftpboot $(loadaddr) u-boot.bin;" \
	200	"protect off 0x20000000 0x2007FFFF;" \
	201	"erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0" \
	202	""
26bf7dec	203
6d0f6bcf	204	#define CONFIG_SYS_PROMPT "bfin> " /* Monitor Command Prompt */
26bf7dec	205
ba2351f9	206	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	207	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
26bf7dec	208	#else
6d0f6bcf	209	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
26bf7dec	210	#endif
6d0f6bcf JCPV	211	#define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024)
	212	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	213	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	214	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	215	#define CONFIG_SYS_MEMTEST_START 0x0 /* memtest works on */
	216	#define CONFIG_SYS_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 10241024) / 1 ... 63 MB in DRAM */
	217	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* default load address */
	218	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 10 ms ticks */
	219	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	220	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	221
	222	#define CONFIG_SYS_FLASH_BASE 0x20000000
	223	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	224	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
6d0f6bcf JCPV	225	#define CONFIG_SYS_FLASH_PROTECTION
	226	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	227	#define CONFIG_SYS_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
	228
	229	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	230	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
	231	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	232	#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
	233	#define CONFIG_SYS_GBL_DATA_SIZE 0x4000
	234	#define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
	235	#define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
26bf7dec	236
9171fc81	237	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
bb1f8b4f	238	#define CONFIG_ENV_IS_IN_EEPROM 1
0e8d1586 JCPV	239	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	240	#define CONFIG_ENV_HEADER (CONFIG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
9171fc81	241	#else
5a1aceb0	242	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	243	#define CONFIG_ENV_ADDR 0x20004000
6d0f6bcf	244	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
26bf7dec	245	#endif
0e8d1586 JCPV	246	#define CONFIG_ENV_SIZE 0x2000
0e8d1586 JCPV	247	#define CONFIG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
26bf7dec	248	#define ENV_IS_EMBEDDED
26bf7dec AL	249
26bf7dec AL	250	/* JFFS Partition offset set */
6d0f6bcf JCPV	251	#define CONFIG_SYS_JFFS2_FIRST_BANK 0
6d0f6bcf JCPV	252	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
26bf7dec	253	/* 512k reserved for u-boot */
6d0f6bcf	254	#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
26bf7dec AL	255
	256	#define CONFIG_SPI
	257
	258	/*
	259	* Stack sizes
	260	*/
	261	#define CONFIG_STACKSIZE (1281024) / regular stack */
	262
	263	#define POLL_MODE 1
	264	#define FLASH_TOT_SECT 71
	265	#define FLASH_SIZE 0x400000
6d0f6bcf	266	#define CONFIG_SYS_FLASH_SIZE 0x400000
26bf7dec AL	267
	268	/*
	269	* Board NAND Infomation
	270	*/
	271
6d0f6bcf JCPV	272	#define CONFIG_SYS_NAND_ADDR 0x20212000
	273	#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND_ADDR
	274	#define CONFIG_SYS_MAX_NAND_DEVICE 1
26bf7dec AL	275	#define SECTORSIZE 512
	276	#define ADDR_COLUMN 1
	277	#define ADDR_PAGE 2
	278	#define ADDR_COLUMN_PAGE 3
	279	#define NAND_ChipID_UNKNOWN 0x00
	280	#define NAND_MAX_FLOORS 1
	281	#define NAND_MAX_CHIPS 1
	282	#define BFIN_NAND_READY PF3
	283
53677ef1 WD	284	#define NAND_WAIT_READY(nand) \
	285	do { \
	286	int timeout = 0; \
	287	while(!(*pPORTFIO & PF3)) \
26bf7dec AL	288	if (timeout++ > 100000) \
	289	break; \
	290	} while (0)
	291
	292	#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
	293	#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
	294
	295	#define WRITE_NAND_COMMAND(d, adr) do{ (volatile __u8 )((unsigned long)adr \| BFIN_NAND_CLE) = (__u8)(d); } while(0)
	296	#define WRITE_NAND_ADDRESS(d, adr) do{ (volatile __u8 )((unsigned long)adr \| BFIN_NAND_ALE) = (__u8)(d); } while(0)
	297	#define WRITE_NAND(d, adr) do{ (volatile __u8 )((unsigned long)adr) = (__u8)d; } while(0)
	298	#define READ_NAND(adr) ((volatile unsigned char)((volatile __u8 )(unsigned long)adr))
	299
	300	/*
	301	* Initialize PSD4256 registers for using I2C
	302	*/
	303	#define CONFIG_MISC_INIT_R
	304
6d0f6bcf	305	#define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
26bf7dec AL	306
	307	/*
	308	* I2C settings
	309	* By default PF1 is used as SDA and PF0 as SCL on the Stamp board
	310	*/
	311	/* #define CONFIG_SOFT_I2C 1/ / I2C bit-banged */
	312	#define CONFIG_HARD_I2C 1 /* I2C TWI */
	313	#if defined CONFIG_HARD_I2C
	314	#define CONFIG_TWICLK_KHZ 50
	315	#endif
	316
9171fc81 MF	317	#define CONFIG_EBIU_SDRRC_VAL 0x306
	318	#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
	319	#define CONFIG_EBIU_SDBCTL_VAL 0x25
	320
	321	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	322	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
	323	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
	324
26bf7dec AL	325	#if defined CONFIG_SOFT_I2C
	326	/*
	327	* Software (bit-bang) I2C driver configuration
	328	*/
	329	#define PF_SCL PF0
	330	#define PF_SDA PF1
	331
	332	#define I2C_INIT (*pFIO_DIR \|= PF_SCL); asm("ssync;")
	333	#define I2C_ACTIVE (pFIO_DIR \|= PF_SDA); pFIO_INEN &= ~PF_SDA; asm("ssync;")
	334	#define I2C_TRISTATE (pFIO_DIR &= ~PF_SDA); pFIO_INEN \|= PF_SDA; asm("ssync;")
	335	#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
	336	#define I2C_SDA(bit) if(bit) { \
	337	*pFIO_FLAG_S = PF_SDA; \
	338	asm("ssync;"); \
	339	} \
	340	else { \
	341	*pFIO_FLAG_C = PF_SDA; \
	342	asm("ssync;"); \
	343	}
	344	#define I2C_SCL(bit) if(bit) { \
	345	*pFIO_FLAG_S = PF_SCL; \
	346	asm("ssync;"); \
	347	} \
	348	else { \
	349	*pFIO_FLAG_C = PF_SCL; \
	350	asm("ssync;"); \
	351	}
	352	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	353	#endif
	354
6d0f6bcf JCPV	355	#define CONFIG_SYS_I2C_SPEED 50000
6d0f6bcf JCPV	356	#define CONFIG_SYS_I2C_SLAVE 0xFE
26bf7dec AL	357
	358	/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
	359	/* #define AMGCTLVAL (AMBEN_P0 \| AMBEN_P1 \| AMBEN_P2 \| AMCKEN)
	360	#define AMBCTL0VAL (B1WAT_7 \| B1RAT_11 \| B1HT_2 \| B1ST_3 \| B1TT_4 \| ~B1RDYPOL \| \
	361	~B1RDYEN \| B0WAT_7 \| B0RAT_11 \| B0HT_2 \| B0ST_3 \| B0TT_4 \| ~B0RDYPOL \| ~B0RDYEN)
	362	#define AMBCTL1VAL (B3WAT_2 \| B3RAT_2 \| B3HT_1 \| B3ST_1 \| B3TT_4 \| B3RDYPOL \| ~B3RDYEN \| \
	363	B2WAT_7 \| B2RAT_11 \| B2HT_2 \| B2ST_3 \| B2TT_4 \| ~B2RDYPOL \| ~B2RDYEN)
	364	*/
	365
	366	#define AMGCTLVAL 0xFF
	367	#define AMBCTL0VAL 0x7BB07BB0
	368	#define AMBCTL1VAL 0xFFC27BB0
	369
26bf7dec AL	370	#if defined(CONFIG_BFIN_IDE)
	371
	372	#define CONFIG_DOS_PARTITION 1
	373	/*
	374	* IDE/ATA stuff
	375	*/
	376	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	377	#undef CONFIG_IDE_LED /* no led for ide supported */
	378	#undef CONFIG_IDE_RESET /* no reset for ide supported */
	379
6d0f6bcf JCPV	380	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
6d0f6bcf JCPV	381	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS1) / max. 1 drives per IDE bus */
26bf7dec AL	382
	383	#undef AMBCTL1VAL
	384	#define AMBCTL1VAL 0xFFC3FFC3
	385
	386	#define CONFIG_CF_ATASEL_DIS 0x20311800
	387	#define CONFIG_CF_ATASEL_ENA 0x20311802
	388
	389	#if defined(CONFIG_BFIN_TRUE_IDE)
	390	/*
	391	* Note that these settings aren't for the most part used in include/ata.h
	392	* when all of the ATA registers are setup
	393	*/
6d0f6bcf JCPV	394	#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
	395	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	396	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
	397	#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
	398	#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
	399	#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
26bf7dec AL	400	#endif /* CONFIG_BFIN_TRUE_IDE */
	401
	402	#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
6d0f6bcf JCPV	403	#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
	404	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	405	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
	406	#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
	407	#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
	408	#define CONFIG_SYS_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
26bf7dec AL	409	#endif /* CONFIG_BFIN_CF_IDE */
	410
	411	#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
6d0f6bcf JCPV	412	#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
	413	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	414	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
	415	#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
	416	#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
	417	#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
26bf7dec AL	418
	419	#undef CONFIG_SCLK_DIV
	420	#define CONFIG_SCLK_DIV 8
	421	#endif /* CONFIG_BFIN_HDD_IDE */
	422
	423	#endif /CONFIG_BFIN_IDE /
	424
9171fc81 MF	425	#include <asm/blackfin-config-post.h>
9171fc81 MF	426
26bf7dec	427	#endif