[people/ms/u-boot.git] / include / configs / blackstamp.h

/*
 * U-boot - Configuration file for BlackStamp board
 * Configuration by Ben Matthews for UR LLE using bf533-stamp.h
 * as a template
 * See http://blackfin.uclinux.org/gf/project/blackstamp/
 */

#ifndef __CONFIG_BLACKSTAMP_H__
#define __CONFIG_BLACKSTAMP_H__

#include <asm/config-pre.h>

/*
 * Debugging: Set these options if you're having problems
 */
/*
 * #define CONFIG_DEBUG_EARLY_SERIAL
 * #define DEBUG
 * #define CONFIG_DEBUG_DUMP
 * #define CONFIG_DEBUG_DUMP_SYMS
*/
#define CONFIG_PANIC_HANG 0

/* CPU Options
 * Be sure to set the Silicon Revision Correctly
 */
#define CONFIG_BFIN_CPU		bf532-0.5
#define CONFIG_BFIN_BOOT_MODE	BFIN_BOOT_SPI_MASTER

/*
 * Board settings
 */
#define CONFIG_SMC91111	1
#define CONFIG_SMC91111_BASE	0x20300300

/* FLASH/ETHERNET uses the same address range
 * Depending on what you have the CPLD doing
 * this probably isn't needed
 */
#define SHARED_RESOURCES	1

/* Is I2C bit-banged? */

/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			16
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			3

/*
 * Network settings
 */

#ifdef CONFIG_SMC91111
#define CONFIG_IPADDR		192.168.0.15
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_GATEWAYIP	192.168.0.1
#define CONFIG_SERVERIP		192.168.0.2
#define CONFIG_HOSTNAME		blackstamp
#define CONFIG_ROOTPATH		"/checkout/uClinux-dist/romfs"
#define CONFIG_SYS_AUTOLOAD		"no"
#endif

#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x40000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x40000

/*
 * SDRAM settings & memory map
 */

#define CONFIG_MEM_SIZE		64	/* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH	10	/* 8, 9, 10, 11    */

#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
#define CONFIG_SYS_MALLOC_LEN	(384 << 10)

/*
 * Command settings
 */

#define CONFIG_SYS_LONGHELP		1
#define CONFIG_CMDLINE_EDITING	1
#define CONFIG_AUTO_COMPLETE	1
#define CONFIG_ENV_OVERWRITE	1

#include <config_cmd_default.h>

#ifdef CONFIG_SMC91111
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_PING
#else
#endif

#ifdef CONFIG_SYS_I2C_SOFT
# define CONFIG_CMD_I2C
#endif

#define CONFIG_CMD_BOOTLDR
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_CPLBINFO
#define CONFIG_CMD_DATE
#define CONFIG_CMD_SF
#define CONFIG_CMD_ELF

#define CONFIG_BOOTDELAY     5
#define CONFIG_BOOTCOMMAND   "run ramboot"
#define CONFIG_BOOTARGS \
	"root=/dev/mtdblock0 rw " \
	"clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
	"earlyprintk=" \
		"serial," \
		"uart" __stringify(CONFIG_UART_CONSOLE) "," \
		__stringify(CONFIG_BAUDRATE) " " \
	"console=ttyBF0," __stringify(CONFIG_BAUDRATE)

#if defined(CONFIG_CMD_NET)
# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#  define UBOOT_ENV_FILE "u-boot.bin"
# else
#  define UBOOT_ENV_FILE "u-boot.ldr"
# endif
# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#  ifdef CONFIG_SPI
#   define UBOOT_ENV_UPDATE \
		"eeprom write $(loadaddr) 0x0 $(filesize)"
#  else
#   define UBOOT_ENV_UPDATE \
		"sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
		"sf erase 0 0x40000;" \
		"sf write $(loadaddr) 0 $(filesize)"
#  endif
# else
#  define UBOOT_ENV_UPDATE \
		"protect off 0x20000000 0x2003FFFF;" \
		"erase 0x20000000 0x2003FFFF;" \
		"cp.b $(loadaddr) 0x20000000 $(filesize)"
# endif
# define NETWORK_ENV_SETTINGS \
	"ubootfile=" UBOOT_ENV_FILE "\0" \
	"update=" \
		"tftp $(loadaddr) $(ubootfile);" \
		UBOOT_ENV_UPDATE \
		"\0" \
	"addip=set bootargs $(bootargs) " \
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
		   "$(hostname):eth0:off" \
		"\0" \
	"ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
	"ramboot=" \
		"tftp $(loadaddr) uImage;" \
		"run ramargs;" \
		"run addip;" \
		"bootm" \
		"\0" \
	"nfsargs=set bootargs " \
		"root=/dev/nfs rw " \
		"nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
		"\0" \
	"nfsboot=" \
		"tftp $(loadaddr) vmImage;" \
		"run nfsargs;" \
		"run addip;" \
		"bootm" \
		"\0"
#else
# define NETWORK_ENV_SETTINGS
#endif

/*
 * Console settings
 */
#define CONFIG_BAUDRATE		57600
#define CONFIG_LOADS_ECHO	1
#define CONFIG_UART_CONSOLE	0
#define CONFIG_BFIN_SERIAL

/*
 * I2C settings
 * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
 * Located on the expansion connector on pins 86/85
 * Note these pins are arbitrarily chosen because we aren't using
 * them yet. You can (and probably should) change these values!
 */
#ifdef CONFIG_SYS_I2C_SOFT
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF9
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF8
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_RTC_BFIN		1

/*
 * Serial Flash Infomation
 */
#define CONFIG_BFIN_SPI
/* For the M25P64 SCK Should be Kept < 15Mhz */
#define CONFIG_ENV_SPI_MAX_HZ	15000000
#define CONFIG_SF_DEFAULT_SPEED	15000000
#define CONFIG_SPI_FLASH_STMICRO

/*
 * FLASH organization and environment definitions
 */

#define CONFIG_EBIU_AMGCTL_VAL		0xFF
#define CONFIG_EBIU_AMBCTL0_VAL		0xBBC3BBC3
#define CONFIG_EBIU_AMBCTL1_VAL		0x99B39983
#define CONFIG_EBIU_SDRRC_VAL		0x268
#define CONFIG_EBIU_SDGCTL_VAL		0x911109

/* Even though Rev C boards have Parallel Flash
 * We aren't supporting it. Newer versions of the
 * hardware don't support Parallel Flash at all.
 */
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_JFFS2
#undef CONFIG_CMD_FLASH

#endif
Commit	Line	Data
3088189a MF	1	/*
	2	* U-boot - Configuration file for BlackStamp board
	3	* Configuration by Ben Matthews for UR LLE using bf533-stamp.h
	4	* as a template
	5	* See http://blackfin.uclinux.org/gf/project/blackstamp/
	6	*/
	7
	8	#ifndef __CONFIG_BLACKSTAMP_H__
	9	#define __CONFIG_BLACKSTAMP_H__
	10
f348ab85	11	#include <asm/config-pre.h>
3088189a MF	12
	13	/*
	14	* Debugging: Set these options if you're having problems
	15	*/
	16	/*
	17	* #define CONFIG_DEBUG_EARLY_SERIAL
	18	* #define DEBUG
	19	* #define CONFIG_DEBUG_DUMP
	20	* #define CONFIG_DEBUG_DUMP_SYMS
	21	*/
	22	#define CONFIG_PANIC_HANG 0
	23
	24	/* CPU Options
	25	* Be sure to set the Silicon Revision Correctly
	26	*/
fbcf8e8c	27	#define CONFIG_BFIN_CPU bf532-0.5
3088189a MF	28	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
	29
	30	/*
	31	* Board settings
	32	*/
7194ab80	33	#define CONFIG_SMC91111 1
3088189a MF	34	#define CONFIG_SMC91111_BASE 0x20300300
	35
	36	/* FLASH/ETHERNET uses the same address range
	37	* Depending on what you have the CPLD doing
	38	* this probably isn't needed
	39	*/
	40	#define SHARED_RESOURCES 1
	41
	42	/* Is I2C bit-banged? */
3088189a MF	43
	44	/*
	45	* Clock Settings
	46	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	47	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	48	*/
	49	/* CONFIG_CLKIN_HZ is any value in Hz */
	50	#define CONFIG_CLKIN_HZ 25000000
	51	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	52	/* 1 = CLKIN / 2 */
	53	#define CONFIG_CLKIN_HALF 0
	54	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	55	/* 1 = bypass PLL */
	56	#define CONFIG_PLL_BYPASS 0
	57	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	58	/* Values can range from 0-63 (where 0 means 64) */
	59	#define CONFIG_VCO_MULT 16
	60	/* CCLK_DIV controls the core clock divider */
	61	/* Values can be 1, 2, 4, or 8 ONLY */
	62	#define CONFIG_CCLK_DIV 1
	63	/* SCLK_DIV controls the system clock divider */
	64	/* Values can range from 1-15 */
	65	#define CONFIG_SCLK_DIV 3
	66
	67	/*
	68	* Network settings
	69	*/
	70
7194ab80	71	#ifdef CONFIG_SMC91111
3088189a MF	72	#define CONFIG_IPADDR 192.168.0.15
	73	#define CONFIG_NETMASK 255.255.255.0
	74	#define CONFIG_GATEWAYIP 192.168.0.1
	75	#define CONFIG_SERVERIP 192.168.0.2
	76	#define CONFIG_HOSTNAME blackstamp
8b3637c6	77	#define CONFIG_ROOTPATH "/checkout/uClinux-dist/romfs"
3088189a	78	#define CONFIG_SYS_AUTOLOAD "no"
3088189a MF	79	#endif
	80
	81	#define CONFIG_ENV_IS_IN_SPI_FLASH
f8bf54b4	82	#define CONFIG_ENV_OFFSET 0x40000
3088189a MF	83	#define CONFIG_ENV_SIZE 0x2000
3088189a MF	84	#define CONFIG_ENV_SECT_SIZE 0x40000
3088189a MF	85
	86	/*
	87	* SDRAM settings & memory map
	88	*/
	89
	90	#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
	91	#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
	92
	93	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
	94	#define CONFIG_SYS_MALLOC_LEN (384 << 10)
	95
	96	/*
	97	* Command settings
	98	*/
	99
	100	#define CONFIG_SYS_LONGHELP 1
	101	#define CONFIG_CMDLINE_EDITING 1
	102	#define CONFIG_AUTO_COMPLETE 1
	103	#define CONFIG_ENV_OVERWRITE 1
	104
	105	#include <config_cmd_default.h>
	106
7194ab80	107	#ifdef CONFIG_SMC91111
3088189a MF	108	# define CONFIG_CMD_DHCP
	109	# define CONFIG_CMD_PING
	110	#else
3088189a MF	111	#endif
3088189a MF	112
ea818dbb	113	#ifdef CONFIG_SYS_I2C_SOFT
3088189a MF	114	# define CONFIG_CMD_I2C
	115	#endif
	116
	117	#define CONFIG_CMD_BOOTLDR
	118	#define CONFIG_CMD_CACHE
	119	#define CONFIG_CMD_CPLBINFO
	120	#define CONFIG_CMD_DATE
	121	#define CONFIG_CMD_SF
	122	#define CONFIG_CMD_ELF
	123
	124	#define CONFIG_BOOTDELAY 5
	125	#define CONFIG_BOOTCOMMAND "run ramboot"
	126	#define CONFIG_BOOTARGS \
	127	"root=/dev/mtdblock0 rw " \
5368c55d	128	"clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
3088189a MF	129	"earlyprintk=" \
3088189a MF	130	"serial," \
5368c55d MV	131	"uart" __stringify(CONFIG_UART_CONSOLE) "," \
	132	__stringify(CONFIG_BAUDRATE) " " \
	133	"console=ttyBF0," __stringify(CONFIG_BAUDRATE)
3088189a MF	134
	135	#if defined(CONFIG_CMD_NET)
	136	# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
	137	# define UBOOT_ENV_FILE "u-boot.bin"
	138	# else
	139	# define UBOOT_ENV_FILE "u-boot.ldr"
	140	# endif
	141	# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
	142	# ifdef CONFIG_SPI
	143	# define UBOOT_ENV_UPDATE \
	144	"eeprom write $(loadaddr) 0x0 $(filesize)"
	145	# else
	146	# define UBOOT_ENV_UPDATE \
5368c55d	147	"sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
3088189a MF	148	"sf erase 0 0x40000;" \
	149	"sf write $(loadaddr) 0 $(filesize)"
	150	# endif
	151	# else
	152	# define UBOOT_ENV_UPDATE \
	153	"protect off 0x20000000 0x2003FFFF;" \
	154	"erase 0x20000000 0x2003FFFF;" \
	155	"cp.b $(loadaddr) 0x20000000 $(filesize)"
	156	# endif
	157	# define NETWORK_ENV_SETTINGS \
	158	"ubootfile=" UBOOT_ENV_FILE "\0" \
	159	"update=" \
	160	"tftp $(loadaddr) $(ubootfile);" \
	161	UBOOT_ENV_UPDATE \
	162	"\0" \
	163	"addip=set bootargs $(bootargs) " \
	164	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
	165	"$(hostname):eth0:off" \
	166	"\0" \
	167	"ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
	168	"ramboot=" \
	169	"tftp $(loadaddr) uImage;" \
	170	"run ramargs;" \
	171	"run addip;" \
	172	"bootm" \
	173	"\0" \
	174	"nfsargs=set bootargs " \
	175	"root=/dev/nfs rw " \
	176	"nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
	177	"\0" \
	178	"nfsboot=" \
	179	"tftp $(loadaddr) vmImage;" \
	180	"run nfsargs;" \
	181	"run addip;" \
	182	"bootm" \
	183	"\0"
	184	#else
	185	# define NETWORK_ENV_SETTINGS
	186	#endif
	187
	188	/*
	189	* Console settings
	190	*/
	191	#define CONFIG_BAUDRATE 57600
	192	#define CONFIG_LOADS_ECHO 1
	193	#define CONFIG_UART_CONSOLE 0
7a58eb96	194	#define CONFIG_BFIN_SERIAL
3088189a MF	195
	196	/*
	197	* I2C settings
	198	* By default PF2 is used as SDA and PF3 as SCL on the Stamp board
	199	* Located on the expansion connector on pins 86/85
	200	* Note these pins are arbitrarily chosen because we aren't using
	201	* them yet. You can (and probably should) change these values!
	202	*/
ea818dbb	203	#ifdef CONFIG_SYS_I2C_SOFT
beb60e77 MF	204	#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF9
beb60e77 MF	205	#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF8
90f002a9 MV	206	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
90f002a9 MV	207	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
3088189a MF	208	#endif
	209
	210	/*
	211	* Miscellaneous configurable options
	212	*/
	213	#define CONFIG_RTC_BFIN 1
	214
	215	/*
	216	* Serial Flash Infomation
	217	*/
	218	#define CONFIG_BFIN_SPI
f8bf54b4 MF	219	/* For the M25P64 SCK Should be Kept < 15Mhz */
	220	#define CONFIG_ENV_SPI_MAX_HZ 15000000
	221	#define CONFIG_SF_DEFAULT_SPEED 15000000
3088189a MF	222	#define CONFIG_SPI_FLASH_STMICRO
	223
	224	/*
	225	* FLASH organization and environment definitions
	226	*/
	227
	228	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	229	#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
	230	#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
	231	#define CONFIG_EBIU_SDRRC_VAL 0x268
	232	#define CONFIG_EBIU_SDGCTL_VAL 0x911109
	233
	234	/* Even though Rev C boards have Parallel Flash
	235	* We aren't supporting it. Newer versions of the
	236	* hardware don't support Parallel Flash at all.
	237	*/
	238	#define CONFIG_SYS_NO_FLASH
	239	#undef CONFIG_CMD_IMLS
	240	#undef CONFIG_CMD_JFFS2
	241	#undef CONFIG_CMD_FLASH
	242
3088189a	243	#endif