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893c04e1 HP |
1 | /* |
2 | * bur_am335x_common.h | |
3 | * | |
4 | * common parts used by B&R AM335x based boards | |
5 | * | |
3b804d94 | 6 | * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> - |
893c04e1 HP |
7 | * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com |
8 | * | |
9 | * SPDX-License-Identifier: GPL-2.0+ | |
10 | */ | |
11 | ||
12 | #ifndef __BUR_AM335X_COMMON_H__ | |
13 | #define __BUR_AM335X_COMMON_H__ | |
14 | /* ------------------------------------------------------------------------- */ | |
893c04e1 HP |
15 | #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ |
16 | ||
17 | /* Timer information */ | |
18 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
19 | #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ | |
96de041e | 20 | #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC /* enable 32kHz OSC at bootime */ |
893c04e1 HP |
21 | #define CONFIG_POWER_TPS65217 |
22 | ||
893c04e1 HP |
23 | #include <asm/arch/omap.h> |
24 | ||
25 | /* NS16550 Configuration */ | |
893c04e1 HP |
26 | #define CONFIG_SYS_NS16550_SERIAL |
27 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
28 | #define CONFIG_SYS_NS16550_CLK 48000000 | |
29 | #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ | |
893c04e1 HP |
30 | |
31 | /* Network defines */ | |
893c04e1 HP |
32 | #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ |
33 | #define CONFIG_MII /* Required in net/eth.c */ | |
893c04e1 | 34 | #define CONFIG_PHY_NATSEMI |
3b804d94 | 35 | |
893c04e1 HP |
36 | /* |
37 | * SPL related defines. The Public RAM memory map the ROM defines the | |
38 | * area between 0x402F0400 and 0x4030B800 as a download area and | |
39 | * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also | |
40 | * supports X-MODEM loading via UART, and we leverage this and then use | |
fa2f81b0 TR |
41 | * Y-MODEM to load u-boot.img, when booted over UART. We must also include |
42 | * the scratch space that U-Boot uses in SRAM. | |
893c04e1 HP |
43 | */ |
44 | #define CONFIG_SPL_TEXT_BASE 0x402F0400 | |
fa2f81b0 TR |
45 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
46 | CONFIG_SPL_TEXT_BASE) | |
893c04e1 HP |
47 | |
48 | /* | |
49 | * Since SPL did pll and ddr initialization for us, | |
50 | * we don't need to do it twice. | |
51 | */ | |
52 | #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) | |
53 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
54 | #endif /* !CONFIG_SPL_BUILD, ... */ | |
55 | /* | |
56 | * Our DDR memory always starts at 0x80000000 and U-Boot shall have | |
57 | * relocated itself to higher in memory by the time this value is used. | |
58 | */ | |
59 | #define CONFIG_SYS_LOAD_ADDR 0x80000000 | |
60 | /* | |
61 | * ---------------------------------------------------------------------------- | |
62 | * DDR information. We say (for simplicity) that we have 1 bank, | |
63 | * always, even when we have more. We always start at 0x80000000, | |
64 | * and we place the initial stack pointer in our SRAM. | |
65 | */ | |
66 | #define CONFIG_NR_DRAM_BANKS 1 | |
67 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 | |
68 | #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ | |
69 | GENERATED_GBL_DATA_SIZE) | |
70 | ||
71 | /* I2C */ | |
72 | #define CONFIG_SYS_I2C | |
73 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 | |
74 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
893c04e1 HP |
75 | |
76 | /* | |
77 | * Our platforms make use of SPL to initalize the hardware (primarily | |
78 | * memory) enough for full U-Boot to be loaded. We also support Falcon | |
79 | * Mode so that the Linux kernel can be booted directly from SPL | |
80 | * instead, if desired. We make use of the general SPL framework found | |
81 | * under common/spl/. Given our generally common memory map, we set a | |
82 | * number of related defaults and sizes here. | |
83 | */ | |
893c04e1 HP |
84 | #define CONFIG_SPL_FRAMEWORK |
85 | /* | |
86 | * Place the image at the start of the ROM defined image space. | |
87 | * We limit our size to the ROM-defined downloaded image area, and use the | |
88 | * rest of the space for stack. We load U-Boot itself into memory at | |
89 | * 0x80800000 for legacy reasons (to not conflict with older SPLs). We | |
90 | * have our BSS be placed 1MiB after this, to allow for the default | |
91 | * Linux kernel address of 0x80008000 to work, in the Falcon Mode case. | |
92 | * We have the SPL malloc pool at the end of the BSS area. | |
93 | * | |
94 | * ---------------------------------------------------------------------------- | |
95 | */ | |
893c04e1 HP |
96 | #undef CONFIG_SYS_TEXT_BASE |
97 | #define CONFIG_SYS_TEXT_BASE 0x80800000 | |
98 | #define CONFIG_SPL_BSS_START_ADDR 0x80A00000 | |
99 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ | |
100 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ | |
101 | CONFIG_SPL_BSS_MAX_SIZE) | |
102 | #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN | |
103 | ||
104 | /* General parts of the framework, required. */ | |
893c04e1 HP |
105 | |
106 | #endif /* ! __BUR_AM335X_COMMON_H__ */ |