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0f8c9768 | 1 | /* |
414eec35 | 2 | * (C) Copyright 2001-2005 |
0f8c9768 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ | |
37 | #define CONFIG_C2MON 1 /* ...on a C2MON module */ | |
38 | ||
39 | #define CONFIG_80MHz 1 /* Running at 5 * 16 = 80 MHz */ | |
40 | ||
41 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
42 | #undef CONFIG_8xx_CONS_SMC2 | |
43 | #undef CONFIG_8xx_CONS_NONE | |
44 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
45 | #if 0 | |
46 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
47 | #else | |
48 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
49 | #endif | |
50 | ||
51 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
52 | ||
32bf3d14 | 53 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
0f8c9768 WD |
54 | |
55 | #undef CONFIG_BOOTARGS | |
56 | #define CONFIG_BOOTCOMMAND \ | |
53677ef1 WD |
57 | "bootp; " \ |
58 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
59 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
0f8c9768 WD |
60 | "bootm" |
61 | ||
62 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 63 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
0f8c9768 WD |
64 | |
65 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
66 | ||
67 | #undef CONFIG_STATUS_LED /* Status LED disabled */ | |
68 | ||
69 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
70 | ||
2fd90ce5 JL |
71 | /* |
72 | * BOOTP options | |
73 | */ | |
74 | #define CONFIG_BOOTP_SUBNETMASK | |
75 | #define CONFIG_BOOTP_GATEWAY | |
76 | #define CONFIG_BOOTP_HOSTNAME | |
77 | #define CONFIG_BOOTP_BOOTPATH | |
78 | #define CONFIG_BOOTP_BOOTFILESIZE | |
79 | ||
0f8c9768 WD |
80 | |
81 | #define CONFIG_MAC_PARTITION | |
82 | #define CONFIG_DOS_PARTITION | |
83 | ||
84 | #define CONFIG_FEC_ENET 1 /* Use Fast Ethernet Controller */ | |
85 | ||
86 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
87 | ||
0f8c9768 | 88 | |
37e4f24b JL |
89 | /* |
90 | * Command line configuration. | |
91 | */ | |
92 | #include <config_cmd_default.h> | |
93 | ||
94 | #define CONFIG_CMD_DATE | |
95 | #define CONFIG_CMD_DHCP | |
96 | #define CONFIG_CMD_IDE | |
97 | #define CONFIG_CMD_NFS | |
98 | #define CONFIG_CMD_SNTP | |
99 | ||
0f8c9768 WD |
100 | |
101 | /* | |
102 | * Miscellaneous configurable options | |
103 | */ | |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
105 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
0f8c9768 | 106 | |
6d0f6bcf JCPV |
107 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
108 | #ifdef CONFIG_SYS_HUSH_PARSER | |
109 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
0f8c9768 WD |
110 | #endif |
111 | ||
37e4f24b | 112 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 113 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
0f8c9768 | 114 | #else |
6d0f6bcf | 115 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
0f8c9768 | 116 | #endif |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
118 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
119 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
0f8c9768 | 120 | |
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
122 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
0f8c9768 | 123 | |
6d0f6bcf | 124 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
0f8c9768 | 125 | |
6d0f6bcf | 126 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
0f8c9768 | 127 | |
6d0f6bcf | 128 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
0f8c9768 WD |
129 | |
130 | /* | |
131 | * Low Level Configuration Settings | |
132 | * (address mappings, register initial values, etc.) | |
133 | * You should know what you are doing if you make changes here. | |
134 | */ | |
135 | /*----------------------------------------------------------------------- | |
136 | * Internal Memory Mapped Register | |
137 | */ | |
6d0f6bcf | 138 | #define CONFIG_SYS_IMMR 0xFFF00000 |
0f8c9768 WD |
139 | |
140 | /*----------------------------------------------------------------------- | |
141 | * Definitions for initial stack pointer and data area (in DPRAM) | |
142 | */ | |
6d0f6bcf JCPV |
143 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
144 | #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
145 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
146 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
147 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
0f8c9768 WD |
148 | |
149 | /*----------------------------------------------------------------------- | |
150 | * Start addresses for the final memory configuration | |
151 | * (Set up by the startup code) | |
6d0f6bcf | 152 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
0f8c9768 | 153 | */ |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
155 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
0f8c9768 | 156 | #if defined(DEBUG) |
6d0f6bcf | 157 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
0f8c9768 | 158 | #else |
6d0f6bcf | 159 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
0f8c9768 | 160 | #endif |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
162 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
0f8c9768 WD |
163 | |
164 | /* | |
165 | * For booting Linux, the board info and command line data | |
166 | * have to be in the first 8 MB of memory, since this is | |
167 | * the maximum mapped by the Linux kernel during initialization. | |
168 | */ | |
6d0f6bcf | 169 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
0f8c9768 WD |
170 | |
171 | /*----------------------------------------------------------------------- | |
172 | * FLASH organization | |
173 | */ | |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
175 | #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ | |
0f8c9768 | 176 | |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
178 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
0f8c9768 | 179 | |
5a1aceb0 | 180 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
181 | #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
182 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
0f8c9768 WD |
183 | |
184 | /*----------------------------------------------------------------------- | |
185 | * Cache Configuration | |
186 | */ | |
6d0f6bcf | 187 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
37e4f24b | 188 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 189 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
0f8c9768 WD |
190 | #endif |
191 | ||
192 | /*----------------------------------------------------------------------- | |
193 | * SYPCR - System Protection Control 11-9 | |
194 | * SYPCR can only be written once after reset! | |
195 | *----------------------------------------------------------------------- | |
196 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
197 | */ | |
198 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 199 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
0f8c9768 WD |
200 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
201 | #else | |
6d0f6bcf | 202 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
0f8c9768 WD |
203 | #endif |
204 | ||
205 | /*----------------------------------------------------------------------- | |
206 | * SIUMCR - SIU Module Configuration 11-6 | |
207 | *----------------------------------------------------------------------- | |
208 | * PCMCIA config., multi-function pin tri-state | |
209 | */ | |
210 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf | 211 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
0f8c9768 | 212 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 213 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
0f8c9768 WD |
214 | #endif /* CONFIG_CAN_DRIVER */ |
215 | ||
216 | /*----------------------------------------------------------------------- | |
217 | * TBSCR - Time Base Status and Control 11-26 | |
218 | *----------------------------------------------------------------------- | |
219 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
220 | */ | |
6d0f6bcf | 221 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
0f8c9768 WD |
222 | |
223 | /*----------------------------------------------------------------------- | |
224 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
225 | *----------------------------------------------------------------------- | |
226 | */ | |
6d0f6bcf | 227 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
0f8c9768 WD |
228 | |
229 | /*----------------------------------------------------------------------- | |
230 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
231 | *----------------------------------------------------------------------- | |
232 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
233 | */ | |
6d0f6bcf | 234 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
0f8c9768 WD |
235 | |
236 | /*----------------------------------------------------------------------- | |
237 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
238 | *----------------------------------------------------------------------- | |
239 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
240 | * interrupt status bit | |
241 | * | |
242 | * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! | |
243 | */ | |
244 | #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ | |
6d0f6bcf | 245 | #define CONFIG_SYS_PLPRCR \ |
0f8c9768 WD |
246 | ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) |
247 | #else /* up to 50 MHz we use a 1:1 clock */ | |
6d0f6bcf | 248 | #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
0f8c9768 WD |
249 | #endif /* CONFIG_80MHz */ |
250 | ||
251 | /*----------------------------------------------------------------------- | |
252 | * SCCR - System Clock and reset Control Register 15-27 | |
253 | *----------------------------------------------------------------------- | |
254 | * Set clock output, timebase and RTC source and divider, | |
255 | * power management and some other internal clocks | |
256 | */ | |
257 | #define SCCR_MASK SCCR_EBDF11 | |
258 | #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ | |
6d0f6bcf | 259 | #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ \ |
0f8c9768 WD |
260 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
261 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
262 | SCCR_DFALCD00) | |
263 | #else /* up to 50 MHz we use a 1:1 clock */ | |
6d0f6bcf | 264 | #define CONFIG_SYS_SCCR (SCCR_TBS | \ |
0f8c9768 WD |
265 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
266 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
267 | SCCR_DFALCD00) | |
268 | #endif /* CONFIG_80MHz */ | |
269 | ||
270 | /*----------------------------------------------------------------------- | |
271 | * PCMCIA stuff | |
272 | *----------------------------------------------------------------------- | |
273 | * | |
274 | */ | |
6d0f6bcf JCPV |
275 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
276 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
277 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
278 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
279 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
280 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
281 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
282 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
0f8c9768 WD |
283 | |
284 | /*----------------------------------------------------------------------- | |
285 | * PCMCIA Power Switch | |
286 | * | |
287 | * The C2MON uses a TPS2211A PC-Card Power-Interface Switch to | |
288 | * control the voltages on the PCMCIA slot which is connected | |
289 | * to Port C (all outputs) and Port B (Over-Current Input) | |
290 | *----------------------------------------------------------------------- | |
291 | */ | |
292 | /* Output pins */ | |
293 | #define TPS2211_VCCD0 0x0002 /* PC.14 */ | |
294 | #define TPS2211_VCCD1 0x0004 /* PC.13 */ | |
295 | #define TPS2211_VPPD0 0x0008 /* PC.12 */ | |
296 | #define TPS2211_VPPD1 0x0010 /* PC.11 */ | |
297 | #define TPS2211_OUTPUTS ( TPS2211_VCCD0 | TPS2211_VCCD1 | \ | |
298 | TPS2211_VPPD0 | TPS2211_VPPD1 ) | |
299 | ||
300 | /* Input pins */ | |
301 | #define TPS2211_OC 0x00000200 /* PB.22: Over-Current */ | |
302 | #define TPS2211_INPUTS ( TPS2211_OC ) | |
303 | ||
304 | /*----------------------------------------------------------------------- | |
305 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
306 | *----------------------------------------------------------------------- | |
307 | */ | |
308 | ||
309 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
310 | ||
311 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
312 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
313 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
314 | ||
6d0f6bcf JCPV |
315 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
316 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
0f8c9768 | 317 | |
6d0f6bcf | 318 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
0f8c9768 | 319 | |
6d0f6bcf | 320 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
0f8c9768 WD |
321 | |
322 | /* Offset for data I/O */ | |
6d0f6bcf | 323 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
0f8c9768 WD |
324 | |
325 | /* Offset for normal register accesses */ | |
6d0f6bcf | 326 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
0f8c9768 WD |
327 | |
328 | /* Offset for alternate registers */ | |
6d0f6bcf | 329 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
0f8c9768 WD |
330 | |
331 | ||
332 | /*----------------------------------------------------------------------- | |
333 | * | |
334 | *----------------------------------------------------------------------- | |
335 | * | |
336 | */ | |
6d0f6bcf | 337 | #define CONFIG_SYS_DER 0 |
0f8c9768 WD |
338 | |
339 | /* | |
340 | * Init Memory Controller: | |
341 | * | |
342 | * BR0/1 and OR0/1 (FLASH) | |
343 | */ | |
344 | ||
345 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
346 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
347 | ||
348 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
349 | * restrict access enough to keep SRAM working (if any) | |
350 | * but not too much to meddle with FLASH accesses | |
351 | */ | |
6d0f6bcf JCPV |
352 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
353 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
0f8c9768 WD |
354 | |
355 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
6d0f6bcf | 356 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ |
0f8c9768 WD |
357 | OR_SCY_5_CLK | OR_EHTR) |
358 | ||
6d0f6bcf JCPV |
359 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
360 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
361 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
0f8c9768 | 362 | |
6d0f6bcf JCPV |
363 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
364 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
365 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
0f8c9768 WD |
366 | |
367 | /* | |
368 | * BR2/3 and OR2/3 (SDRAM) | |
369 | * | |
370 | */ | |
371 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
372 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
373 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
374 | ||
375 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 376 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
0f8c9768 | 377 | |
6d0f6bcf JCPV |
378 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
379 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
0f8c9768 WD |
380 | |
381 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf JCPV |
382 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
383 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
0f8c9768 | 384 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
6d0f6bcf JCPV |
385 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
386 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
387 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
388 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
0f8c9768 WD |
389 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
390 | #endif /* CONFIG_CAN_DRIVER */ | |
391 | ||
392 | /* | |
393 | * Memory Periodic Timer Prescaler | |
394 | */ | |
395 | ||
396 | /* periodic timer for refresh */ | |
6d0f6bcf | 397 | #define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ |
0f8c9768 WD |
398 | |
399 | /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ | |
6d0f6bcf JCPV |
400 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
401 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
0f8c9768 WD |
402 | |
403 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf JCPV |
404 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
405 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
0f8c9768 WD |
406 | |
407 | /* | |
408 | * MAMR settings for SDRAM | |
409 | */ | |
410 | ||
411 | /* 8 column SDRAM */ | |
6d0f6bcf | 412 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
0f8c9768 WD |
413 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
414 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
415 | /* 9 column SDRAM */ | |
6d0f6bcf | 416 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
0f8c9768 WD |
417 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
418 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
419 | ||
420 | ||
421 | /* | |
422 | * Internal Definitions | |
423 | * | |
424 | * Boot Flags | |
425 | */ | |
426 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
427 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
428 | ||
429 | #endif /* __CONFIG_H */ |