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5e5f9ed2 WD |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /* | |
28 | * High Level Configuration Options | |
29 | * (easy to change) | |
30 | */ | |
31 | ||
32 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
33 | #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ | |
34 | #define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ | |
35 | ||
36 | #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ | |
37 | ||
38 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
39 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
40 | ||
5e5f9ed2 WD |
41 | #define CONFIG_BOARD_EARLY_INIT_R |
42 | ||
43 | /* | |
44 | * Serial console configuration | |
45 | */ | |
46 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
47 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
48 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
49 | ||
37e4f24b | 50 | |
5e5f9ed2 | 51 | /* |
37e4f24b | 52 | * Command line configuration. |
5e5f9ed2 | 53 | */ |
37e4f24b JL |
54 | #include <config_cmd_default.h> |
55 | ||
56 | #define CONFIG_CMD_ASKENV | |
57 | #define CONFIG_CMD_DATE | |
58 | #define CONFIG_CMD_DHCP | |
59 | #define CONFIG_CMD_IMMAP | |
60 | #define CONFIG_CMD_MII | |
61 | #define CONFIG_CMD_NFS | |
62 | #define CONFIG_CMD_REGINFO | |
63 | #define CONFIG_CMD_SNTP | |
64 | ||
5e5f9ed2 WD |
65 | |
66 | /* | |
67 | * MUST be low boot - HIGHBOOT is not supported anymore | |
68 | */ | |
69 | #if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ | |
70 | # define CFG_LOWBOOT 1 | |
71 | # define CFG_LOWBOOT16 1 | |
72 | #else | |
73 | # error "TEXT_BASE must be 0xFE000000" | |
74 | #endif | |
75 | ||
76 | /* | |
77 | * Autobooting | |
78 | */ | |
79 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
80 | ||
81 | #define CONFIG_PREBOOT "echo;" \ | |
82 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
83 | "echo" | |
84 | ||
85 | #undef CONFIG_BOOTARGS | |
86 | ||
87 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
88 | "netdev=eth0\0" \ | |
89 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 90 | "nfsroot=${serverip}:${rootpath}\0" \ |
5e5f9ed2 | 91 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
92 | "addip=setenv bootargs ${bootargs} " \ |
93 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
94 | ":${hostname}:${netdev}:off panic=1\0" \ | |
5e5f9ed2 | 95 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 96 | "bootm ${kernel_addr}\0" \ |
5e5f9ed2 | 97 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
98 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
99 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
5e5f9ed2 WD |
100 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
101 | "bootfile=/tftpboot/canmb/uImage\0" \ | |
102 | "" | |
103 | ||
104 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
105 | ||
106 | /* | |
107 | * IPB Bus clocking configuration. | |
108 | */ | |
c99512d6 | 109 | #undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
5e5f9ed2 WD |
110 | |
111 | /* | |
112 | * Flash configuration, expect one 16 Megabyte Bank at most | |
113 | */ | |
114 | #define CFG_FLASH_BASE 0xFE000000 | |
115 | #define CFG_FLASH_SIZE 0x02000000 | |
116 | #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
117 | #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ | |
118 | ||
119 | #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ | |
120 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
121 | ||
122 | #define CFG_FLASH_CFI_DRIVER | |
123 | #define CFG_FLASH_CFI | |
124 | #define CFG_FLASH_EMPTY_INFO | |
125 | ||
5e5f9ed2 WD |
126 | /* |
127 | * Environment settings | |
128 | */ | |
129 | #define CFG_ENV_IS_IN_FLASH 1 | |
130 | #define CFG_ENV_OFFSET (2*128*1024) | |
131 | #define CFG_ENV_SIZE 0x2000 | |
132 | #define CFG_ENV_SECT_SIZE (128*1024) | |
133 | ||
134 | /* | |
135 | * Memory map | |
136 | * | |
137 | * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000 | |
138 | */ | |
139 | #define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */ | |
140 | #define CFG_SDRAM_BASE 0x00000000 | |
141 | #define CFG_DEFAULT_MBAR 0x80000000 | |
142 | ||
143 | /* Use SRAM until RAM will be available */ | |
144 | #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM | |
145 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ | |
146 | ||
147 | ||
148 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
149 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
150 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
151 | ||
152 | #define CFG_MONITOR_BASE TEXT_BASE | |
153 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
154 | # define CFG_RAMBOOT 1 | |
155 | #endif | |
156 | ||
157 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
158 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
159 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
160 | ||
161 | /* | |
162 | * Ethernet configuration | |
163 | */ | |
164 | #define CONFIG_MPC5xxx_FEC 1 | |
a6310928 | 165 | #define CONFIG_PHY_ADDR 0x0 |
5e5f9ed2 WD |
166 | /* |
167 | * GPIO configuration: | |
168 | * PSC1,2,3 predefined as UART | |
169 | * PCI disabled | |
170 | * Ethernet 100 with MD | |
171 | */ | |
172 | #define CFG_GPS_PORT_CONFIG 0x00058444 | |
173 | ||
174 | /* | |
175 | * Miscellaneous configurable options | |
176 | */ | |
177 | #define CFG_LONGHELP /* undef to save memory */ | |
178 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
37e4f24b | 179 | #if defined(CONFIG_CMD_KGDB) |
5e5f9ed2 WD |
180 | # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
181 | #else | |
182 | # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
183 | #endif | |
184 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
185 | #define CFG_MAXARGS 16 /* max number of command args */ | |
186 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
187 | ||
188 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ | |
189 | #define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */ | |
190 | ||
191 | #define CFG_LOAD_ADDR 0x200000 /* default load address */ | |
192 | ||
193 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
194 | ||
195 | #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ | |
196 | ||
37e4f24b JL |
197 | #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
198 | #if defined(CONFIG_CMD_KGDB) | |
199 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
200 | #endif | |
201 | ||
5e5f9ed2 WD |
202 | /* |
203 | * Various low-level settings | |
204 | */ | |
205 | #define CFG_HID0_INIT HID0_ICE | HID0_ICFI | |
206 | #define CFG_HID0_FINAL HID0_ICE | |
207 | ||
208 | #define CFG_BOOTCS_START CFG_FLASH_BASE | |
209 | #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE | |
210 | #define CFG_BOOTCS_CFG 0x00047D01 | |
211 | #define CFG_CS0_START CFG_FLASH_BASE | |
212 | #define CFG_CS0_SIZE CFG_FLASH_SIZE | |
213 | ||
214 | #define CFG_CS_BURST 0x00000000 | |
215 | #define CFG_CS_DEADCYCLE 0x33333333 | |
216 | ||
217 | #define CFG_RESET_ADDRESS 0x7f000000 | |
218 | ||
219 | #endif /* __CONFIG_H */ |