[people/ms/u-boot.git] / include / configs / cerf250.h

/*
 * (C) Copyright 2002
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * Configuation settings for the CERF250 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_PXA250		1	/* This is an PXA250 CPU    */
#define CONFIG_CERF250		1	/* on Cerf PXA Board	    */
#define BOARD_LATE_INIT		1
#define CONFIG_BAUDRATE		38400

#undef	CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */

/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

/*
 * Hardware drivers
 */
#define CONFIG_DRIVER_SMC91111
#define CONFIG_SMC91111_BASE 0x04000300
#define CONFIG_SMC_USE_32_BIT

/*
 * select serial console configuration
 */
#define CONFIG_FFUART	     1	/* we use FFUART on CERF PXA */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>


#define CONFIG_BOOTDELAY	3
#define CONFIG_ETHADDR		00:D0:CA:F1:3C:D2
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		192.168.0.5
#define CONFIG_SERVERIP		192.168.0.2
#define CONFIG_BOOTCOMMAND	"bootm 0xC0000"
#define CONFIG_BOOTARGS		"root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400"
#define CONFIG_CMDLINE_TAG

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define CFG_HUSH_PARSER		1
#define CFG_PROMPT_HUSH_PS2	"> "

#define CFG_LONGHELP					/* undef to save memory		*/
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT			"uboot$ "	/* Monitor Command Prompt */
#else
#define CFG_PROMPT			"=> "		/* Monitor Command Prompt */
#endif
#define CFG_CBSIZE			256			/* Console I/O Buffer Size	*/
#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
										/* Print Buffer Size */
#define CFG_MAXARGS			16			/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_DEVICE_NULLDEV	1

#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/

#undef	CFG_CLKS_IN_HZ

#define CFG_LOAD_ADDR		0xa2000000	/* default load address */

#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
#define CFG_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }


/*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	4			/* we have 2 banks of DRAM */
#define PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
#define PHYS_SDRAM_2			0xa4000000	/* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 MB */
#define PHYS_SDRAM_3			0xa8000000	/* SDRAM Bank #3 */
#define PHYS_SDRAM_3_SIZE		0x00000000	/* 0 MB */
#define PHYS_SDRAM_4			0xac000000	/* SDRAM Bank #4 */
#define PHYS_SDRAM_4_SIZE		0x00000000	/* 0 MB */

#define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
#define PHYS_FLASH_2			0x04000000	/* Flash Bank #2 */
#define PHYS_FLASH_SIZE			0x02000000	/* 32 MB */
#define PHYS_FLASH_BANK_SIZE		0x02000000	/* 32 MB Banks */
#define PHYS_FLASH_SECT_SIZE		0x00040000	/* 256 KB sectors (x2) */

#define CFG_DRAM_BASE			0xa0000000
#define CFG_DRAM_SIZE			0x04000000

#define CFG_FLASH_BASE			PHYS_FLASH_1

/*
 * GPIO settings
 */


#define CFG_GPSR0_VAL		0x00408030
#define CFG_GPSR1_VAL		0x00BFA882
#define CFG_GPSR2_VAL		0x0001C000
#define CFG_GPCR0_VAL		0xC0031100
#define CFG_GPCR1_VAL		0xFC400300
#define CFG_GPCR2_VAL		0x00003FFF
#define CFG_GPDR0_VAL		0xC0439330
#define CFG_GPDR1_VAL		0xFCFFAB82
#define CFG_GPDR2_VAL		0x0001FFFF
#define CFG_GAFR0_L_VAL		0x80000000
#define CFG_GAFR0_U_VAL		0xA5000010
#define CFG_GAFR1_L_VAL		0x60008018
#define CFG_GAFR1_U_VAL		0xAAA5AAAA
#define CFG_GAFR2_L_VAL		0xAAA0000A
#define CFG_GAFR2_U_VAL		0x00000002

#define CFG_PSSR_VAL		0x20

/*
 * Memory settings
 */
#define CFG_MSC0_VAL		0x12447FF0
#define CFG_MSC1_VAL		0x12BC5554
#define CFG_MSC2_VAL		0x7FF97FF1
#define CFG_MDCNFG_VAL		0x00001AC9
#define CFG_MDREFR_VAL		0x03CDC017
#define CFG_MDMRS_VAL		0x00000000

/*
 * PCMCIA and CF Interfaces
 */
#define CFG_MECR_VAL		0x00000000
#define CFG_MCMEM0_VAL		0x00010504
#define CFG_MCMEM1_VAL		0x00010504
#define CFG_MCATT0_VAL		0x00010504
#define CFG_MCATT1_VAL		0x00010504
#define CFG_MCIO0_VAL		0x00004715
#define CFG_MCIO1_VAL		0x00004715

#define _LED			0x08000010	/*check this */
#define LED_BLANK		0x08000040
#define LED_GPIO		0x10

/*
 * FLASH and environment organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip    */

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */

#define CFG_MONITOR_LEN		0x40000		/* 256 KiB */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CFG_MONITOR_LEN)
#define CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/


#endif	/* __CONFIG_H */
Commit	Line	Data
fabd46ac WD	1	/*
	2	* (C) Copyright 2002
	3	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	4	*
	5	* (C) Copyright 2002
	6	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	7	* Marius Groeger <mgroeger@sysgo.de>
	8	*
	9	* Configuation settings for the CERF250 board.
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32
fabd46ac WD	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37	#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
	38	#define CONFIG_CERF250 1 /* on Cerf PXA Board */
	39	#define BOARD_LATE_INIT 1
	40	#define CONFIG_BAUDRATE 38400
	41
53677ef1	42	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
fabd46ac WD	43
	44	/*
	45	* Size of malloc() pool
	46	*/
0e8d1586	47	#define CFG_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
fabd46ac WD	48	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	49
	50	/*
	51	* Hardware drivers
	52	*/
	53	#define CONFIG_DRIVER_SMC91111
	54	#define CONFIG_SMC91111_BASE 0x04000300
	55	#define CONFIG_SMC_USE_32_BIT
	56
	57	/*
	58	* select serial console configuration
	59	*/
	60	#define CONFIG_FFUART 1 /* we use FFUART on CERF PXA */
	61
	62	/* allow to overwrite serial and ethaddr */
	63	#define CONFIG_ENV_OVERWRITE
fabd46ac	64
80ff4f99 JL	65	/*
	66	* BOOTP options
	67	*/
	68	#define CONFIG_BOOTP_BOOTFILESIZE
	69	#define CONFIG_BOOTP_BOOTPATH
	70	#define CONFIG_BOOTP_GATEWAY
	71	#define CONFIG_BOOTP_HOSTNAME
	72
	73
37e4f24b JL	74	/*
	75	* Command line configuration.
	76	*/
	77	#include <config_cmd_default.h>
	78
fabd46ac WD	79
	80	#define CONFIG_BOOTDELAY 3
	81	#define CONFIG_ETHADDR 00:D0:CA:F1:3C:D2
	82	#define CONFIG_NETMASK 255.255.255.0
	83	#define CONFIG_IPADDR 192.168.0.5
	84	#define CONFIG_SERVERIP 192.168.0.2
	85	#define CONFIG_BOOTCOMMAND "bootm 0xC0000"
	86	#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400"
	87	#define CONFIG_CMDLINE_TAG
	88
37e4f24b	89	#if defined(CONFIG_CMD_KGDB)
fabd46ac WD	90	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	91	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	92	#endif
	93
	94	/*
	95	* Miscellaneous configurable options
	96	*/
	97	#define CFG_HUSH_PARSER 1
	98	#define CFG_PROMPT_HUSH_PS2 "> "
	99
	100	#define CFG_LONGHELP /* undef to save memory */
	101	#ifdef CFG_HUSH_PARSER
	102	#define CFG_PROMPT "uboot$ " /* Monitor Command Prompt */
	103	#else
	104	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	105	#endif
	106	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
53677ef1	107	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
fabd46ac WD	108	/* Print Buffer Size */
	109	#define CFG_MAXARGS 16 /* max number of command args */
	110	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	111	#define CFG_DEVICE_NULLDEV 1
	112
	113	#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
	114	#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
	115
	116	#undef CFG_CLKS_IN_HZ
	117
	118	#define CFG_LOAD_ADDR 0xa2000000 /* default load address */
	119
	120	#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
	121	#define CFG_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
	122
	123	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	124
	125
	126	/*
	127	* Stack sizes
	128	*
	129	* The stack sizes are set up in start.S using the settings below
	130	*/
	131	#define CONFIG_STACKSIZE (1281024) / regular stack */
	132	#ifdef CONFIG_USE_IRQ
	133	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	134	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	135	#endif
	136
	137	/*
	138	* Physical Memory Map
	139	*/
53677ef1 WD	140	#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
	141	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	142	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	143	#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
	144	#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
	145	#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
	146	#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
	147	#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
	148	#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
	149
	150	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	151	#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
	152	#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
	153	#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
	154	#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
fabd46ac WD	155
	156	#define CFG_DRAM_BASE 0xa0000000
	157	#define CFG_DRAM_SIZE 0x04000000
	158
	159	#define CFG_FLASH_BASE PHYS_FLASH_1
	160
	161	/*
	162	* GPIO settings
	163	*/
	164
	165
	166	#define CFG_GPSR0_VAL 0x00408030
	167	#define CFG_GPSR1_VAL 0x00BFA882
	168	#define CFG_GPSR2_VAL 0x0001C000
	169	#define CFG_GPCR0_VAL 0xC0031100
	170	#define CFG_GPCR1_VAL 0xFC400300
	171	#define CFG_GPCR2_VAL 0x00003FFF
	172	#define CFG_GPDR0_VAL 0xC0439330
	173	#define CFG_GPDR1_VAL 0xFCFFAB82
	174	#define CFG_GPDR2_VAL 0x0001FFFF
	175	#define CFG_GAFR0_L_VAL 0x80000000
	176	#define CFG_GAFR0_U_VAL 0xA5000010
	177	#define CFG_GAFR1_L_VAL 0x60008018
	178	#define CFG_GAFR1_U_VAL 0xAAA5AAAA
	179	#define CFG_GAFR2_L_VAL 0xAAA0000A
	180	#define CFG_GAFR2_U_VAL 0x00000002
	181
	182	#define CFG_PSSR_VAL 0x20
	183
	184	/*
	185	* Memory settings
	186	*/
	187	#define CFG_MSC0_VAL 0x12447FF0
	188	#define CFG_MSC1_VAL 0x12BC5554
	189	#define CFG_MSC2_VAL 0x7FF97FF1
	190	#define CFG_MDCNFG_VAL 0x00001AC9
	191	#define CFG_MDREFR_VAL 0x03CDC017
	192	#define CFG_MDMRS_VAL 0x00000000
	193
	194	/*
	195	* PCMCIA and CF Interfaces
	196	*/
	197	#define CFG_MECR_VAL 0x00000000
	198	#define CFG_MCMEM0_VAL 0x00010504
	199	#define CFG_MCMEM1_VAL 0x00010504
	200	#define CFG_MCATT0_VAL 0x00010504
	201	#define CFG_MCATT1_VAL 0x00010504
	202	#define CFG_MCIO0_VAL 0x00004715
	203	#define CFG_MCIO1_VAL 0x00004715
	204
	205	#define _LED 0x08000010 /check this /
	206	#define LED_BLANK 0x08000040
	207	#define LED_GPIO 0x10
	208
	209	/*
	210	* FLASH and environment organization
	211	*/
	212	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
53677ef1	213	#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
fabd46ac WD	214
	215	/* timeout values are in ticks */
	216	#define CFG_FLASH_ERASE_TOUT (25CFG_HZ) / Timeout for Flash Erase */
	217	#define CFG_FLASH_WRITE_TOUT (25CFG_HZ) / Timeout for Flash Write */
	218
	219	#define CFG_MONITOR_LEN 0x40000 /* 256 KiB */
5a1aceb0	220	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	221	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN)
0e8d1586 JCPV	222	#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
fabd46ac WD	223
	224
	225	#endif /* __CONFIG_H */