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e32028a7 NK |
1 | /* |
2 | * Config file for Compulab CM-FX6 board | |
3 | * | |
4 | * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ | |
5 | * | |
6 | * Author: Nikita Kiryanov <nikita@compulab.co.il> | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
11 | #ifndef __CONFIG_CM_FX6_H | |
12 | #define __CONFIG_CM_FX6_H | |
13 | ||
e32028a7 NK |
14 | #include "mx6_common.h" |
15 | ||
16 | /* Machine config */ | |
e32028a7 NK |
17 | #define CONFIG_SYS_LITTLE_ENDIAN |
18 | #define CONFIG_MACH_TYPE 4273 | |
e32028a7 | 19 | |
e32028a7 | 20 | /* MMC */ |
e32028a7 NK |
21 | #define CONFIG_SYS_FSL_USDHC_NUM 3 |
22 | #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR | |
23 | ||
24 | /* RAM */ | |
25 | #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR | |
26 | #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR | |
27 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
28 | #define CONFIG_NR_DRAM_BANKS 2 | |
29 | #define CONFIG_SYS_MEMTEST_START 0x10000000 | |
30 | #define CONFIG_SYS_MEMTEST_END 0x10010000 | |
31 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
32 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
33 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
34 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
35 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
36 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
37 | ||
38 | /* Serial console */ | |
39 | #define CONFIG_MXC_UART | |
40 | #define CONFIG_MXC_UART_BASE UART4_BASE | |
e32028a7 NK |
41 | #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} |
42 | ||
e32028a7 | 43 | /* SPI flash */ |
e32028a7 NK |
44 | #define CONFIG_SF_DEFAULT_BUS 0 |
45 | #define CONFIG_SF_DEFAULT_CS 0 | |
46 | #define CONFIG_SF_DEFAULT_SPEED 25000000 | |
47 | #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) | |
48 | ||
63a93093 CS |
49 | /* MTD support */ |
50 | #ifndef CONFIG_SPL_BUILD | |
63a93093 CS |
51 | #define CONFIG_MTD_DEVICE |
52 | #define CONFIG_MTD_PARTITIONS | |
53 | #define CONFIG_SPI_FLASH_MTD | |
54 | #endif | |
55 | ||
e32028a7 | 56 | /* Environment */ |
e32028a7 NK |
57 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED |
58 | #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE | |
59 | #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS | |
60 | #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
61 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) | |
62 | #define CONFIG_ENV_SIZE (8 * 1024) | |
63 | #define CONFIG_ENV_OFFSET (768 * 1024) | |
64 | ||
65 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
1c2e5292 | 66 | "stdin=serial,usbkbd\0" \ |
deb94d61 NK |
67 | "stdout=serial,vga\0" \ |
68 | "stderr=serial,vga\0" \ | |
69 | "panel=HDMI\0" \ | |
e32028a7 | 70 | "autoload=no\0" \ |
f0f6724f CS |
71 | "uImage=uImage-cm-fx6\0" \ |
72 | "zImage=zImage-cm-fx6\0" \ | |
508a6ede NK |
73 | "kernel=uImage-cm-fx6\0" \ |
74 | "script=boot.scr\0" \ | |
75 | "dtb=cm-fx6.dtb\0" \ | |
76 | "bootm_low=18000000\0" \ | |
e32028a7 NK |
77 | "loadaddr=0x10800000\0" \ |
78 | "fdtaddr=0x11000000\0" \ | |
79 | "console=ttymxc3,115200\0" \ | |
80 | "ethprime=FEC0\0" \ | |
e32028a7 NK |
81 | "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \ |
82 | "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ | |
e32028a7 | 83 | "doboot=bootm ${loadaddr}\0" \ |
508a6ede | 84 | "doloadfdt=false\0" \ |
43ede0bc TR |
85 | "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ |
86 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ | |
f0f6724f | 87 | "setboottypez=setenv kernel ${zImage};" \ |
e32028a7 | 88 | "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \ |
508a6ede | 89 | "setenv doloadfdt true;\0" \ |
f0f6724f | 90 | "setboottypem=setenv kernel ${uImage};" \ |
e32028a7 | 91 | "setenv doboot bootm ${loadaddr};" \ |
508a6ede | 92 | "setenv doloadfdt false;\0"\ |
e32028a7 | 93 | "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ |
206f38f7 | 94 | "sataroot=/dev/sda2 rw rootwait\0" \ |
a6b0652b NK |
95 | "nandroot=/dev/mtdblock4 rw\0" \ |
96 | "nandrootfstype=ubifs\0" \ | |
508a6ede | 97 | "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \ |
f0f6724f | 98 | "${video} ${extrabootargs}\0" \ |
508a6ede | 99 | "sataargs=setenv bootargs console=${console} root=${sataroot} " \ |
f0f6724f | 100 | "${video} ${extrabootargs}\0" \ |
a6b0652b NK |
101 | "nandargs=setenv bootargs console=${console} " \ |
102 | "root=${nandroot} " \ | |
103 | "rootfstype=${nandrootfstype} " \ | |
f0f6724f | 104 | "${video} ${extrabootargs}\0" \ |
508a6ede | 105 | "nandboot=if run nandloadkernel; then " \ |
a6b0652b | 106 | "run nandloadfdt;" \ |
508a6ede NK |
107 | "run setboottypem;" \ |
108 | "run storagebootcmd;" \ | |
109 | "run setboottypez;" \ | |
110 | "run storagebootcmd;" \ | |
111 | "fi;\0" \ | |
112 | "run_eboot=echo Starting EBOOT ...; "\ | |
113 | "mmc dev 2 && " \ | |
114 | "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \ | |
115 | "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0"\ | |
116 | "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0"\ | |
117 | "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${dtb};\0" \ | |
118 | "bootscript=echo Running bootscript from ${storagetype} ...;" \ | |
119 | "source ${loadaddr};\0" \ | |
120 | "nandloadkernel=nand read ${loadaddr} 0 780000;\0" \ | |
121 | "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \ | |
122 | "setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \ | |
123 | "setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \ | |
124 | "setupnandboot=setenv storagetype nand;\0" \ | |
125 | "setupusbboot=setenv storagetype usb; setenv storagedev 0;\0" \ | |
126 | "storagebootcmd=echo Booting from ${storagetype} ...;" \ | |
127 | "run ${storagetype}args; run doboot;\0" \ | |
128 | "trybootk=if run loadkernel; then " \ | |
129 | "if ${doloadfdt}; then " \ | |
130 | "run loadfdt;" \ | |
a6b0652b | 131 | "fi;" \ |
508a6ede NK |
132 | "run storagebootcmd;" \ |
133 | "fi;\0" \ | |
134 | "trybootsmz=if run loadscript; then " \ | |
135 | "run bootscript;" \ | |
206f38f7 | 136 | "fi;" \ |
508a6ede NK |
137 | "run setboottypem;" \ |
138 | "run trybootk;" \ | |
139 | "run setboottypez;" \ | |
140 | "run trybootk;\0" | |
e32028a7 NK |
141 | |
142 | #define CONFIG_BOOTCOMMAND \ | |
508a6ede NK |
143 | "run setupmmcboot;" \ |
144 | "mmc dev ${storagedev};" \ | |
145 | "if mmc rescan; then " \ | |
146 | "run trybootsmz;" \ | |
147 | "fi;" \ | |
148 | "run setupusbboot;" \ | |
149 | "if usb start; then "\ | |
150 | "if run loadscript; then " \ | |
151 | "run bootscript;" \ | |
152 | "fi;" \ | |
153 | "fi;" \ | |
154 | "run setupsataboot;" \ | |
155 | "if sata init; then " \ | |
156 | "run trybootsmz;" \ | |
157 | "fi;" \ | |
158 | "run setupnandboot;" \ | |
159 | "run nandboot;" | |
e32028a7 | 160 | |
63a93093 | 161 | #define CONFIG_PREBOOT "usb start;sf probe" |
1c2e5292 | 162 | |
e32028a7 NK |
163 | /* SPI */ |
164 | #define CONFIG_SPI | |
165 | #define CONFIG_MXC_SPI | |
e32028a7 | 166 | |
a6b0652b NK |
167 | /* NAND */ |
168 | #ifndef CONFIG_SPL_BUILD | |
a6b0652b NK |
169 | #define CONFIG_SYS_NAND_BASE 0x40000000 |
170 | #define CONFIG_SYS_NAND_MAX_CHIPS 1 | |
171 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
172 | #define CONFIG_NAND_MXS | |
173 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
174 | /* APBH DMA is required for NAND support */ | |
175 | #define CONFIG_APBH_DMA | |
176 | #define CONFIG_APBH_DMA_BURST | |
177 | #define CONFIG_APBH_DMA_BURST8 | |
178 | #endif | |
179 | ||
02b1343e NK |
180 | /* Ethernet */ |
181 | #define CONFIG_FEC_MXC | |
182 | #define CONFIG_FEC_MXC_PHYADDR 0 | |
183 | #define CONFIG_FEC_XCV_TYPE RGMII | |
184 | #define IMX_FEC_BASE ENET_BASE_ADDR | |
02b1343e NK |
185 | #define CONFIG_PHY_ATHEROS |
186 | #define CONFIG_MII | |
187 | #define CONFIG_ETHPRIME "FEC0" | |
188 | #define CONFIG_ARP_TIMEOUT 200UL | |
02b1343e NK |
189 | #define CONFIG_NET_RETRY_COUNT 5 |
190 | ||
0f3effb9 | 191 | /* USB */ |
0f3effb9 NK |
192 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
193 | #define CONFIG_MXC_USB_FLAGS 0 | |
194 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | |
195 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ | |
196 | ||
f42b2f60 | 197 | /* I2C */ |
f42b2f60 NK |
198 | #define CONFIG_SYS_I2C |
199 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
200 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
201 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 202 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
f42b2f60 NK |
203 | #define CONFIG_SYS_I2C_SPEED 100000 |
204 | #define CONFIG_SYS_MXC_I2C3_SPEED 400000 | |
205 | ||
206 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
207 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
208 | #define CONFIG_SYS_I2C_EEPROM_BUS 2 | |
209 | ||
206f38f7 | 210 | /* SATA */ |
206f38f7 | 211 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
206f38f7 | 212 | #define CONFIG_LBA48 |
206f38f7 NK |
213 | #define CONFIG_DWC_AHSATA_PORT_ID 0 |
214 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR | |
215 | ||
e32028a7 | 216 | /* Boot */ |
e32028a7 | 217 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
f66113c0 | 218 | #define CONFIG_SERIAL_TAG |
e32028a7 NK |
219 | |
220 | /* misc */ | |
9fbdcf01 | 221 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
7d1abb7d | 222 | #define CONFIG_MISC_INIT_R |
e32028a7 NK |
223 | |
224 | /* SPL */ | |
225 | #include "imx6_spl.h" | |
e32028a7 NK |
226 | #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) |
227 | #define CONFIG_SPL_SPI_LOAD | |
228 | ||
deb94d61 | 229 | /* Display */ |
deb94d61 | 230 | #define CONFIG_VIDEO_IPUV3 |
deb94d61 | 231 | #define CONFIG_IMX_HDMI |
deb94d61 | 232 | |
3a236a35 | 233 | #define CONFIG_SPLASH_SCREEN |
f82eb2fa | 234 | #define CONFIG_SPLASH_SOURCE |
3a236a35 NK |
235 | #define CONFIG_VIDEO_BMP_RLE8 |
236 | ||
8015dde8 NK |
237 | #define CONFIG_VIDEO_LOGO |
238 | #define CONFIG_VIDEO_BMP_LOGO | |
239 | ||
12616531 | 240 | /* EEPROM */ |
12616531 NK |
241 | #define CONFIG_ENV_EEPROM_IS_ON_I2C |
242 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
243 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
244 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
245 | #define CONFIG_SYS_EEPROM_SIZE 256 | |
246 | ||
e32028a7 | 247 | #endif /* __CONFIG_CM_FX6_H */ |