[people/ms/u-boot.git] / include / configs / cm_t335.h

/*
 * Config file for Compulab CM-T335 board
 *
 * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
 *
 * Author: Ilya Ledvich <ilya@compulab.co.il>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_CM_T335_H
#define __CONFIG_CM_T335_H

#define CONFIG_CM_T335
#define CONFIG_NAND

#include <configs/ti_am335x_common.h>

#undef CONFIG_SPI
#undef CONFIG_OMAP3_SPI
#undef CONFIG_BOOTCOUNT_LIMIT
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC

#undef CONFIG_MAX_RAM_BANK_SIZE
#define CONFIG_MAX_RAM_BANK_SIZE	(512 << 20)	/* 512MB */

#define CONFIG_MACH_TYPE		MACH_TYPE_CM_T335

/* Clock Defines */
#define V_OSCK				25000000  /* Clock output from T2 */
#define V_SCLK				(V_OSCK)

#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KiB */

#ifndef CONFIG_SPL_BUILD
#define MMCARGS \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
	"mmcrootfstype=ext4\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0"

#define NANDARGS \
	"mtdids=" MTDIDS_DEFAULT "\0" \
	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	"nandroot=ubi0:rootfs rw\0" \
	"nandrootfstype=ubifs\0" \
	"nandargs=setenv bootargs console=${console} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype} " \
		"ubi.mtd=${rootfs_name}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nboot ${loadaddr} nand0 900000; " \
		"bootm ${loadaddr}\0"

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=82000000\0" \
	"console=ttyO0,115200n8\0" \
	"rootfs_name=rootfs\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	MMCARGS \
	NANDARGS

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"
#endif /* CONFIG_SPL_BUILD */

#define CONFIG_TIMESTAMP
#define CONFIG_SYS_AUTOLOAD		"no"

/* Serial console configuration */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SERIAL1			1	/* UART0 */

/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */

/* I2C Configuration */
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_I2C_EEPROM_BUS	0

/* SPL */
#define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-omap2/u-boot-spl.lds"

/* Network. */
#define CONFIG_PHY_ATHEROS

/* NAND support */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
					 CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
					 10, 11, 12, 13, 14, 15, 16, 17, \
					 18, 19, 20, 21, 22, 23, 24, 25, \
					 26, 27, 28, 29, 30, 31, 32, 33, \
					 34, 35, 36, 37, 38, 39, 40, 41, \
					 42, 43, 44, 45, 46, 47, 48, 49, \
					 50, 51, 52, 53, 54, 55, 56, 57, }

#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	14

#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#undef CONFIG_SYS_NAND_U_BOOT_OFFS
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x200000

#define MTDIDS_DEFAULT			"nand0=nand"
#define MTDPARTS_DEFAULT		"mtdparts=nand:2m(spl)," \
					"1m(u-boot),1m(u-boot-env)," \
					"1m(dtb),4m(splash)," \
					"6m(kernel),-(rootfs)"
#define CONFIG_ENV_OFFSET		0x300000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_SYS_NAND_ONFI_DETECTION
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_CMD_SPL_NAND_OFS		0x400000 /* un-assigned: (using dtb) */
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x500000
#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
#endif

/* GPIO pin + bank to pin ID mapping */
#define GPIO_PIN(_bank, _pin)		((_bank << 5) + _pin)

/* Status LED */
/* Status LED polarity is inversed, so init it in the "off" state */

/* EEPROM */
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
#define CONFIG_SYS_EEPROM_SIZE			256

#ifndef CONFIG_SPL_BUILD
/*
 * Enable PCA9555 at I2C0-0x26.
 * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
 */
#define CONFIG_PCA953X
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_SYS_I2C_PCA953X_ADDR	0x26
#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x26, 16} }
#endif /* CONFIG_SPL_BUILD */

#endif	/* __CONFIG_CM_T335_H */
Commit	Line	Data
54e7445d IL	1	/*
	2	* Config file for Compulab CM-T335 board
	3	*
	4	* Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
	5	*
	6	* Author: Ilya Ledvich <ilya@compulab.co.il>
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#ifndef __CONFIG_CM_T335_H
	12	#define __CONFIG_CM_T335_H
	13
	14	#define CONFIG_CM_T335
	15	#define CONFIG_NAND
	16
	17	#include <configs/ti_am335x_common.h>
	18
54e7445d IL	19	#undef CONFIG_SPI
54e7445d IL	20	#undef CONFIG_OMAP3_SPI
54e7445d IL	21	#undef CONFIG_BOOTCOUNT_LIMIT
	22	#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
	23
	24	#undef CONFIG_MAX_RAM_BANK_SIZE
	25	#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */
	26
54e7445d IL	27	#define CONFIG_MACH_TYPE MACH_TYPE_CM_T335
	28
	29	/* Clock Defines */
	30	#define V_OSCK 25000000 /* Clock output from T2 */
	31	#define V_SCLK (V_OSCK)
	32
	33	#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
	34
	35	#ifndef CONFIG_SPL_BUILD
	36	#define MMCARGS \
	37	"mmcdev=0\0" \
	38	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
	39	"mmcrootfstype=ext4\0" \
	40	"mmcargs=setenv bootargs console=${console} " \
	41	"root=${mmcroot} " \
	42	"rootfstype=${mmcrootfstype}\0" \
	43	"mmcboot=echo Booting from mmc ...; " \
	44	"run mmcargs; " \
	45	"bootm ${loadaddr}\0"
	46
	47	#define NANDARGS \
	48	"mtdids=" MTDIDS_DEFAULT "\0" \
	49	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	50	"nandroot=ubi0:rootfs rw\0" \
	51	"nandrootfstype=ubifs\0" \
	52	"nandargs=setenv bootargs console=${console} " \
	53	"root=${nandroot} " \
	54	"rootfstype=${nandrootfstype} " \
	55	"ubi.mtd=${rootfs_name}\0" \
	56	"nandboot=echo Booting from nand ...; " \
	57	"run nandargs; " \
	58	"nboot ${loadaddr} nand0 900000; " \
	59	"bootm ${loadaddr}\0"
	60
54e7445d IL	61	#define CONFIG_EXTRA_ENV_SETTINGS \
	62	"loadaddr=82000000\0" \
	63	"console=ttyO0,115200n8\0" \
	64	"rootfs_name=rootfs\0" \
	65	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	66	"bootscript=echo Running bootscript from mmc ...; " \
	67	"source ${loadaddr}\0" \
	68	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	69	MMCARGS \
	70	NANDARGS
	71
	72	#define CONFIG_BOOTCOMMAND \
	73	"mmc dev ${mmcdev}; if mmc rescan; then " \
	74	"if run loadbootscript; then " \
	75	"run bootscript; " \
	76	"else " \
	77	"if run loaduimage; then " \
	78	"run mmcboot; " \
	79	"else run nandboot; " \
	80	"fi; " \
	81	"fi; " \
	82	"else run nandboot; fi"
	83	#endif /* CONFIG_SPL_BUILD */
	84
	85	#define CONFIG_TIMESTAMP
	86	#define CONFIG_SYS_AUTOLOAD "no"
	87
	88	/* Serial console configuration */
	89	#define CONFIG_CONS_INDEX 1
	90	#define CONFIG_SERIAL1 1 /* UART0 */
	91
	92	/* NS16550 Configuration */
	93	#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
	94	#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
54e7445d IL	95
	96	/* I2C Configuration */
	97	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
	98	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
52658fda	99	#define CONFIG_SYS_I2C_EEPROM_BUS 0
54e7445d IL	100
54e7445d IL	101	/* SPL */
3a517fdc	102	#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
54e7445d IL	103
54e7445d IL	104	/* Network. */
54e7445d IL	105	#define CONFIG_PHY_ATHEROS
	106
	107	/* NAND support */
	108	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	109	#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
	110	CONFIG_SYS_NAND_PAGE_SIZE)
	111	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	112	#define CONFIG_SYS_NAND_OOBSIZE 64
	113	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	114	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	115	#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
	116	10, 11, 12, 13, 14, 15, 16, 17, \
	117	18, 19, 20, 21, 22, 23, 24, 25, \
	118	26, 27, 28, 29, 30, 31, 32, 33, \
	119	34, 35, 36, 37, 38, 39, 40, 41, \
	120	42, 43, 44, 45, 46, 47, 48, 49, \
	121	50, 51, 52, 53, 54, 55, 56, 57, }
	122
	123	#define CONFIG_SYS_NAND_ECCSIZE 512
	124	#define CONFIG_SYS_NAND_ECCBYTES 14
	125
	126	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	127
	128	#undef CONFIG_SYS_NAND_U_BOOT_OFFS
	129	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
	130
54e7445d IL	131	#define MTDIDS_DEFAULT "nand0=nand"
	132	#define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl)," \
	133	"1m(u-boot),1m(u-boot-env)," \
	134	"1m(dtb),4m(splash)," \
	135	"6m(kernel),-(rootfs)"
54e7445d IL	136	#define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */
	137	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	138	#define CONFIG_SYS_NAND_ONFI_DETECTION
434f2cfc	139	#ifdef CONFIG_SPL_OS_BOOT
	140	#define CONFIG_CMD_SPL_NAND_OFS 0x400000 /* un-assigned: (using dtb) */
	141	#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000
	142	#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
	143	#endif
54e7445d IL	144
	145	/* GPIO pin + bank to pin ID mapping */
	146	#define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin)
	147
e8ac22be	148	/* Status LED */
e8ac22be	149	/* Status LED polarity is inversed, so init it in the "off" state */
e8ac22be	150
0e656b82	151	/* EEPROM */
0e656b82 NK	152	#define CONFIG_ENV_EEPROM_IS_ON_I2C
	153	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	154	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	155	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	156	#define CONFIG_SYS_EEPROM_SIZE 256
	157
ef62df80 IL	158	#ifndef CONFIG_SPL_BUILD
	159	/*
	160	* Enable PCA9555 at I2C0-0x26.
	161	* First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
	162	*/
	163	#define CONFIG_PCA953X
	164	#define CONFIG_CMD_PCA953X
	165	#define CONFIG_CMD_PCA953X_INFO
	166	#define CONFIG_SYS_I2C_PCA953X_ADDR 0x26
	167	#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} }
	168	#endif /* CONFIG_SPL_BUILD */
	169
54e7445d IL	170	#endif /* __CONFIG_CM_T335_H */
54e7445d IL	171