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36b4e2dd | 1 | /* |
9fc376be | 2 | * (C) Copyright 2011 CompuLab, Ltd. |
36b4e2dd | 3 | * Mike Rapoport <mike@compulab.co.il> |
dccd9a0b | 4 | * Igor Grinberg <grinberg@compulab.co.il> |
36b4e2dd MR |
5 | * |
6 | * Based on omap3_beagle.h | |
7 | * (C) Copyright 2006-2008 | |
8 | * Texas Instruments. | |
9 | * Richard Woodruff <r-woodruff2@ti.com> | |
10 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
11 | * | |
b65a77a8 | 12 | * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards |
36b4e2dd | 13 | * |
1a459660 | 14 | * SPDX-License-Identifier: GPL-2.0+ |
36b4e2dd MR |
15 | */ |
16 | ||
17 | #ifndef __CONFIG_H | |
18 | #define __CONFIG_H | |
19 | ||
3709844f AA |
20 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
21 | ||
36b4e2dd MR |
22 | /* |
23 | * High Level Configuration Options | |
24 | */ | |
9fc376be | 25 | #define CONFIG_OMAP /* in a TI OMAP core */ |
308252ad | 26 | #define CONFIG_OMAP_GPIO |
9fc376be | 27 | #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ |
c6f90e14 NM |
28 | /* Common ARM Erratas */ |
29 | #define CONFIG_ARM_ERRATA_454179 | |
30 | #define CONFIG_ARM_ERRATA_430973 | |
31 | #define CONFIG_ARM_ERRATA_621766 | |
36b4e2dd | 32 | |
36b4e2dd MR |
33 | #define CONFIG_SDRC /* The chip has SDRC controller */ |
34 | ||
35 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
987ec585 | 36 | #include <asm/arch/omap.h> |
36b4e2dd | 37 | |
36b4e2dd MR |
38 | /* Clock Defines */ |
39 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
40 | #define V_SCLK (V_OSCK >> 1) | |
41 | ||
36b4e2dd MR |
42 | #define CONFIG_MISC_INIT_R |
43 | ||
9fc376be NK |
44 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
45 | #define CONFIG_SETUP_MEMORY_TAGS | |
46 | #define CONFIG_INITRD_TAG | |
47 | #define CONFIG_REVISION_TAG | |
82309250 | 48 | #define CONFIG_SERIAL_TAG |
36b4e2dd MR |
49 | |
50 | /* | |
51 | * Size of malloc() pool | |
52 | */ | |
390cdcda | 53 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ |
9fc376be NK |
54 | /* Sector */ |
55 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) | |
36b4e2dd MR |
56 | |
57 | /* | |
58 | * Hardware drivers | |
59 | */ | |
60 | ||
61 | /* | |
62 | * NS16550 Configuration | |
63 | */ | |
64 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
65 | ||
36b4e2dd MR |
66 | #define CONFIG_SYS_NS16550_SERIAL |
67 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
68 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
69 | ||
70 | /* | |
71 | * select serial console configuration | |
72 | */ | |
73 | #define CONFIG_CONS_INDEX 3 | |
74 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
75 | #define CONFIG_SERIAL3 3 /* UART3 */ | |
76 | ||
77 | /* allow to overwrite serial and ethaddr */ | |
78 | #define CONFIG_ENV_OVERWRITE | |
79 | #define CONFIG_BAUDRATE 115200 | |
80 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
81 | 115200} | |
9fc376be | 82 | |
36b4e2dd | 83 | /* USB */ |
9fc376be | 84 | #define CONFIG_USB_OMAP3 |
854a7836 NK |
85 | #define CONFIG_USB_EHCI |
86 | #define CONFIG_USB_EHCI_OMAP | |
95de1e2f | 87 | #define CONFIG_USB_MUSB_UDC |
9fc376be | 88 | #define CONFIG_TWL4030_USB |
36b4e2dd MR |
89 | |
90 | /* USB device configuration */ | |
9fc376be NK |
91 | #define CONFIG_USB_DEVICE |
92 | #define CONFIG_USB_TTY | |
36b4e2dd MR |
93 | |
94 | /* commands to include */ | |
36b4e2dd MR |
95 | #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ |
96 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
0b800a6b | 97 | #define CONFIG_MTD_PARTITIONS |
9fc376be NK |
98 | #define MTDIDS_DEFAULT "nand0=nand" |
99 | #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ | |
0b800a6b | 100 | "1920k(u-boot),256k(u-boot-env),"\ |
9fc376be | 101 | "4m(kernel),-(fs)" |
36b4e2dd | 102 | |
36b4e2dd | 103 | #define CONFIG_CMD_NAND /* NAND support */ |
36b4e2dd | 104 | |
6789e84e HS |
105 | #define CONFIG_SYS_I2C |
106 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 | |
107 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
108 | #define CONFIG_SYS_I2C_OMAP34XX | |
82309250 NK |
109 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
110 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
52658fda | 111 | #define CONFIG_SYS_I2C_EEPROM_BUS 0 |
79874ae9 | 112 | #define CONFIG_I2C_MULTI_BUS |
36b4e2dd MR |
113 | |
114 | /* | |
115 | * TWL4030 | |
116 | */ | |
9fc376be NK |
117 | #define CONFIG_TWL4030_POWER |
118 | #define CONFIG_TWL4030_LED | |
36b4e2dd MR |
119 | |
120 | /* | |
121 | * Board NAND Info. | |
122 | */ | |
36b4e2dd MR |
123 | #define CONFIG_NAND_OMAP_GPMC |
124 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
125 | /* to access nand */ | |
126 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
127 | /* to access nand at */ | |
128 | /* CS0 */ | |
36b4e2dd MR |
129 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ |
130 | /* devices */ | |
7bb6e29b | 131 | |
36b4e2dd | 132 | /* Environment information */ |
36b4e2dd MR |
133 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
134 | "loadaddr=0x82000000\0" \ | |
135 | "usbtty=cdc_acm\0" \ | |
f3ef3609 | 136 | "console=ttyO2,115200n8\0" \ |
36b4e2dd MR |
137 | "mpurate=500\0" \ |
138 | "vram=12M\0" \ | |
139 | "dvimode=1024x768MR-16@60\0" \ | |
140 | "defaultdisplay=dvi\0" \ | |
141 | "mmcdev=0\0" \ | |
142 | "mmcroot=/dev/mmcblk0p2 rw\0" \ | |
0b800a6b | 143 | "mmcrootfstype=ext4 rootwait\0" \ |
36b4e2dd | 144 | "nandroot=/dev/mtdblock4 rw\0" \ |
0b800a6b | 145 | "nandrootfstype=ubifs\0" \ |
36b4e2dd MR |
146 | "mmcargs=setenv bootargs console=${console} " \ |
147 | "mpurate=${mpurate} " \ | |
148 | "vram=${vram} " \ | |
149 | "omapfb.mode=dvi:${dvimode} " \ | |
36b4e2dd MR |
150 | "omapdss.def_disp=${defaultdisplay} " \ |
151 | "root=${mmcroot} " \ | |
152 | "rootfstype=${mmcrootfstype}\0" \ | |
153 | "nandargs=setenv bootargs console=${console} " \ | |
154 | "mpurate=${mpurate} " \ | |
155 | "vram=${vram} " \ | |
156 | "omapfb.mode=dvi:${dvimode} " \ | |
36b4e2dd MR |
157 | "omapdss.def_disp=${defaultdisplay} " \ |
158 | "root=${nandroot} " \ | |
159 | "rootfstype=${nandrootfstype}\0" \ | |
160 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ | |
161 | "bootscript=echo Running bootscript from mmc ...; " \ | |
162 | "source ${loadaddr}\0" \ | |
163 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ | |
164 | "mmcboot=echo Booting from mmc ...; " \ | |
165 | "run mmcargs; " \ | |
166 | "bootm ${loadaddr}\0" \ | |
167 | "nandboot=echo Booting from nand ...; " \ | |
168 | "run nandargs; " \ | |
0b800a6b | 169 | "nand read ${loadaddr} 2a0000 400000; " \ |
36b4e2dd MR |
170 | "bootm ${loadaddr}\0" \ |
171 | ||
172 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 173 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
36b4e2dd MR |
174 | "if run loadbootscript; then " \ |
175 | "run bootscript; " \ | |
176 | "else " \ | |
177 | "if run loaduimage; then " \ | |
178 | "run mmcboot; " \ | |
179 | "else run nandboot; " \ | |
180 | "fi; " \ | |
181 | "fi; " \ | |
182 | "else run nandboot; fi" | |
183 | ||
36b4e2dd MR |
184 | /* |
185 | * Miscellaneous configurable options | |
186 | */ | |
41d7e702 IG |
187 | #define CONFIG_AUTO_COMPLETE |
188 | #define CONFIG_CMDLINE_EDITING | |
189 | #define CONFIG_TIMESTAMP | |
9fc376be | 190 | #define CONFIG_SYS_AUTOLOAD "no" |
36b4e2dd | 191 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
36b4e2dd MR |
192 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
193 | /* Print Buffer Size */ | |
194 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
195 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
196 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
197 | /* Boot Argument Buffer Size */ | |
198 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
199 | ||
200 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ | |
201 | /* works on */ | |
202 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
203 | 0x01F00000) /* 31MB */ | |
204 | ||
205 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ | |
206 | /* load address */ | |
207 | ||
208 | /* | |
209 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
210 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
211 | * This rate is divided by a local divisor. | |
212 | */ | |
213 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
214 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
36b4e2dd | 215 | |
36b4e2dd MR |
216 | /*----------------------------------------------------------------------- |
217 | * Physical Memory Map | |
218 | */ | |
219 | #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ | |
220 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
36b4e2dd | 221 | |
36b4e2dd MR |
222 | /*----------------------------------------------------------------------- |
223 | * FLASH and environment organization | |
224 | */ | |
225 | ||
226 | /* **** PISMO SUPPORT *** */ | |
36b4e2dd MR |
227 | /* Monitor at start of flash */ |
228 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
3530a35d | 229 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
36b4e2dd | 230 | |
9fc376be | 231 | #define CONFIG_ENV_IS_IN_NAND |
36b4e2dd | 232 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ |
6cbec7b3 | 233 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET |
36b4e2dd MR |
234 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET |
235 | ||
36b4e2dd | 236 | #if defined(CONFIG_CMD_NET) |
36b4e2dd MR |
237 | #define CONFIG_SMC911X |
238 | #define CONFIG_SMC911X_32_BIT | |
b65a77a8 IG |
239 | #define CM_T3X_SMC911X_BASE 0x2C000000 |
240 | #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) | |
241 | #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE | |
36b4e2dd MR |
242 | #endif /* (CONFIG_CMD_NET) */ |
243 | ||
244 | /* additions for new relocation code, must be added to all boards */ | |
245 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
246 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
247 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
248 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
249 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
250 | GENERATED_GBL_DATA_SIZE) | |
251 | ||
2b8754b2 | 252 | /* Status LED */ |
ebc18afd | 253 | #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ |
2b8754b2 | 254 | |
60e6bdcc NK |
255 | #define CONFIG_SPLASHIMAGE_GUARD |
256 | ||
2b8754b2 | 257 | /* GPIO banks */ |
2d8d190c | 258 | #ifdef CONFIG_LED_STATUS |
9fc376be | 259 | #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ |
2b8754b2 IG |
260 | #endif |
261 | ||
7878ca51 NK |
262 | /* Display Configuration */ |
263 | #define CONFIG_OMAP3_GPIO_2 | |
6f72892a | 264 | #define CONFIG_OMAP3_GPIO_5 |
7878ca51 NK |
265 | #define CONFIG_VIDEO_OMAP3 |
266 | #define LCD_BPP LCD_COLOR16 | |
267 | ||
f35034fe | 268 | #define CONFIG_SPLASH_SCREEN |
f82eb2fa | 269 | #define CONFIG_SPLASH_SOURCE |
f35034fe NK |
270 | #define CONFIG_CMD_BMP |
271 | #define CONFIG_BMP_16BPP | |
63c4f17b NK |
272 | #define CONFIG_SCF0403_LCD |
273 | ||
274 | #define CONFIG_OMAP3_SPI | |
7878ca51 | 275 | |
3e51b7c8 | 276 | /* Defines for SPL */ |
3e51b7c8 SR |
277 | #define CONFIG_SPL_FRAMEWORK |
278 | #define CONFIG_SPL_NAND_SIMPLE | |
279 | ||
e2ccdf89 | 280 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
205b4f33 | 281 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
3e51b7c8 SR |
282 | |
283 | #define CONFIG_SPL_BOARD_INIT | |
3e51b7c8 SR |
284 | #define CONFIG_SPL_NAND_BASE |
285 | #define CONFIG_SPL_NAND_DRIVERS | |
286 | #define CONFIG_SPL_NAND_ECC | |
3e51b7c8 | 287 | #define CONFIG_SPL_OMAP3_ID_NAND |
983e3700 | 288 | #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" |
3e51b7c8 SR |
289 | |
290 | /* NAND boot config */ | |
291 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
292 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
293 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
294 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
295 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
296 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
297 | /* | |
298 | * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: | |
299 | * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT | |
300 | */ | |
301 | #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ | |
302 | 10, 11, 12 } | |
303 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
304 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
305 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW | |
306 | ||
307 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
308 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
309 | ||
310 | #define CONFIG_SPL_TEXT_BASE 0x40200800 | |
fa2f81b0 TR |
311 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
312 | CONFIG_SPL_TEXT_BASE) | |
3e51b7c8 SR |
313 | |
314 | /* | |
315 | * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the | |
316 | * older x-loader implementations. And move the BSS area so that it | |
317 | * doesn't overlap with TEXT_BASE. | |
318 | */ | |
319 | #define CONFIG_SYS_TEXT_BASE 0x80008000 | |
320 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
321 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ | |
322 | ||
323 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
324 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
325 | ||
bcb447e1 NK |
326 | /* EEPROM */ |
327 | #define CONFIG_CMD_EEPROM | |
328 | #define CONFIG_ENV_EEPROM_IS_ON_I2C | |
329 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
330 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
331 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
332 | #define CONFIG_SYS_EEPROM_SIZE 256 | |
333 | ||
334 | #define CONFIG_CMD_EEPROM_LAYOUT | |
335 | #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3" | |
336 | ||
36b4e2dd | 337 | #endif /* __CONFIG_H */ |