[people/ms/u-boot.git] / include / configs / cm_t3517.h

/*
 * (C) Copyright 2013 CompuLab, Ltd.
 * Author: Igor Grinberg <grinberg@compulab.co.il>
 *
 * Configuration settings for the CompuLab CM-T3517 board
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_CM_T3517	/* working with CM-T3517 */

#define CONFIG_SYS_TEXT_BASE	0x80008000

/*
 * This is needed for the DMA stuff.
 * Although the default iss 64, we still define it
 * to be on the safe side once the default is changed.
 */

#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

#define CONFIG_MACH_TYPE                MACH_TYPE_CM_T3517

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

/*
 * The early kernel mapping on ARM currently only maps from the base of DRAM
 * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
 * so that leaves DRAM base to DRAM base + 0x4000 available.
 */
#define CONFIG_SYS_BOOTMAPSZ	        0x4000

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SERIAL_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/* USB */
#define CONFIG_USB_MUSB_AM35X

#ifndef CONFIG_USB_MUSB_AM35X
#define CONFIG_USB_OMAP3
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
#else /* !CONFIG_USB_MUSB_AM35X */
#define CONFIG_USB_MUSB_PIO_ONLY
#endif /* CONFIG_USB_MUSB_AM35X */

/* commands to include */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT		"nand0=nand"
#define MTDPARTS_DEFAULT	"mtdparts=nand:512k(x-loader),"\
				"1920k(u-boot),256k(u-boot-env),"\
				"4m(kernel),-(fs)"

#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	400000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_I2C_EEPROM_BUS	0
#define CONFIG_I2C_MULTI_BUS

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */

/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"baudrate=115200\0" \
	"console=ttyO2,115200n8\0" \
	"netretry=yes\0" \
	"mpurate=auto\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
	"mmcrootfstype=ext4\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=ubifs\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 2a0000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

/*
 * Miscellaneous configurable options
 */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_TIMESTAMP
#define CONFIG_SYS_AUTOLOAD		"no"
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	/* CM-T3517 DRAM is only on CS0 */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define CONFIG_SYS_CS0_SIZE		(256 << 20)

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#if defined(CONFIG_CMD_NET)
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE	(0x2C000000 + (16 << 20))
#define CONFIG_ARP_TIMEOUT		200UL
#define CONFIG_NET_RETRY_COUNT		5
#endif /* CONFIG_CMD_NET */

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
					 CONFIG_SYS_INIT_RAM_SIZE -	\
					 GENERATED_GBL_DATA_SIZE)

/* Status LED */
#define GREEN_LED_GPIO			186 /* CM-T3517 Green LED is GPIO186 */

/* Display Configuration */
#define CONFIG_VIDEO_OMAP3
#define LCD_BPP		LCD_COLOR16

#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASHIMAGE_GUARD
#define CONFIG_BMP_16BPP
#define CONFIG_SCF0403_LCD

#define CONFIG_OMAP3_SPI

/* EEPROM */
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
#define CONFIG_SYS_EEPROM_SIZE			256

#endif /* __CONFIG_H */
Commit	Line	Data
b09bf723 IG	1	/*
	2	* (C) Copyright 2013 CompuLab, Ltd.
	3	* Author: Igor Grinberg <grinberg@compulab.co.il>
	4	*
	5	* Configuration settings for the CompuLab CM-T3517 board
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	/*
	14	* High Level Configuration Options
	15	*/
b09bf723	16	#define CONFIG_CM_T3517 /* working with CM-T3517 */
b09bf723 IG	17
	18	#define CONFIG_SYS_TEXT_BASE 0x80008000
	19
	20	/*
	21	* This is needed for the DMA stuff.
	22	* Although the default iss 64, we still define it
	23	* to be on the safe side once the default is changed.
	24	*/
b09bf723 IG	25
	26	#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
	27
	28	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	29	#include <asm/arch/omap.h>
b09bf723	30
f3b44e8b DL	31	#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517
f3b44e8b DL	32
b09bf723 IG	33	/* Clock Defines */
	34	#define V_OSCK 26000000 /* Clock output from T2 */
	35	#define V_SCLK (V_OSCK >> 1)
	36
	37	#define CONFIG_MISC_INIT_R
	38
b09bf723 IG	39	/*
	40	* The early kernel mapping on ARM currently only maps from the base of DRAM
	41	* to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
	42	* The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
	43	* so that leaves DRAM base to DRAM base + 0x4000 available.
	44	*/
	45	#define CONFIG_SYS_BOOTMAPSZ 0x4000
	46
	47	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	48	#define CONFIG_SETUP_MEMORY_TAGS
	49	#define CONFIG_INITRD_TAG
	50	#define CONFIG_REVISION_TAG
	51	#define CONFIG_SERIAL_TAG
	52
	53	/*
	54	* Size of malloc() pool
	55	*/
2f6e4bf8	56	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
b09bf723 IG	57	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
	58
	59	/*
	60	* Hardware drivers
	61	*/
	62
	63	/*
	64	* NS16550 Configuration
	65	*/
b09bf723 IG	66	#define CONFIG_SYS_NS16550_SERIAL
	67	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	68	#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	69
	70	/*
	71	* select serial console configuration
	72	*/
	73	#define CONFIG_CONS_INDEX 3
	74	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	75	#define CONFIG_SERIAL3 3 /* UART3 */
b09bf723 IG	76
	77	/* allow to overwrite serial and ethaddr */
	78	#define CONFIG_ENV_OVERWRITE
b09bf723 IG	79	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	80	115200}
	81
011f5c13 IG	82	/* USB */
	83	#define CONFIG_USB_MUSB_AM35X
	84
	85	#ifndef CONFIG_USB_MUSB_AM35X
	86	#define CONFIG_USB_OMAP3
011f5c13 IG	87	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
	88	#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
	89	#else /* !CONFIG_USB_MUSB_AM35X */
95de1e2f	90	#define CONFIG_USB_MUSB_PIO_ONLY
011f5c13 IG	91	#endif /* CONFIG_USB_MUSB_AM35X */
011f5c13 IG	92
b09bf723	93	/* commands to include */
b09bf723 IG	94	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
	95	#define CONFIG_MTD_PARTITIONS
	96	#define MTDIDS_DEFAULT "nand0=nand"
	97	#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
	98	"1920k(u-boot),256k(u-boot-env),"\
	99	"4m(kernel),-(fs)"
	100
b09bf723 IG	101	#define CONFIG_SYS_I2C
	102	#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
	103	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	104	#define CONFIG_SYS_I2C_OMAP34XX
	105	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	106	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	107	#define CONFIG_SYS_I2C_EEPROM_BUS 0
	108	#define CONFIG_I2C_MULTI_BUS
	109
	110	/*
	111	* Board NAND Info.
	112	*/
b09bf723 IG	113	#define CONFIG_NAND_OMAP_GPMC
	114	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	115	/* to access nand */
	116	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	117	/* to access nand at */
	118	/* CS0 */
	119	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	120	/* devices */
	121
	122	/* Environment information */
b09bf723 IG	123	#define CONFIG_EXTRA_ENV_SETTINGS \
	124	"loadaddr=0x82000000\0" \
	125	"baudrate=115200\0" \
	126	"console=ttyO2,115200n8\0" \
e093d0b2	127	"netretry=yes\0" \
b09bf723 IG	128	"mpurate=auto\0" \
	129	"vram=12M\0" \
	130	"dvimode=1024x768MR-16@60\0" \
	131	"defaultdisplay=dvi\0" \
	132	"mmcdev=0\0" \
	133	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
	134	"mmcrootfstype=ext4\0" \
	135	"nandroot=/dev/mtdblock4 rw\0" \
	136	"nandrootfstype=ubifs\0" \
	137	"mmcargs=setenv bootargs console=${console} " \
	138	"mpurate=${mpurate} " \
	139	"vram=${vram} " \
	140	"omapfb.mode=dvi:${dvimode} " \
	141	"omapdss.def_disp=${defaultdisplay} " \
	142	"root=${mmcroot} " \
	143	"rootfstype=${mmcrootfstype}\0" \
	144	"nandargs=setenv bootargs console=${console} " \
	145	"mpurate=${mpurate} " \
	146	"vram=${vram} " \
	147	"omapfb.mode=dvi:${dvimode} " \
	148	"omapdss.def_disp=${defaultdisplay} " \
	149	"root=${nandroot} " \
	150	"rootfstype=${nandrootfstype}\0" \
	151	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	152	"bootscript=echo Running bootscript from mmc ...; " \
	153	"source ${loadaddr}\0" \
	154	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	155	"mmcboot=echo Booting from mmc ...; " \
	156	"run mmcargs; " \
	157	"bootm ${loadaddr}\0" \
	158	"nandboot=echo Booting from nand ...; " \
	159	"run nandargs; " \
	160	"nand read ${loadaddr} 2a0000 400000; " \
	161	"bootm ${loadaddr}\0" \
	162
b09bf723 IG	163	#define CONFIG_BOOTCOMMAND \
	164	"mmc dev ${mmcdev}; if mmc rescan; then " \
	165	"if run loadbootscript; then " \
	166	"run bootscript; " \
	167	"else " \
	168	"if run loaduimage; then " \
	169	"run mmcboot; " \
	170	"else run nandboot; " \
	171	"fi; " \
	172	"fi; " \
	173	"else run nandboot; fi"
	174
	175	/*
	176	* Miscellaneous configurable options
	177	*/
	178	#define CONFIG_AUTO_COMPLETE
	179	#define CONFIG_CMDLINE_EDITING
	180	#define CONFIG_TIMESTAMP
	181	#define CONFIG_SYS_AUTOLOAD "no"
	182	#define CONFIG_SYS_LONGHELP /* undef to save memory */
b09bf723 IG	183	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	184	/* Print Buffer Size */
	185	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	186	sizeof(CONFIG_SYS_PROMPT) + 16)
	187	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
	188	/* Boot Argument Buffer Size */
	189	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	190
	191	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
	192
	193	/*
	194	* AM3517 has 12 GP timers, they can be driven by the system clock
	195	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	196	* This rate is divided by a local divisor.
	197	*/
	198	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	199	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	200	#define CONFIG_SYS_HZ 1000
	201
	202	/*-----------------------------------------------------------------------
	203	* Physical Memory Map
	204	*/
	205	#define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */
	206	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	207	#define CONFIG_SYS_CS0_SIZE (256 << 20)
	208
	209	/*-----------------------------------------------------------------------
	210	* FLASH and environment organization
	211	*/
	212
	213	/* ** PISMO SUPPORT * */
	214	/* Monitor at start of flash */
	215	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	216	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
	217
b09bf723 IG	218	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	219	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	220	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
	221
a8a78c74 IG	222	#if defined(CONFIG_CMD_NET)
	223	#define CONFIG_DRIVER_TI_EMAC
	224	#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	225	#define CONFIG_MII
	226	#define CONFIG_SMC911X
	227	#define CONFIG_SMC911X_32_BIT
	228	#define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20))
e093d0b2 DL	229	#define CONFIG_ARP_TIMEOUT 200UL
e093d0b2 DL	230	#define CONFIG_NET_RETRY_COUNT 5
a8a78c74 IG	231	#endif /* CONFIG_CMD_NET */
a8a78c74 IG	232
b09bf723 IG	233	/* additions for new relocation code, must be added to all boards */
	234	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	235	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	236	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	237	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	238	CONFIG_SYS_INIT_RAM_SIZE - \
	239	GENERATED_GBL_DATA_SIZE)
	240
	241	/* Status LED */
b09bf723	242	#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */
b09bf723	243
40bbd52a	244	/* Display Configuration */
40bbd52a IG	245	#define CONFIG_VIDEO_OMAP3
	246	#define LCD_BPP LCD_COLOR16
	247
40bbd52a IG	248	#define CONFIG_SPLASH_SCREEN
40bbd52a IG	249	#define CONFIG_SPLASHIMAGE_GUARD
40bbd52a IG	250	#define CONFIG_BMP_16BPP
	251	#define CONFIG_SCF0403_LCD
	252
	253	#define CONFIG_OMAP3_SPI
	254
19a90ed6	255	/* EEPROM */
19a90ed6 NK	256	#define CONFIG_ENV_EEPROM_IS_ON_I2C
	257	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	258	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	259	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	260	#define CONFIG_SYS_EEPROM_SIZE 256
	261
b09bf723	262	#endif /* __CONFIG_H */