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0db5bca8 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Martin Winistoerfer, martinwinistoerfer@gmx.ch. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
8bde7f77 | 20 | * Foundation, |
0db5bca8 WD |
21 | */ |
22 | ||
23 | /* | |
24 | * File: cmi_mpc5xx.h | |
8bde7f77 WD |
25 | * |
26 | * Discription: Config header file for cmi | |
53677ef1 | 27 | * board using an MPC5xx CPU |
0db5bca8 WD |
28 | * |
29 | */ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
33 | ||
34 | /* | |
35 | * High Level Configuration Options | |
36 | */ | |
37 | ||
38 | #define CONFIG_MPC555 1 /* This is an MPC555 CPU */ | |
53677ef1 | 39 | #define CONFIG_CMI 1 /* Using the customized cmi board */ |
0db5bca8 WD |
40 | |
41 | /* Serial Console Configuration */ | |
42 | #define CONFIG_5xx_CONS_SCI1 | |
43 | #undef CONFIG_5xx_CONS_SCI2 | |
44 | ||
45 | #define CONFIG_BAUDRATE 57600 | |
46 | ||
0db5bca8 | 47 | |
80ff4f99 JL |
48 | /* |
49 | * BOOTP options | |
50 | */ | |
51 | #define CONFIG_BOOTP_BOOTFILESIZE | |
52 | #define CONFIG_BOOTP_BOOTPATH | |
53 | #define CONFIG_BOOTP_GATEWAY | |
54 | #define CONFIG_BOOTP_HOSTNAME | |
55 | ||
56 | ||
b730cda8 JL |
57 | /* |
58 | * Command line configuration. | |
59 | */ | |
60 | #include <config_cmd_default.h> | |
61 | ||
2d1f23aa WD |
62 | #undef CONFIG_CMD_NET /* disabeled - causes compile errors */ |
63 | ||
b730cda8 JL |
64 | #define CONFIG_CMD_MEMORY |
65 | #define CONFIG_CMD_LOADB | |
66 | #define CONFIG_CMD_REGINFO | |
67 | #define CONFIG_CMD_FLASH | |
68 | #define CONFIG_CMD_LOADS | |
69 | #define CONFIG_CMD_ASKENV | |
70 | #define CONFIG_CMD_BDI | |
71 | #define CONFIG_CMD_CONSOLE | |
72 | #define CONFIG_CMD_ENV | |
73 | #define CONFIG_CMD_RUN | |
74 | #define CONFIG_CMD_IMI | |
75 | ||
0db5bca8 WD |
76 | |
77 | #if 0 | |
78 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
79 | #else | |
80 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
81 | #endif | |
53677ef1 | 82 | #define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */ |
0db5bca8 WD |
83 | |
84 | #define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */ | |
85 | ||
53677ef1 | 86 | #define CONFIG_WATCHDOG /* turn on platform specific watchdog */ |
0db5bca8 | 87 | |
8bde7f77 | 88 | #define CONFIG_STATUS_LED 1 /* Enable status led */ |
0db5bca8 WD |
89 | |
90 | #define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ | |
91 | ||
92 | /* | |
8bde7f77 | 93 | * Miscellaneous configurable options |
0db5bca8 WD |
94 | */ |
95 | ||
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
97 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
b730cda8 | 98 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 99 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
0db5bca8 | 100 | #else |
6d0f6bcf | 101 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
0db5bca8 | 102 | #endif |
6d0f6bcf JCPV |
103 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
104 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
105 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
0db5bca8 | 106 | |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
108 | #define CONFIG_SYS_MEMTEST_END 0x000fa000 /* 1 MB in SRAM */ | |
0db5bca8 | 109 | |
6d0f6bcf | 110 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
0db5bca8 | 111 | |
6d0f6bcf | 112 | #define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ |
0db5bca8 | 113 | |
6d0f6bcf | 114 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } |
0db5bca8 WD |
115 | |
116 | ||
117 | /* | |
118 | * Low Level Configuration Settings | |
119 | */ | |
120 | ||
121 | /* | |
122 | * Internal Memory Mapped (This is not the IMMR content) | |
123 | */ | |
6d0f6bcf | 124 | #define CONFIG_SYS_IMMR 0x01000000 /* Physical start adress of internal memory map */ |
0db5bca8 WD |
125 | |
126 | /* | |
127 | * Definitions for initial stack pointer and data area | |
128 | */ | |
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ |
130 | #define CONFIG_SYS_INIT_RAM_END (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ | |
131 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */ | |
132 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_RAM_ADDR) - CONFIG_SYS_GBL_DATA_SIZE) /* Offset from the beginning of ram */ | |
133 | #define CONFIG_SYS_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */ | |
0db5bca8 WD |
134 | |
135 | /* | |
136 | * Start addresses for the final memory configuration | |
6d0f6bcf | 137 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
0db5bca8 | 138 | */ |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ |
140 | #define CONFIG_SYS_FLASH_BASE 0x02000000 /* External flash */ | |
0db5bca8 WD |
141 | #define PLD_BASE 0x03000000 /* PLD */ |
142 | #define ANYBUS_BASE 0x03010000 /* Anybus Module */ | |
143 | ||
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_RESET_ADRESS 0x01000000 /* Adress which causes reset */ |
145 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */ | |
53677ef1 WD |
146 | /* This adress is given to the linker with -Ttext to */ |
147 | /* locate the text section at this adress. */ | |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
149 | #define CONFIG_SYS_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */ | |
0db5bca8 WD |
150 | |
151 | /* | |
152 | * For booting Linux, the board info and command line data | |
153 | * have to be in the first 8 MB of memory, since this is | |
154 | * the maximum mapped by the Linux kernel during initialization. | |
155 | */ | |
6d0f6bcf | 156 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
0db5bca8 WD |
157 | |
158 | ||
159 | /*----------------------------------------------------------------------- | |
8bde7f77 | 160 | * FLASH organization |
0db5bca8 | 161 | *----------------------------------------------------------------------- |
8bde7f77 | 162 | * |
0db5bca8 WD |
163 | */ |
164 | ||
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of memory banks */ |
166 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */ | |
167 | #define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ | |
168 | #define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ | |
169 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Physically section protection on */ | |
0db5bca8 | 170 | |
5a1aceb0 | 171 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0db5bca8 | 172 | |
5a1aceb0 | 173 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
174 | #define CONFIG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ |
175 | #define CONFIG_ENV_SIZE 0x00010000 /* Set whole sector as env */ | |
6d0f6bcf | 176 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
0db5bca8 WD |
177 | #endif |
178 | ||
179 | /*----------------------------------------------------------------------- | |
8bde7f77 | 180 | * SYPCR - System Protection Control |
0db5bca8 WD |
181 | * SYPCR can only be written once after reset! |
182 | *----------------------------------------------------------------------- | |
183 | * SW Watchdog freeze | |
184 | */ | |
185 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 186 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
0db5bca8 WD |
187 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
188 | #else | |
6d0f6bcf | 189 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
8bde7f77 | 190 | SYPCR_SWP) |
0db5bca8 WD |
191 | #endif /* CONFIG_WATCHDOG */ |
192 | ||
193 | /*----------------------------------------------------------------------- | |
194 | * TBSCR - Time Base Status and Control | |
195 | *----------------------------------------------------------------------- | |
196 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
197 | */ | |
6d0f6bcf | 198 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
0db5bca8 WD |
199 | |
200 | /*----------------------------------------------------------------------- | |
201 | * PISCR - Periodic Interrupt Status and Control | |
202 | *----------------------------------------------------------------------- | |
203 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
204 | */ | |
6d0f6bcf | 205 | #define CONFIG_SYS_PISCR (PISCR_PITF) |
0db5bca8 WD |
206 | |
207 | /*----------------------------------------------------------------------- | |
208 | * SCCR - System Clock and reset Control Register | |
209 | *----------------------------------------------------------------------- | |
210 | * Set clock output, timebase and RTC source and divider, | |
211 | * power management and some other internal clocks | |
212 | */ | |
213 | #define SCCR_MASK SCCR_EBDF00 | |
6d0f6bcf | 214 | #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ |
0db5bca8 WD |
215 | SCCR_COM00 | SCCR_DFNL000 | SCCR_DFNH000) |
216 | ||
217 | /*----------------------------------------------------------------------- | |
218 | * SIUMCR - SIU Module Configuration | |
219 | *----------------------------------------------------------------------- | |
220 | * Data show cycle | |
221 | */ | |
6d0f6bcf | 222 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */ |
0db5bca8 WD |
223 | |
224 | /*----------------------------------------------------------------------- | |
225 | * PLPRCR - PLL, Low-Power, and Reset Control Register | |
226 | *----------------------------------------------------------------------- | |
227 | * Set all bits to 40 Mhz | |
8bde7f77 | 228 | * |
0db5bca8 | 229 | */ |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ |
231 | #define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) | |
8bde7f77 | 232 | |
0db5bca8 WD |
233 | |
234 | /*----------------------------------------------------------------------- | |
235 | * UMCR - UIMB Module Configuration Register | |
236 | *----------------------------------------------------------------------- | |
8bde7f77 | 237 | * |
0db5bca8 | 238 | */ |
6d0f6bcf | 239 | #define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ |
0db5bca8 WD |
240 | |
241 | /*----------------------------------------------------------------------- | |
242 | * ICTRL - I-Bus Support Control Register | |
243 | */ | |
6d0f6bcf | 244 | #define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ |
0db5bca8 WD |
245 | |
246 | /*----------------------------------------------------------------------- | |
247 | * USIU - Memory Controller Register | |
8bde7f77 | 248 | *----------------------------------------------------------------------- |
0db5bca8 WD |
249 | */ |
250 | ||
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16) |
252 | #define CONFIG_SYS_OR0_PRELIM (OR_ADDR_MK_FF | OR_SCY_3) | |
253 | #define CONFIG_SYS_BR1_PRELIM (ANYBUS_BASE) | |
254 | #define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR) | |
255 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_PS_32) | |
256 | #define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) | |
257 | #define CONFIG_SYS_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8) | |
258 | #define CONFIG_SYS_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \ | |
53677ef1 | 259 | OR_ACS_10 | OR_ETHR | OR_CSNT) |
0db5bca8 | 260 | |
6d0f6bcf | 261 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ |
0db5bca8 WD |
262 | |
263 | /*----------------------------------------------------------------------- | |
8bde7f77 | 264 | * DER - Timer Decrementer |
0db5bca8 WD |
265 | *----------------------------------------------------------------------- |
266 | * Initialise to zero | |
267 | */ | |
6d0f6bcf | 268 | #define CONFIG_SYS_DER 0x00000000 |
0db5bca8 WD |
269 | |
270 | ||
271 | /* | |
272 | * Internal Definitions | |
273 | * | |
274 | * Boot Flags | |
275 | */ | |
276 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
277 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
278 | ||
279 | #endif /* __CONFIG_H */ |