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rename CFG_ macros to CONFIG_SYS
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1/*
2 * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
3 * Anders Larsen <alarsen@rea.de>
4 *
5 * Configuation settings for the Cogent CSB637 board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/* ARM asynchronous clock */
30#define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */
31#define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */
32
33#define AT91_SLOW_CLOCK 32768 /* slow clock */
34
35#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
36#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
f5c254d7 37#define CONFIG_CSB637 1 /* on a CSB637 board */
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38#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39#define USE_920T_MMU 1
40
41#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
42#define CONFIG_SETUP_MEMORY_TAGS 1
43#define CONFIG_INITRD_TAG 1
44
45#ifndef CONFIG_SKIP_LOWLEVEL_INIT
6d0f6bcf 46#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
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47/* flash */
48#define MC_PUIA_VAL 0x00000000
49#define MC_PUP_VAL 0x00000000
50#define MC_PUER_VAL 0x00000000
51#define MC_ASR_VAL 0x00000000
52#define MC_AASR_VAL 0x00000000
53#define EBI_CFGR_VAL 0x00000000
480ed1de 54#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
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55
56/* clocks */
57#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */
58#define PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
59#define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
60
61/* sdram */
62#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
63#define PIOC_BSR_VAL 0x00000000
64#define PIOC_PDR_VAL 0xFFFF0000
65#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
66#define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */
67#define SDRAM 0x20000000 /* address of the SDRAM */
68#define SDRAM1 0x20000080 /* address of the SDRAM */
69#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
70#define SDRC_MR_VAL 0x00000002 /* Precharge All */
71#define SDRC_MR_VAL1 0x00000004 /* refresh */
72#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
73#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
74#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
75#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
76/*
77 * Size of malloc() pool
78 */
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79#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
80#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
645da510 81
f5c254d7 82#define CONFIG_BAUDRATE 115200
645da510 83
6d0f6bcf 84#define CONFIG_SYS_AT91C_BRGR_DIVISOR 75 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
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85
86/*
87 * Hardware drivers
88 */
89
90/* define one of these to choose the DBGU, USART0 or USART1 as console */
91#define CONFIG_DBGU
92#undef CONFIG_USART0
93#undef CONFIG_USART1
94
95#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
96
97#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
98
99#define CONFIG_BOOTDELAY 3
100/* #define CONFIG_ENV_OVERWRITE 1 */
101
37e4f24b 102
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103/*
104 * BOOTP options
105 */
106#define CONFIG_BOOTP_BOOTFILESIZE
107#define CONFIG_BOOTP_BOOTPATH
108#define CONFIG_BOOTP_GATEWAY
109#define CONFIG_BOOTP_HOSTNAME
110
111
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112/*
113 * Command line configuration.
114 */
115#include <config_cmd_default.h>
116
37e4f24b 117#define CONFIG_CMD_DHCP
3c95960e 118#define CONFIG_CMD_JFFS2
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119#define CONFIG_CMD_PING
120
3c95960e 121#ifdef NAND_SUPPORT_HAS_BEEN_FIXED /* NAND support is broken / unimplemented */
645da510 122
6d0f6bcf 123#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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124#define SECTORSIZE 512
125
126#define ADDR_COLUMN 1
127#define ADDR_PAGE 2
128#define ADDR_COLUMN_PAGE 3
129
130#define NAND_ChipID_UNKNOWN 0x00
131#define NAND_MAX_FLOORS 1
132#define NAND_MAX_CHIPS 1
133
134#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
135#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
136
3c95960e 137#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
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138#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
139#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
140
141#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
142
143#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
144#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
145#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
146#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
147/* the following are NOP's in our implementation */
148#define NAND_CTL_CLRALE(nandptr)
149#define NAND_CTL_SETALE(nandptr)
150#define NAND_CTL_CLRCLE(nandptr)
151#define NAND_CTL_SETCLE(nandptr)
152
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153#endif /* NAND_SUPPORT_HAS_BEEN_FIXED */
154
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155#define CONFIG_NR_DRAM_BANKS 1
156#define PHYS_SDRAM 0x20000000
157#define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */
158
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159#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
160#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4
161#define CONFIG_SYS_ALT_MEMTEST 1
162#define CONFIG_SYS_MEMTEST_SCRATCH CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 4
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163
164#define CONFIG_DRIVER_ETHER
165#define CONFIG_NET_RETRY_COUNT 20
166#undef CONFIG_AT91C_USE_RMII
167
168#undef CONFIG_HAS_DATAFLASH
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169#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
170#define CONFIG_SYS_MAX_DATAFLASH_BANKS 0
171#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
172#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
173#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
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174
175/*
176 * FLASH Device configuration
177 */
178#define PHYS_FLASH_1 0x10000000
179#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
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180#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
181#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */
00b1883a 182#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
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183#define CONFIG_SYS_FLASH_EMPTY_INFO
184#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
185#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
186#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
187#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
188#define CONFIG_SYS_MAX_FLASH_SECT 64
645da510 189
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190#define CONFIG_SYS_JFFS2_FIRST_BANK 0
191#define CONFIG_SYS_JFFS2_FIRST_SECTOR 3
192#define CONFIG_SYS_JFFS2_NUM_BANKS 1
645da510 193
057c849c 194#undef CONFIG_ENV_IS_IN_DATAFLASH
645da510 195
057c849c 196#ifdef CONFIG_ENV_IS_IN_DATAFLASH
0e8d1586 197#define CONFIG_ENV_OFFSET 0x20000
6d0f6bcf 198#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
0e8d1586 199#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
645da510 200#else
5a1aceb0 201#define CONFIG_ENV_IS_IN_FLASH 1
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202#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */
203#define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
057c849c 204#endif /* CONFIG_ENV_IS_IN_DATAFLASH */
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205
206
6d0f6bcf 207#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
645da510 208
6d0f6bcf 209#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
645da510 210
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211#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
212#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
213#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
214#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
645da510 215
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216#define CONFIG_SYS_HZ 1000
217#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
2c5260f7 218 /* AT91C_TC_TIMER_DIV1_CLOCK */
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219
220#define CONFIG_STACKSIZE (32*1024) /* regular stack */
221
222#ifdef CONFIG_USE_IRQ
223#error CONFIG_USE_IRQ not supported
224#endif
225
226#endif