[people/ms/u-boot.git] / include / configs / davinci_sonata.h

/*
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>

/*
 * Define this to make U-Boot skip low level initialization when loaded
 * by initial bootloader. Not required by NAND U-Boot version but IS
 * required for a NOR version used to burn the real NOR U-Boot into
 * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
 * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
 * NOR U-Boot is loaded directly from Flash so it must perform all the
 * low level initialization itself. NAND version is loaded by an initial
 * bootloader (UBL in TI-ese) that performs such an initialization so it's
 * skipped in NAND version. The third DaVinci boot mode loads a bootloader
 * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
 * performing low level init prior to loading. All that means we can NOT use
 * NAND version to put U-Boot into NOR because it doesn't have NOR support and
 * we can NOT use NOR version because it performs low level initialization
 * effectively destroying itself in DDR memory. That's why a separate NOR
 * version with this define is needed. It is loaded via UART, then one uses
 * it to somehow download a proper NOR version built WITHOUT this define to
 * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
 * NOR support into the initial bootloader so it won't be needed but DaVinci
 * static RAM might be too small for this (I have something like 2Kbytes left
 * as of now, without NOR support) so this might've not happened...
 *
#define CONFIG_NOR_UART_BOOT
 */

/*=======*/
/* Board */
/*=======*/
#define SONATA_BOARD
#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SYS_USE_NOR
/*===================*/
/* SoC Configuration */
/*===================*/
#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
#define CONFIG_SYS_CLK_FREQ	297000000	/* Arm Clock frequency */
#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
#define CONFIG_SYS_HZ			1000
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
/*====================================================*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
/*=============*/
/* Memory Info */
/*=============*/
#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 128*1024)	/* malloc() len */
#define CONFIG_SYS_GBL_DATA_SIZE	128		/* reserved for initial data */
#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
#define CONFIG_STACKSIZE	(256*1024)	/* regular stack */
#define PHYS_SDRAM_1		0x80000000	/* DDR Start */
#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
#define DDR_4BANKS				/* 4-bank DDR2 (128MB) */
/*====================*/
/* Serial Driver info */
/*====================*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	4		/* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK		27000000	/* Input clock to NS16550 */
#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
#define CONFIG_BAUDRATE		115200		/* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
/*===================*/
/* I2C Configuration */
/*===================*/
#define CONFIG_HARD_I2C
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED		80000	/* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_I2C_SLAVE		10	/* Bogus, master-only in U-Boot */
/*==================================*/
/* Network & Ethernet Configuration */
/*==================================*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT	10
/*=====================*/
/* Flash & Environment */
/*=====================*/
#ifdef CONFIG_SYS_USE_NAND
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
#define CONFIG_ENV_SECT_SIZE	512	/* Env sector Size */
#define CONFIG_ENV_SIZE		SZ_16K
#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
#define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
#define CONFIG_SYS_NAND_BASE		0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
#define NAND_MAX_CHIPS		1
#define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
#define DEF_BOOTM		""
#elif defined(CONFIG_SYS_USE_NOR)
#ifdef CONFIG_NOR_UART_BOOT
#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
#define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
#else
#undef CONFIG_SKIP_LOWLEVEL_INIT
#undef CONFIG_SKIP_RELOCATE_UBOOT
#endif
#define CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ	0x20000		/* 128KB sect size AMD Flash */
#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ*2)
#define PHYS_FLASH_1		0x02000000	/* CS2 Base address	 */
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1	/* Flash Base for U-Boot */
#define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB	 */
#define CONFIG_SYS_MAX_FLASH_SECT	(PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_FLASH_SECT_SZ	/* Env sector Size */
#endif
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
#undef	CONFIG_USE_IRQ			/* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
#define CONFIG_SYS_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print buffer sz */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* default Linux kernel load address */
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far, may be later */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/*===================*/
/* Linux Information */
/*===================*/
#define LINUX_BOOT_PARAM_ADDR	0x80000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS		"mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
#define CONFIG_BOOTCOMMAND	"setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000"
/*=================*/
/* U-Boot commands */
/*=================*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#ifdef CONFIG_SYS_USE_NAND
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#elif defined(CONFIG_SYS_USE_NOR)
#define CONFIG_CMD_JFFS2
#else
#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
#endif
/*=======================*/
/* KGDB support (if any) */
/*=======================*/
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	1	/* which serial port to use */
#endif
#endif /* __CONFIG_H */
Commit	Line	Data
c74b2108 SK	1	/*
	2	* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation; either version 2 of
	7	* the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	17	* MA 02111-1307 USA
	18	*/
	19
	20	#ifndef __CONFIG_H
	21	#define __CONFIG_H
	22	#include <asm/sizes.h>
	23
	24	/*
	25	* Define this to make U-Boot skip low level initialization when loaded
	26	* by initial bootloader. Not required by NAND U-Boot version but IS
	27	* required for a NOR version used to burn the real NOR U-Boot into
	28	* NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
	29	* so it is NOT possible to build a U-Boot with both NAND and NOR routines.
	30	* NOR U-Boot is loaded directly from Flash so it must perform all the
	31	* low level initialization itself. NAND version is loaded by an initial
	32	* bootloader (UBL in TI-ese) that performs such an initialization so it's
	33	* skipped in NAND version. The third DaVinci boot mode loads a bootloader
	34	* via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
	35	* performing low level init prior to loading. All that means we can NOT use
	36	* NAND version to put U-Boot into NOR because it doesn't have NOR support and
	37	* we can NOT use NOR version because it performs low level initialization
	38	* effectively destroying itself in DDR memory. That's why a separate NOR
	39	* version with this define is needed. It is loaded via UART, then one uses
	40	* it to somehow download a proper NOR version built WITHOUT this define to
	41	* RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
	42	* NOR support into the initial bootloader so it won't be needed but DaVinci
	43	* static RAM might be too small for this (I have something like 2Kbytes left
	44	* as of now, without NOR support) so this might've not happened...
	45	*
	46	#define CONFIG_NOR_UART_BOOT
	47	*/
	48
	49	/=======/
	50	/* Board */
	51	/=======/
	52	#define SONATA_BOARD
6d0f6bcf JCPV	53	#define CONFIG_SYS_NAND_SMALLPAGE
6d0f6bcf JCPV	54	#define CONFIG_SYS_USE_NOR
c74b2108 SK	55	/===================/
	56	/* SoC Configuration */
	57	/===================/
	58	#define CONFIG_ARM926EJS /* arm926ejs CPU core */
	59	#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
6d0f6bcf JCPV	60	#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
	61	#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
	62	#define CONFIG_SYS_HZ 1000
c74b2108 SK	63	/====================================================/
	64	/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
	65	/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
	66	/====================================================/
6d0f6bcf JCPV	67	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	68	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	69	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
	70	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
c74b2108 SK	71	/=============/
	72	/* Memory Info */
	73	/=============/
6d0f6bcf JCPV	74	#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1281024) / malloc() len */
	75	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
	76	#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
	77	#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
c74b2108 SK	78	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	79	#define CONFIG_STACKSIZE (2561024) / regular stack */
	80	#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
	81	#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
	82	#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
	83	/====================/
	84	/* Serial Driver info */
	85	/====================/
6d0f6bcf JCPV	86	#define CONFIG_SYS_NS16550
	87	#define CONFIG_SYS_NS16550_SERIAL
	88	#define CONFIG_SYS_NS16550_REG_SIZE 4 /* NS16550 register size */
	89	#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
	90	#define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */
c74b2108 SK	91	#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
c74b2108 SK	92	#define CONFIG_BAUDRATE 115200 /* Default baud rate */
6d0f6bcf	93	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
c74b2108 SK	94	/===================/
	95	/* I2C Configuration */
	96	/===================/
	97	#define CONFIG_HARD_I2C
	98	#define CONFIG_DRIVER_DAVINCI_I2C
6d0f6bcf JCPV	99	#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
6d0f6bcf JCPV	100	#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
c74b2108 SK	101	/==================================/
	102	/* Network & Ethernet Configuration */
	103	/==================================/
	104	#define CONFIG_DRIVER_TI_EMAC
	105	#define CONFIG_MII
	106	#define CONFIG_BOOTP_DEFAULT
	107	#define CONFIG_BOOTP_DNS
	108	#define CONFIG_BOOTP_DNS2
	109	#define CONFIG_BOOTP_SEND_HOSTNAME
	110	#define CONFIG_NET_RETRY_COUNT 10
	111	/=====================/
	112	/* Flash & Environment */
	113	/=====================/
6d0f6bcf	114	#ifdef CONFIG_SYS_USE_NAND
5a1aceb0	115	#undef CONFIG_ENV_IS_IN_FLASH
6d0f6bcf	116	#define CONFIG_SYS_NO_FLASH
51bfee19	117	#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
0e8d1586 JCPV	118	#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */
0e8d1586 JCPV	119	#define CONFIG_ENV_SIZE SZ_16K
c74b2108 SK	120	#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
c74b2108 SK	121	#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
6d0f6bcf JCPV	122	#define CONFIG_SYS_NAND_BASE 0x02000000
	123	#define CONFIG_SYS_NAND_HW_ECC
	124	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
c74b2108	125	#define NAND_MAX_CHIPS 1
0e8d1586	126	#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
c74b2108	127	#define DEF_BOOTM ""
6d0f6bcf	128	#elif defined(CONFIG_SYS_USE_NOR)
c74b2108 SK	129	#ifdef CONFIG_NOR_UART_BOOT
	130	#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
	131	#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
	132	#else
	133	#undef CONFIG_SKIP_LOWLEVEL_INIT
	134	#undef CONFIG_SKIP_RELOCATE_UBOOT
	135	#endif
5a1aceb0	136	#define CONFIG_ENV_IS_IN_FLASH
6d0f6bcf	137	#undef CONFIG_SYS_NO_FLASH
00b1883a	138	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	139	#define CONFIG_SYS_FLASH_CFI
	140	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
	141	#define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */
	142	#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*2)
53677ef1	143	#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
6d0f6bcf	144	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
53677ef1	145	#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
6d0f6bcf JCPV	146	#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
6d0f6bcf JCPV	147	#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */
c74b2108 SK	148	#endif
	149	/==============================/
	150	/* U-Boot general configuration */
	151	/==============================/
53677ef1	152	#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
c74b2108 SK	153	#define CONFIG_MISC_INIT_R
	154	#undef CONFIG_BOOTDELAY
	155	#define CONFIG_BOOTFILE "uImage" /* Boot file name */
6d0f6bcf JCPV	156	#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
	157	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	158	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
	159	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	160	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	161	#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
c74b2108 SK	162	#define CONFIG_VERSION_VARIABLE
c74b2108 SK	163	#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
6d0f6bcf JCPV	164	#define CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	165	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
c74b2108	166	#define CONFIG_CMDLINE_EDITING
6d0f6bcf	167	#define CONFIG_SYS_LONGHELP
c74b2108 SK	168	#define CONFIG_CRC32_VERIFY
	169	#define CONFIG_MX_CYCLIC
	170	/===================/
	171	/* Linux Information */
	172	/===================/
	173	#define LINUX_BOOT_PARAM_ADDR 0x80000100
	174	#define CONFIG_CMDLINE_TAG
	175	#define CONFIG_SETUP_MEMORY_TAGS
	176	#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
	177	#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000"
	178	/=================/
	179	/* U-Boot commands */
	180	/=================/
	181	#include <config_cmd_default.h>
	182	#define CONFIG_CMD_ASKENV
	183	#define CONFIG_CMD_DHCP
	184	#define CONFIG_CMD_DIAG
	185	#define CONFIG_CMD_I2C
	186	#define CONFIG_CMD_MII
	187	#define CONFIG_CMD_PING
	188	#define CONFIG_CMD_SAVES
	189	#define CONFIG_CMD_EEPROM
	190	#undef CONFIG_CMD_BDI
	191	#undef CONFIG_CMD_FPGA
	192	#undef CONFIG_CMD_SETGETDCR
6d0f6bcf	193	#ifdef CONFIG_SYS_USE_NAND
c74b2108 SK	194	#undef CONFIG_CMD_FLASH
	195	#undef CONFIG_CMD_IMLS
	196	#define CONFIG_CMD_NAND
6d0f6bcf	197	#elif defined(CONFIG_SYS_USE_NOR)
c74b2108 SK	198	#define CONFIG_CMD_JFFS2
c74b2108 SK	199	#else
6d0f6bcf	200	#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
c74b2108 SK	201	#endif
	202	/=======================/
	203	/* KGDB support (if any) */
	204	/=======================/
	205	#ifdef CONFIG_CMD_KGDB
	206	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
	207	#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
	208	#endif
	209	#endif /* __CONFIG_H */