[people/ms/u-boot.git] / include / configs / debris.h

/*
 * (C) Copyright 2001, 2002
 * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

/* Environments */

/* bootargs */
#define CONFIG_BOOTARGS \
	"console=ttyS0,9600 init=/linuxrc " \
	"root=/dev/nfs rw nfsroot=192.168.0.1:" \
	"/tftpboot/target " \
	"ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
	"255.255.255.0:debris:eth0:none " \
	"mtdparts=phys:12m(root),-(kernel)"

/* bootcmd */
#define CONFIG_BOOTCOMMAND \
	"tftp 800000 pImage; " \
	"setenv bootargs console=ttyS0,9600 init=/linuxrc " \
	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	"${netmask}:${hostname}:eth0:none " \
	"mtdparts=phys:12m(root),-(kernel); " \
	"bootm 800000"

/* bootdelay */
#define CONFIG_BOOTDELAY	5	/* autoboot 5s */

/* baudrate */
#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/

/* loads_echo */
#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */

/* ethaddr */
#undef CONFIG_ETHADDR

/* eth2addr */
#undef CONFIG_ETH2ADDR

/* eth3addr */
#undef CONFIG_ETH3ADDR

/* ipaddr */
#define CONFIG_IPADDR	192.168.0.2

/* serverip */
#define CONFIG_SERVERIP	192.168.0.1

/* autoload */
#undef CONFIG_SYS_AUTOLOAD

/* rootpath */
#define CONFIG_ROOTPATH /tftpboot/target

/* gatewayip */
#define CONFIG_GATEWAYIP 192.168.0.1

/* netmask */
#define CONFIG_NETMASK 255.255.255.0

/* hostname */
#define CONFIG_HOSTNAME debris

/* bootfile */
#define CONFIG_BOOTFILE pImage

/* loadaddr */
#define CONFIG_LOADADDR 800000

/* preboot */
#undef CONFIG_PREBOOT

/* clocks_in_mhz */
#undef CONFIG_CLOCKS_IN_MHZ


/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1
#define CONFIG_DEBRIS		1

#if 0
#define USE_DINK32		1
#else
#undef USE_DINK32
#endif

#define CONFIG_CONS_INDEX       1
#define CONFIG_BAUDRATE		9600
#define CONFIG_DRAM_SPEED	100		/* MHz */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_KGBD
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_SDRAM


/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI				/* include pci support		*/
#define CONFIG_PCI_PNP

#define CONFIG_NET_MULTI		/* Multi ethernet cards support */
#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100  */
#define CONFIG_EEPRO100_SROM_WRITE

#define PCI_ENET0_IOADDR	0x80000000
#define PCI_ENET0_MEMADDR	0x80000000
#define	PCI_ENET1_IOADDR	0x81000000
#define	PCI_ENET1_MEMADDR	0x81000000
/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_MAX_RAM_SIZE	0x20000000
#define CONFIG_VERY_BIG_RAM

#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100

#if defined (USE_DINK32)
#define CONFIG_SYS_MONITOR_LEN		0x00040000
#define CONFIG_SYS_MONITOR_BASE	0x00090000
#define CONFIG_SYS_RAMBOOT		1
#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_INIT_RAM_END	0x10000
#define CONFIG_SYS_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#else
#undef	CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_MONITOR_LEN		0x00040000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE

/*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
#define CONFIG_SYS_GBL_DATA_SIZE	128

#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
#define CONFIG_SYS_INIT_RAM_END      0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)

#endif

#define CONFIG_SYS_FLASH_BASE		0x7C000000
#define CONFIG_SYS_FLASH_SIZE		(16*1024*1024)	/* debris has tiny eeprom	*/

#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/

#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/

#define CONFIG_SYS_EUMB_ADDR		0xFC000000

#define CONFIG_SYS_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
#define CONFIG_SYS_FLASH_RANGE_SIZE	0x01000000
#define FLASH_BASE0_PRELIM	0x7C000000	/* debris flash		*/

/*
 * JFFS2 partitions
 *
 */
/* No command line, one static partition, whole device */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */

/* Use first bank for JFFS2, second bank contains U-Boot.
 *
 * Note: fake mtd_id's used, no linux mtd map file.
 */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT		"nor0=debris-0"
#define MTDPARTS_DEFAULT	"mtdparts=debris-0:-(jffs2)"
*/

#define CONFIG_ENV_IS_IN_NVRAM      1
#define CONFIG_ENV_OVERWRITE     1
#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
#define CONFIG_ENV_ADDR		0xFF000000 /* right at the start of NVRAM  */
#define CONFIG_ENV_SIZE		0x400	/* Size of the Environment - 8K	   */
#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning */

#define CONFIG_SYS_NVRAM_BASE_ADDR	0xff000000

/*
 * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
 * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
 */
#define CONFIG_SYS_NVRAM_VXWORKS_OFFS	0x6900

/*
 * select i2c support configuration
 *
 * Supported configurations are {none, software, hardware} drivers.
 * If the software driver is chosen, there are some additional
 * configuration items that the driver uses to drive the port pins.
 */
#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
#undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F

#ifdef CONFIG_SOFT_I2C
#error "Soft I2C is not configured properly.  Please review!"
#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
#define I2C_READ		((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
				else    iop->pdat &= ~0x00010000
#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
				else    iop->pdat &= ~0x00020000
#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
#endif /* CONFIG_SOFT_I2C */

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM }

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE	1

#define CONFIG_SYS_NS16550_CLK		7372800

#define CONFIG_SYS_NS16550_COM1	0xFF080000
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_NS16550_COM1 + 8)
#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_NS16550_COM1 + 16)
#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_NS16550_COM1 + 24)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3

#define CONFIG_SYS_DLL_EXTEND		0x00
#define CONFIG_SYS_PCI_HOLD_DEL	0x20

#define CONFIG_SYS_ROMNAL	15	/* rom/flash next access time */
#define CONFIG_SYS_ROMFAL	31	/* rom/flash access time */

#define CONFIG_SYS_REFINT	430	/* # of clocks between CBR refresh cycles */

#define CONFIG_SYS_DBUS_SIZE2	1	/* set for 8-bit RCS1, clear for 32,64 */

/* the following are for SDRAM only*/
#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
#define CONFIG_SYS_REFREC	8	/* Refresh to activate interval		*/
#define CONFIG_SYS_RDLAT	4	/* data latency from read command	*/
#define CONFIG_SYS_PRETOACT	3	/* Precharge to activate interval	*/
#define CONFIG_SYS_ACTTOPRE	5	/* Activate to Precharge interval	*/
#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
#if 0
#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
#endif

#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
#define CONFIG_SYS_EXTROM 1
#define CONFIG_SYS_REGDIMM 0


/* memory bank settings*/
/*
 * only bits 20-29 are actually used from these vales to set the
 * start/end address the upper two bits will be 0, and the lower 20
 * bits will be set to 0x00000 for a start address, or 0xfffff for an
 * end address
 */
#define CONFIG_SYS_BANK0_START		0x00000000
#define CONFIG_SYS_BANK0_END		(0x4000000 - 1)
#define CONFIG_SYS_BANK0_ENABLE	1
#define CONFIG_SYS_BANK1_START		0x04000000
#define CONFIG_SYS_BANK1_END		(0x8000000 - 1)
#define CONFIG_SYS_BANK1_ENABLE	1
#define CONFIG_SYS_BANK2_START		0x3ff00000
#define CONFIG_SYS_BANK2_END		0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE	0
#define CONFIG_SYS_BANK3_START		0x3ff00000
#define CONFIG_SYS_BANK3_END		0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE	0
#define CONFIG_SYS_BANK4_START		0x00000000
#define CONFIG_SYS_BANK4_END		0x00000000
#define CONFIG_SYS_BANK4_ENABLE	0
#define CONFIG_SYS_BANK5_START		0x00000000
#define CONFIG_SYS_BANK5_END		0x00000000
#define CONFIG_SYS_BANK5_ENABLE	0
#define CONFIG_SYS_BANK6_START		0x00000000
#define CONFIG_SYS_BANK6_END		0x00000000
#define CONFIG_SYS_BANK6_ENABLE	0
#define CONFIG_SYS_BANK7_START		0x00000000
#define CONFIG_SYS_BANK7_END		0x00000000
#define CONFIG_SYS_BANK7_ENABLE	0
/*
 * Memory bank enable bitmask, specifying which of the banks defined above
 are actually present. MSB is for bank #7, LSB is for bank #0.
 */
#define CONFIG_SYS_BANK_ENABLE		0x01

#define CONFIG_SYS_ODCR		0x75	/* configures line driver impedances,	*/
					/* see 8240 book for bit definitions	*/
#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
					/* currently accessed page in memory	*/
					/* see 8240 book for details		*/

/* SDRAM 0 - 256MB */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* stack in DCACHE @ 1GB (no backing mem) */
#if defined(USE_DINK32)
#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
#else
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#endif

/* PCI memory */
#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

/* Flash, config addrs, etc */
#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/* values according to the manual */

#define CONFIG_DRAM_50MHZ	1
#define CONFIG_SDRAM_50MHZ

#define CONFIG_DISK_SPINUP_TIME 1000000

#endif	/* __CONFIG_H */
Commit	Line	Data
15647dc7 WD	1	/*
	2	* (C) Copyright 2001, 2002
	3	* Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/* ------------------------------------------------------------------------- */
	25
	26	/*
	27	* board/config.h - configuration options, board specific
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32
2ae18241 WD	33	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
2ae18241 WD	34
15647dc7 WD	35	/* Environments */
	36
	37	/* bootargs */
	38	#define CONFIG_BOOTARGS \
	39	"console=ttyS0,9600 init=/linuxrc " \
	40	"root=/dev/nfs rw nfsroot=192.168.0.1:" \
	41	"/tftpboot/target " \
	42	"ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
	43	"255.255.255.0:debris:eth0:none " \
	44	"mtdparts=phys:12m(root),-(kernel)"
	45
	46	/* bootcmd */
	47	#define CONFIG_BOOTCOMMAND \
	48	"tftp 800000 pImage; " \
	49	"setenv bootargs console=ttyS0,9600 init=/linuxrc " \
fe126d8b WD	50	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	51	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	52	"${netmask}:${hostname}:eth0:none " \
15647dc7 WD	53	"mtdparts=phys:12m(root),-(kernel); " \
	54	"bootm 800000"
	55
	56	/* bootdelay */
	57	#define CONFIG_BOOTDELAY 5 /* autoboot 5s */
	58
	59	/* baudrate */
	60	#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
	61
	62	/* loads_echo */
	63	#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
	64
	65	/* ethaddr */
	66	#undef CONFIG_ETHADDR
	67
	68	/* eth2addr */
	69	#undef CONFIG_ETH2ADDR
	70
	71	/* eth3addr */
	72	#undef CONFIG_ETH3ADDR
	73
	74	/* ipaddr */
	75	#define CONFIG_IPADDR 192.168.0.2
	76
	77	/* serverip */
	78	#define CONFIG_SERVERIP 192.168.0.1
	79
	80	/* autoload */
6d0f6bcf	81	#undef CONFIG_SYS_AUTOLOAD
15647dc7 WD	82
	83	/* rootpath */
	84	#define CONFIG_ROOTPATH /tftpboot/target
	85
	86	/* gatewayip */
	87	#define CONFIG_GATEWAYIP 192.168.0.1
	88
	89	/* netmask */
	90	#define CONFIG_NETMASK 255.255.255.0
	91
	92	/* hostname */
	93	#define CONFIG_HOSTNAME debris
	94
	95	/* bootfile */
	96	#define CONFIG_BOOTFILE pImage
	97
	98	/* loadaddr */
	99	#define CONFIG_LOADADDR 800000
	100
	101	/* preboot */
	102	#undef CONFIG_PREBOOT
	103
	104	/* clocks_in_mhz */
	105	#undef CONFIG_CLOCKS_IN_MHZ
	106
	107
	108	/*
	109	* High Level Configuration Options
	110	* (easy to change)
	111	*/
	112
	113	#define CONFIG_MPC824X 1
	114	#define CONFIG_MPC8245 1
	115	#define CONFIG_DEBRIS 1
	116
	117	#if 0
	118	#define USE_DINK32 1
	119	#else
	120	#undef USE_DINK32
	121	#endif
	122
	123	#define CONFIG_CONS_INDEX 1
	124	#define CONFIG_BAUDRATE 9600
	125	#define CONFIG_DRAM_SPEED 100 /* MHz */
	126
ab999ba1	127
80ff4f99 JL	128	/*
	129	* BOOTP options
	130	*/
	131	#define CONFIG_BOOTP_BOOTFILESIZE
	132	#define CONFIG_BOOTP_BOOTPATH
	133	#define CONFIG_BOOTP_GATEWAY
	134	#define CONFIG_BOOTP_HOSTNAME
	135
	136
ab999ba1 JL	137	/*
	138	* Command line configuration.
	139	*/
	140	#include <config_cmd_default.h>
	141
	142	#define CONFIG_CMD_ASKENV
	143	#define CONFIG_CMD_CACHE
	144	#define CONFIG_CMD_DATE
	145	#define CONFIG_CMD_DHCP
	146	#define CONFIG_CMD_DIAG
	147	#define CONFIG_CMD_EEPROM
	148	#define CONFIG_CMD_ELF
	149	#define CONFIG_CMD_I2C
	150	#define CONFIG_CMD_JFFS2
	151	#define CONFIG_CMD_KGBD
	152	#define CONFIG_CMD_PCI
	153	#define CONFIG_CMD_PING
	154	#define CONFIG_CMD_SAVES
	155	#define CONFIG_CMD_SDRAM
15647dc7 WD	156
	157
	158	/*
	159	* Miscellaneous configurable options
	160	*/
6d0f6bcf JCPV	161	#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
	162	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	163	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	164	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	165	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	166	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	167	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
	168	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
15647dc7 WD	169
	170	/*-----------------------------------------------------------------------
	171	* PCI stuff
	172	*-----------------------------------------------------------------------
	173	*/
	174	#define CONFIG_PCI /* include pci support */
	175	#define CONFIG_PCI_PNP
	176
	177	#define CONFIG_NET_MULTI /* Multi ethernet cards support */
	178	#define CONFIG_EEPRO100
6d0f6bcf	179	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
15647dc7 WD	180	#define CONFIG_EEPRO100_SROM_WRITE
	181
	182	#define PCI_ENET0_IOADDR 0x80000000
	183	#define PCI_ENET0_MEMADDR 0x80000000
	184	#define PCI_ENET1_IOADDR 0x81000000
	185	#define PCI_ENET1_MEMADDR 0x81000000
	186	/*-----------------------------------------------------------------------
	187	* Start addresses for the final memory configuration
	188	* (Set up by the startup code)
6d0f6bcf	189	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
15647dc7	190	*/
6d0f6bcf JCPV	191	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	192	#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
7abf0c58	193	#define CONFIG_VERY_BIG_RAM
15647dc7	194
6d0f6bcf	195	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
15647dc7 WD	196
15647dc7 WD	197	#if defined (USE_DINK32)
6d0f6bcf JCPV	198	#define CONFIG_SYS_MONITOR_LEN 0x00040000
	199	#define CONFIG_SYS_MONITOR_BASE 0x00090000
	200	#define CONFIG_SYS_RAMBOOT 1
	201	#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	202	#define CONFIG_SYS_INIT_RAM_END 0x10000
	203	#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
	204	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	205	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
15647dc7	206	#else
6d0f6bcf JCPV	207	#undef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	208	#define CONFIG_SYS_MONITOR_LEN 0x00040000
14d0a02a	209	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
15647dc7	210
6d0f6bcf JCPV	211	/#define CONFIG_SYS_GBL_DATA_SIZE 256/
6d0f6bcf JCPV	212	#define CONFIG_SYS_GBL_DATA_SIZE 128
15647dc7	213
6d0f6bcf JCPV	214	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
	215	#define CONFIG_SYS_INIT_RAM_END 0x1000
	216	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
15647dc7 WD	217
	218	#endif
	219
6d0f6bcf JCPV	220	#define CONFIG_SYS_FLASH_BASE 0x7C000000
6d0f6bcf JCPV	221	#define CONFIG_SYS_FLASH_SIZE (1610241024) /* debris has tiny eeprom */
15647dc7	222
6d0f6bcf	223	#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
15647dc7	224
6d0f6bcf JCPV	225	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
6d0f6bcf JCPV	226	#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
15647dc7	227
6d0f6bcf	228	#define CONFIG_SYS_EUMB_ADDR 0xFC000000
15647dc7	229
6d0f6bcf JCPV	230	#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
6d0f6bcf JCPV	231	#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
15647dc7 WD	232	#define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */
15647dc7 WD	233
700a0c64 WD	234	/*
	235	* JFFS2 partitions
	236	*
	237	*/
	238	/* No command line, one static partition, whole device */
68d7d651	239	#undef CONFIG_CMD_MTDPARTS
700a0c64 WD	240	#define CONFIG_JFFS2_DEV "nor0"
	241	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	242	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	243
	244	/* mtdparts command line support */
	245
	246	/* Use first bank for JFFS2, second bank contains U-Boot.
	247	*
	248	* Note: fake mtd_id's used, no linux mtd map file.
	249	*/
	250	/*
68d7d651	251	#define CONFIG_CMD_MTDPARTS
700a0c64 WD	252	#define MTDIDS_DEFAULT "nor0=debris-0"
	253	#define MTDPARTS_DEFAULT "mtdparts=debris-0:-(jffs2)"
	254	*/
15647dc7	255
9314cee6	256	#define CONFIG_ENV_IS_IN_NVRAM 1
15647dc7	257	#define CONFIG_ENV_OVERWRITE 1
6d0f6bcf	258	#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
0e8d1586 JCPV	259	#define CONFIG_ENV_ADDR 0xFF000000 /* right at the start of NVRAM */
	260	#define CONFIG_ENV_SIZE 0x400 /* Size of the Environment - 8K */
	261	#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
15647dc7	262
6d0f6bcf	263	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xff000000
15647dc7 WD	264
15647dc7 WD	265	/*
6d0f6bcf	266	* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
15647dc7 WD	267	* NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
15647dc7 WD	268	*/
6d0f6bcf	269	#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900
15647dc7 WD	270
	271	/*
	272	* select i2c support configuration
	273	*
	274	* Supported configurations are {none, software, hardware} drivers.
	275	* If the software driver is chosen, there are some additional
	276	* configuration items that the driver uses to drive the port pins.
	277	*/
	278	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
	279	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	280	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	281	#define CONFIG_SYS_I2C_SLAVE 0x7F
15647dc7 WD	282
	283	#ifdef CONFIG_SOFT_I2C
	284	#error "Soft I2C is not configured properly. Please review!"
	285	#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
	286	#define I2C_ACTIVE (iop->pdir \|= 0x00010000)
	287	#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
	288	#define I2C_READ ((iop->pdat & 0x00010000) != 0)
	289	#define I2C_SDA(bit) if(bit) iop->pdat \|= 0x00010000; \
	290	else iop->pdat &= ~0x00010000
	291	#define I2C_SCL(bit) if(bit) iop->pdat \|= 0x00020000; \
	292	else iop->pdat &= ~0x00020000
	293	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	294	#endif /* CONFIG_SOFT_I2C */
	295
6d0f6bcf JCPV	296	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
	297	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
	298	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	299	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
15647dc7	300
6d0f6bcf JCPV	301	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
6d0f6bcf JCPV	302	#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
15647dc7 WD	303
	304	/*-----------------------------------------------------------------------
	305	* Definitions for initial stack pointer and data area (in DPRAM)
	306	*/
	307
	308	/*
	309	* NS16550 Configuration
	310	*/
6d0f6bcf JCPV	311	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	312	#define CONFIG_SYS_NS16550_SERIAL
15647dc7	313
6d0f6bcf	314	#define CONFIG_SYS_NS16550_REG_SIZE 1
15647dc7	315
6d0f6bcf	316	#define CONFIG_SYS_NS16550_CLK 7372800
15647dc7	317
6d0f6bcf JCPV	318	#define CONFIG_SYS_NS16550_COM1 0xFF080000
	319	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_NS16550_COM1 + 8)
	320	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_NS16550_COM1 + 16)
	321	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_NS16550_COM1 + 24)
15647dc7 WD	322
	323	/*
	324	* Low Level Configuration Settings
	325	* (address mappings, register initial values, etc.)
	326	* You should know what you are doing if you make changes here.
	327	*/
	328
	329	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	330	#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
	331
6d0f6bcf JCPV	332	#define CONFIG_SYS_DLL_EXTEND 0x00
6d0f6bcf JCPV	333	#define CONFIG_SYS_PCI_HOLD_DEL 0x20
15647dc7	334
6d0f6bcf JCPV	335	#define CONFIG_SYS_ROMNAL 15 /* rom/flash next access time */
6d0f6bcf JCPV	336	#define CONFIG_SYS_ROMFAL 31 /* rom/flash access time */
15647dc7	337
6d0f6bcf	338	#define CONFIG_SYS_REFINT 430 /* # of clocks between CBR refresh cycles */
15647dc7	339
6d0f6bcf	340	#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
15647dc7 WD	341
15647dc7 WD	342	/* the following are for SDRAM only*/
6d0f6bcf JCPV	343	#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
	344	#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
	345	#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
	346	#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
	347	#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
	348	#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
	349	#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
	350	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
15647dc7	351	#if 0
6d0f6bcf	352	#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
15647dc7 WD	353	#endif
15647dc7 WD	354
6d0f6bcf JCPV	355	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
	356	#define CONFIG_SYS_EXTROM 1
	357	#define CONFIG_SYS_REGDIMM 0
15647dc7 WD	358
	359
	360	/* memory bank settings*/
	361	/*
	362	* only bits 20-29 are actually used from these vales to set the
	363	* start/end address the upper two bits will be 0, and the lower 20
	364	* bits will be set to 0x00000 for a start address, or 0xfffff for an
	365	* end address
	366	*/
6d0f6bcf JCPV	367	#define CONFIG_SYS_BANK0_START 0x00000000
	368	#define CONFIG_SYS_BANK0_END (0x4000000 - 1)
	369	#define CONFIG_SYS_BANK0_ENABLE 1
	370	#define CONFIG_SYS_BANK1_START 0x04000000
	371	#define CONFIG_SYS_BANK1_END (0x8000000 - 1)
	372	#define CONFIG_SYS_BANK1_ENABLE 1
	373	#define CONFIG_SYS_BANK2_START 0x3ff00000
	374	#define CONFIG_SYS_BANK2_END 0x3fffffff
	375	#define CONFIG_SYS_BANK2_ENABLE 0
	376	#define CONFIG_SYS_BANK3_START 0x3ff00000
	377	#define CONFIG_SYS_BANK3_END 0x3fffffff
	378	#define CONFIG_SYS_BANK3_ENABLE 0
	379	#define CONFIG_SYS_BANK4_START 0x00000000
	380	#define CONFIG_SYS_BANK4_END 0x00000000
	381	#define CONFIG_SYS_BANK4_ENABLE 0
	382	#define CONFIG_SYS_BANK5_START 0x00000000
	383	#define CONFIG_SYS_BANK5_END 0x00000000
	384	#define CONFIG_SYS_BANK5_ENABLE 0
	385	#define CONFIG_SYS_BANK6_START 0x00000000
	386	#define CONFIG_SYS_BANK6_END 0x00000000
	387	#define CONFIG_SYS_BANK6_ENABLE 0
	388	#define CONFIG_SYS_BANK7_START 0x00000000
	389	#define CONFIG_SYS_BANK7_END 0x00000000
	390	#define CONFIG_SYS_BANK7_ENABLE 0
15647dc7 WD	391	/*
	392	* Memory bank enable bitmask, specifying which of the banks defined above
	393	are actually present. MSB is for bank #7, LSB is for bank #0.
	394	*/
6d0f6bcf	395	#define CONFIG_SYS_BANK_ENABLE 0x01
15647dc7	396
6d0f6bcf	397	#define CONFIG_SYS_ODCR 0x75 /* configures line driver impedances, */
15647dc7	398	/* see 8240 book for bit definitions */
6d0f6bcf	399	#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
15647dc7 WD	400	/* currently accessed page in memory */
	401	/* see 8240 book for details */
	402
	403	/* SDRAM 0 - 256MB */
6d0f6bcf JCPV	404	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	405	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
15647dc7 WD	406
	407	/* stack in DCACHE @ 1GB (no backing mem) */
	408	#if defined(USE_DINK32)
6d0f6bcf JCPV	409	#define CONFIG_SYS_IBAT1L (0x40000000 \| BATL_PP_00 )
6d0f6bcf JCPV	410	#define CONFIG_SYS_IBAT1U (0x40000000 \| BATU_BL_128K )
15647dc7	411	#else
6d0f6bcf JCPV	412	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	413	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
15647dc7 WD	414	#endif
	415
	416	/* PCI memory */
6d0f6bcf JCPV	417	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
6d0f6bcf JCPV	418	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
15647dc7 WD	419
15647dc7 WD	420	/* Flash, config addrs, etc */
6d0f6bcf JCPV	421	#define CONFIG_SYS_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	422	#define CONFIG_SYS_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	423
	424	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	425	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	426	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	427	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	428	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	429	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	430	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	431	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
15647dc7 WD	432
	433	/*
	434	* For booting Linux, the board info and command line data
	435	* have to be in the first 8 MB of memory, since this is
	436	* the maximum mapped by the Linux kernel during initialization.
	437	*/
6d0f6bcf	438	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
15647dc7 WD	439	/*-----------------------------------------------------------------------
	440	* FLASH organization
	441	*/
6d0f6bcf JCPV	442	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	443	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
15647dc7	444
6d0f6bcf JCPV	445	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	446	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
15647dc7 WD	447
	448	/*-----------------------------------------------------------------------
	449	* Cache Configuration
	450	*/
6d0f6bcf	451	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
ab999ba1	452	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	453	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
15647dc7 WD	454	#endif
15647dc7 WD	455
15647dc7 WD	456	/* values according to the manual */
	457
	458	#define CONFIG_DRAM_50MHZ 1
	459	#define CONFIG_SDRAM_50MHZ
	460
	461	#define CONFIG_DISK_SPINUP_TIME 1000000
	462
	463	#endif /* __CONFIG_H */