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5c4fa9b4 GB |
1 | /* |
2 | * (C) Copyright 2003-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2005-2007 | |
6 | * Modified for InterControl digsyMTC MPC5200 board by | |
7 | * Frank Bodammer, GCD Hard- & Software GmbH, | |
8 | * frank.bodammer@gcd-solutions.de | |
9 | * | |
10 | * (C) Copyright 2009 Semihalf | |
11 | * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com> | |
12 | * | |
1a459660 | 13 | * SPDX-License-Identifier: GPL-2.0+ |
5c4fa9b4 GB |
14 | */ |
15 | ||
16 | #ifndef __CONFIG_H | |
17 | #define __CONFIG_H | |
18 | ||
19 | /* | |
20 | * High Level Configuration Options | |
21 | */ | |
22 | ||
b2a6dfe4 | 23 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
5c4fa9b4 | 24 | #define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */ |
77d4357d | 25 | #define CONFIG_DISPLAY_BOARDINFO |
5c4fa9b4 | 26 | |
2ae18241 WD |
27 | /* |
28 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
29 | * 0xFFF00000 boot high (standard configuration) | |
30 | * 0xFE000000 boot low | |
31 | * 0x00100000 boot from RAM (for testing only) | |
32 | */ | |
33 | #ifndef CONFIG_SYS_TEXT_BASE | |
34 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */ | |
35 | #endif | |
36 | ||
5c4fa9b4 GB |
37 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 |
38 | ||
5c4fa9b4 GB |
39 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
40 | ||
41 | /* | |
42 | * Serial console configuration | |
43 | */ | |
44 | #define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */ | |
45 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
46 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
47 | { 9600, 19200, 38400, 57600, 115200, 230400 } | |
48 | ||
49 | /* | |
50 | * PCI Mapping: | |
51 | * 0x40000000 - 0x4fffffff - PCI Memory | |
52 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
53 | */ | |
54 | #define CONFIG_PCI 1 | |
55 | #define CONFIG_PCI_PNP 1 | |
56 | #define CONFIG_PCI_SCAN_SHOW 1 | |
4fc823dd | 57 | #define CONFIG_PCI_BOOTDELAY 250 |
5c4fa9b4 GB |
58 | |
59 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
60 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
61 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
62 | ||
63 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
64 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
65 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
66 | ||
67 | /* | |
68 | * Partitions | |
69 | */ | |
70 | #define CONFIG_DOS_PARTITION | |
71 | #define CONFIG_BZIP2 | |
72 | ||
a59996e3 AG |
73 | /* |
74 | * Video | |
75 | */ | |
76 | #define CONFIG_VIDEO | |
77 | ||
78 | #ifdef CONFIG_VIDEO | |
79 | #define CONFIG_VIDEO_MB862xx | |
80 | #define CONFIG_VIDEO_MB862xx_ACCEL | |
81 | #define CONFIG_VIDEO_CORALP | |
82 | #define CONFIG_CFB_CONSOLE | |
83 | #define CONFIG_VIDEO_LOGO | |
348de314 | 84 | #define CONFIG_VIDEO_BMP_LOGO |
a59996e3 AG |
85 | #define CONFIG_VIDEO_SW_CURSOR |
86 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
87 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
88 | #define CONFIG_SPLASH_SCREEN | |
89 | #define CONFIG_VIDEO_BMP_GZIP | |
90 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ | |
91 | ||
92 | /* Coral-PA clock frequency, geo and other both 133MHz */ | |
93 | #define CONFIG_SYS_MB862xx_CCF 0x00050000 | |
94 | /* Video SDRAM parameters */ | |
95 | #define CONFIG_SYS_MB862xx_MMR 0x11d7fa72 | |
96 | #endif | |
97 | ||
5c4fa9b4 GB |
98 | /* |
99 | * Command line configuration. | |
100 | */ | |
a59996e3 AG |
101 | #ifdef CONFIG_VIDEO |
102 | #define CONFIG_CMD_BMP | |
103 | #endif | |
5c4fa9b4 GB |
104 | #define CONFIG_CMD_CACHE |
105 | #define CONFIG_CMD_DATE | |
5c4fa9b4 GB |
106 | #define CONFIG_CMD_DIAG |
107 | #define CONFIG_CMD_EEPROM | |
5c4fa9b4 GB |
108 | #define CONFIG_CMD_EXT2 |
109 | #define CONFIG_CMD_FAT | |
5c4fa9b4 GB |
110 | #define CONFIG_CMD_IDE |
111 | #define CONFIG_CMD_IRQ | |
112 | #define CONFIG_CMD_MII | |
113 | #define CONFIG_CMD_PCI | |
5c4fa9b4 GB |
114 | #define CONFIG_CMD_REGINFO |
115 | #define CONFIG_CMD_SAVES | |
5c4fa9b4 | 116 | |
14d0a02a | 117 | #if (CONFIG_SYS_TEXT_BASE == 0xFF000000) |
5c4fa9b4 GB |
118 | #define CONFIG_SYS_LOWBOOT 1 |
119 | #endif | |
120 | ||
121 | /* | |
122 | * Autobooting | |
123 | */ | |
124 | #define CONFIG_BOOTDELAY 1 | |
125 | ||
126 | #undef CONFIG_BOOTARGS | |
127 | ||
ff27650b DZ |
128 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
129 | "fw_image=digsyMPC.img\0" \ | |
130 | "mtcb_start=mtc led diag orange; run mtcb_1\0" \ | |
131 | "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \ | |
132 | "do mtc led $x; done\0" \ | |
133 | "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \ | |
134 | "else run mtcb_fw; fi\0" \ | |
135 | "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \ | |
136 | "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \ | |
137 | "mtcb_update=mtc led user1 orange;" \ | |
138 | "while mtc key; do ; done; run mtcb_2;\0" \ | |
139 | "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \ | |
140 | "mtcb_usb1=if fatload usb 0 400000 script.img; " \ | |
141 | "then run mtcb_doscript; else run mtcb_usb2; fi\0" \ | |
142 | "mtcb_usb2=if fatload usb 0 400000 $fw_image; " \ | |
143 | "then run mtcb_dousb; else run mtcb_ide; fi\0" \ | |
144 | "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \ | |
145 | "run mtcb_wait_flickr mtcb_ds_1;\0" \ | |
146 | "mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \ | |
147 | "source 400000; else run mtcb_error; fi\0" \ | |
148 | "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \ | |
149 | "mtcb_du_1=if imi 400000; then run mtcb_du_2; " \ | |
150 | "else run mtcb_error; fi\0" \ | |
151 | "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \ | |
152 | "run mtcb_checkfw\0" \ | |
153 | "mtcb_checkfw=if imi ff000000; then run mtcb_success; " \ | |
154 | "else run mtcb_error; fi\0" \ | |
155 | "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \ | |
156 | "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \ | |
157 | "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\ | |
158 | "mtcb_uledflckr=mtc led user1 orange 11\0" \ | |
159 | "mtcb_error=mtc led user1 red\0" \ | |
160 | "mtcb_clear=erase ff000000 ff0fffff\0" \ | |
161 | "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \ | |
162 | "mtcb_success=mtc led user1 green\0" \ | |
163 | "mtcb_ide=if fatload ide 0 400000 $fw_image;" \ | |
164 | "then run mtcb_doide; else run mtcb_error; fi\0" \ | |
165 | "mtcb_doide=mtc led user2 green 1;" \ | |
166 | "run mtcb_wait_flickr mtcb_di_1;\0" \ | |
167 | "mtcb_di_1=if imi 400000; then run mtcb_di_2;" \ | |
168 | "else run mtcb_error; fi\0" \ | |
169 | "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \ | |
170 | "ramdisk_num_sector=16\0" \ | |
171 | "flash_base=ff000000\0" \ | |
172 | "flashdisk_size=e00000\0" \ | |
173 | "env_sector=fff60000\0" \ | |
174 | "flashdisk_start=ff100000\0" \ | |
175 | "load_cmd=tftp 400000 digsyMPC.img\0" \ | |
176 | "clear_cmd=erase ff000000 ff0fffff\0" \ | |
177 | "flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \ | |
178 | "update_cmd=run load_cmd; " \ | |
179 | "iminfo 400000; " \ | |
180 | "run clear_cmd flash_cmd; " \ | |
181 | "iminfo ff000000\0" \ | |
182 | "spi_driver=yes\0" \ | |
183 | "spi_watchdog=no\0" \ | |
184 | "ftps_start=yes\0" \ | |
185 | "ftps_user1=admin\0" \ | |
186 | "ftps_pass1=admin\0" \ | |
187 | "ftps_base1=/\0" \ | |
188 | "ftps_home1=/\0" \ | |
189 | "plc_sio_srv=no\0" \ | |
190 | "plc_sio_baud=57600\0" \ | |
191 | "plc_sio_parity=no\0" \ | |
192 | "plc_sio_stop=1\0" \ | |
193 | "plc_sio_com=2\0" \ | |
194 | "plc_eth_srv=yes\0" \ | |
195 | "plc_eth_port=1200\0" \ | |
196 | "plc_root=/ide/\0" \ | |
197 | "diag_level=0\0" \ | |
198 | "webvisu=no\0" \ | |
199 | "plc_can1_routing=no\0" \ | |
200 | "plc_can1_baudrate=250\0" \ | |
201 | "plc_can2_routing=no\0" \ | |
202 | "plc_can2_baudrate=250\0" \ | |
203 | "plc_can3_routing=no\0" \ | |
204 | "plc_can3_baudrate=250\0" \ | |
205 | "plc_can4_routing=no\0" \ | |
206 | "plc_can4_baudrate=250\0" \ | |
207 | "netdev=eth0\0" \ | |
208 | "console=ttyPSC0\0" \ | |
209 | "kernel_addr_r=400000\0" \ | |
210 | "fdt_addr_r=600000\0" \ | |
211 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
212 | "nfsroot=${serverip}:${rootpath}\0" \ | |
213 | "addip=setenv bootargs ${bootargs} " \ | |
214 | "ip=${ipaddr}:${serverip}:${gatewayip}:" \ | |
215 | "${netmask}:${hostname}:${netdev}:off panic=1\0" \ | |
5c4fa9b4 | 216 | "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\ |
ff27650b DZ |
217 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
218 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
219 | "tftp ${fdt_addr_r} ${fdt_file};" \ | |
220 | "run nfsargs addip addcons;" \ | |
221 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
222 | "load=tftp 200000 ${u-boot}\0" \ | |
223 | "update=protect off FFF00000 +${filesize};" \ | |
224 | "erase FFF00000 +${filesize};" \ | |
225 | "cp.b 200000 FFF00000 ${filesize};" \ | |
226 | "protect on FFF00000 +${filesize}\0" \ | |
5c4fa9b4 GB |
227 | "" |
228 | ||
ff27650b DZ |
229 | #define CONFIG_BOOTCOMMAND "run mtcb_start" |
230 | ||
f1f66edf GB |
231 | /* |
232 | * SPI configuration | |
233 | */ | |
234 | #define CONFIG_HARD_SPI 1 | |
235 | #define CONFIG_MPC52XX_SPI 1 | |
236 | ||
5c4fa9b4 GB |
237 | /* |
238 | * I2C configuration | |
239 | */ | |
240 | #define CONFIG_HARD_I2C 1 | |
241 | #define CONFIG_SYS_I2C_MODULE 1 | |
242 | #define CONFIG_SYS_I2C_SPEED 100000 | |
243 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
244 | ||
245 | /* | |
246 | * EEPROM configuration | |
247 | */ | |
248 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ | |
249 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
250 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
251 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 | |
252 | ||
253 | /* | |
254 | * RTC configuration | |
255 | */ | |
466f0137 HS |
256 | #if defined(CONFIG_DIGSY_REV5) |
257 | #define CONFIG_SYS_I2C_RTC_ADDR 0x56 | |
258 | #define CONFIG_RTC_RV3029 | |
a01ebd96 HS |
259 | /* Enable 5k Ohm trickle charge resistor */ |
260 | #define CONFIG_SYS_RV3029_TCR 0x20 | |
466f0137 | 261 | #else |
5c4fa9b4 GB |
262 | #define CONFIG_RTC_DS1337 |
263 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
c569ad6e | 264 | #define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */ |
466f0137 | 265 | #endif |
5c4fa9b4 GB |
266 | |
267 | /* | |
268 | * Flash configuration | |
269 | */ | |
270 | #define CONFIG_SYS_FLASH_CFI 1 | |
271 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
272 | ||
466f0137 HS |
273 | #if defined(CONFIG_DIGSY_REV5) |
274 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 | |
275 | #define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000 | |
276 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 | |
927d2cea HS |
277 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ |
278 | CONFIG_SYS_FLASH_BASE_CS1} | |
466f0137 HS |
279 | #define CONFIG_SYS_UPDATE_FLASH_SIZE |
280 | #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE | |
281 | #else | |
5c4fa9b4 | 282 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 |
5c4fa9b4 | 283 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
466f0137 HS |
284 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
285 | #endif | |
286 | ||
5c4fa9b4 GB |
287 | #define CONFIG_SYS_MAX_FLASH_SECT 256 |
288 | #define CONFIG_FLASH_16BIT | |
289 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
466f0137 | 290 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 |
5c4fa9b4 GB |
291 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 |
292 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
293 | ||
5c4fa9b4 GB |
294 | #define OF_CPU "PowerPC,5200@0" |
295 | #define OF_SOC "soc5200@f0000000" | |
296 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
297 | ||
298 | #define CONFIG_BOARD_EARLY_INIT_R | |
299 | #define CONFIG_MISC_INIT_R | |
300 | ||
301 | /* | |
302 | * Environment settings | |
303 | */ | |
304 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
305 | #if defined(CONFIG_LOWBOOT) | |
306 | #define CONFIG_ENV_ADDR 0xFF060000 | |
307 | #else /* CONFIG_LOWBOOT */ | |
308 | #define CONFIG_ENV_ADDR 0xFFF60000 | |
309 | #endif /* CONFIG_LOWBOOT */ | |
310 | #define CONFIG_ENV_SIZE 0x10000 | |
311 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
312 | #define CONFIG_ENV_OVERWRITE 1 | |
313 | ||
314 | /* | |
315 | * Memory map | |
316 | */ | |
317 | #define CONFIG_SYS_MBAR 0xF0000000 | |
318 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
319 | #if !defined(CONFIG_SYS_LOWBOOT) | |
320 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
321 | #else | |
322 | #define CONFIG_SYS_DEFAULT_MBAR 0xF0000000 | |
323 | #endif | |
324 | ||
325 | /* | |
326 | * Use SRAM until RAM will be available | |
327 | */ | |
328 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM | |
553f0982 | 329 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
5c4fa9b4 | 330 | |
5c4fa9b4 | 331 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
25ddd1fb | 332 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
5c4fa9b4 GB |
333 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
334 | ||
14d0a02a | 335 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
5c4fa9b4 GB |
336 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
337 | #define CONFIG_SYS_RAMBOOT 1 | |
338 | #endif | |
339 | ||
340 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
341 | #define CONFIG_SYS_MALLOC_LEN (4096 << 10) | |
342 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) | |
343 | ||
344 | /* | |
345 | * Ethernet configuration | |
346 | */ | |
347 | #define CONFIG_MPC5xxx_FEC 1 | |
348 | #define CONFIG_MPC5xxx_FEC_MII100 | |
1b41493d HS |
349 | #if defined(CONFIG_DIGSY_REV5) |
350 | #define CONFIG_PHY_ADDR 0x01 | |
351 | #else | |
5c4fa9b4 | 352 | #define CONFIG_PHY_ADDR 0x00 |
1b41493d | 353 | #endif |
5c4fa9b4 GB |
354 | #define CONFIG_PHY_RESET_DELAY 1000 |
355 | ||
356 | #define CONFIG_NETCONSOLE /* include NetConsole support */ | |
357 | ||
358 | /* | |
359 | * GPIO configuration | |
12602339 GB |
360 | * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1) |
361 | * Bit 0 (mask 0x80000000) : 0x1 | |
362 | * SPI on Tmr2/3/4/5 pins | |
363 | * Bit 2:3 (mask 0x30000000) : 0x2 | |
364 | * ATA cs0/1 on csb_4/5 | |
365 | * Bit 6:7 (mask 0x03000000) : 0x2 | |
366 | * Ethernet 100Mbit with MD | |
367 | * Bits 12:15 (mask 0x000f0000): 0x5 | |
368 | * USB - Two UARTs | |
369 | * Bits 18:19 (mask 0x00003000) : 0x2 | |
370 | * PSC3 - USB2 on PSC3 | |
371 | * Bits 20:23 (mask 0x00000f00) : 0x1 | |
372 | * PSC2 - CAN1&2 on PSC2 pins | |
373 | * Bits 25:27 (mask 0x00000070) : 0x1 | |
374 | * PSC1 - AC97 functionality | |
375 | * Bits 29:31 (mask 0x00000007) : 0x2 | |
5c4fa9b4 GB |
376 | */ |
377 | #define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112 | |
378 | ||
379 | /* | |
380 | * Miscellaneous configurable options | |
381 | */ | |
382 | #define CONFIG_SYS_LONGHELP | |
383 | #define CONFIG_AUTO_COMPLETE 1 | |
a781de12 | 384 | #define CONFIG_CMDLINE_EDITING 1 |
5c4fa9b4 | 385 | |
5c4fa9b4 GB |
386 | #define CONFIG_MX_CYCLIC 1 |
387 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
388 | ||
389 | #define CONFIG_SYS_CBSIZE 1024 | |
390 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
391 | #define CONFIG_SYS_MAXARGS 32 | |
392 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
393 | ||
394 | #define CONFIG_SYS_ALT_MEMTEST | |
395 | #define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000 | |
396 | #define CONFIG_SYS_MEMTEST_START 0x00010000 | |
397 | #define CONFIG_SYS_MEMTEST_END 0x019fffff | |
398 | ||
399 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 | |
400 | ||
5c4fa9b4 GB |
401 | /* |
402 | * Various low-level settings | |
403 | */ | |
404 | #define CONFIG_SYS_SDRAM_CS1 1 | |
405 | #define CONFIG_SYS_XLB_PIPELINING 1 | |
406 | ||
407 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI | |
408 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
409 | ||
410 | #if defined(CONFIG_SYS_LOWBOOT) | |
411 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE | |
412 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
413 | #define CONFIG_SYS_BOOTCS_CFG 0x0002DD00 | |
414 | #endif | |
415 | ||
416 | #define CONFIG_SYS_CS4_START 0x60000000 | |
417 | #define CONFIG_SYS_CS4_SIZE 0x1000 | |
418 | #define CONFIG_SYS_CS4_CFG 0x0008FC00 | |
419 | ||
420 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
421 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
422 | #define CONFIG_SYS_CS0_CFG 0x0002DD00 | |
423 | ||
466f0137 HS |
424 | #if defined(CONFIG_DIGSY_REV5) |
425 | #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1 | |
426 | #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE | |
427 | #define CONFIG_SYS_CS1_CFG 0x0002DD00 | |
428 | #endif | |
429 | ||
5c4fa9b4 GB |
430 | #define CONFIG_SYS_CS_BURST 0x00000000 |
431 | #define CONFIG_SYS_CS_DEADCYCLE 0x11111111 | |
432 | ||
433 | #if !defined(CONFIG_SYS_LOWBOOT) | |
434 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 | |
435 | #else | |
436 | #define CONFIG_SYS_RESET_ADDRESS 0xff000100 | |
437 | #endif | |
438 | ||
439 | /* | |
440 | * USB | |
441 | */ | |
442 | #define CONFIG_USB_OHCI_NEW | |
443 | #define CONFIG_SYS_OHCI_BE_CONTROLLER | |
444 | #define CONFIG_USB_STORAGE | |
445 | ||
446 | #define CONFIG_USB_CLOCK 0x00013333 | |
447 | #define CONFIG_USB_CONFIG 0x00002000 | |
448 | ||
449 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
450 | #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB | |
451 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" | |
452 | #define CONFIG_SYS_USB_OHCI_CPU_INIT | |
453 | ||
454 | /* | |
455 | * IDE/ATA | |
456 | */ | |
457 | #define CONFIG_IDE_RESET | |
458 | #define CONFIG_IDE_PREINIT | |
459 | ||
460 | #define CONFIG_SYS_ATA_CS_ON_I2C2 | |
461 | #define CONFIG_SYS_IDE_MAXBUS 1 | |
462 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
463 | ||
464 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
465 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA | |
466 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) | |
467 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) | |
468 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) | |
469 | #define CONFIG_SYS_ATA_STRIDE 4 | |
470 | ||
471 | #define CONFIG_ATAPI 1 | |
472 | #define CONFIG_LBA48 1 | |
473 | ||
474 | #endif /* __CONFIG_H */ |