[people/ms/u-boot.git] / include / configs / digsy_mtc.h

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2005-2007
 * Modified for InterControl digsyMTC MPC5200 board by
 * Frank Bodammer, GCD Hard- & Software GmbH,
 *                 frank.bodammer@gcd-solutions.de
 *
 * (C) Copyright 2009 Semihalf
 * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */

#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
#define CONFIG_DIGSY_MTC	1	/* ... on InterControl digsyMTC board */

/*
 * Valid values for CONFIG_SYS_TEXT_BASE are:
 * 0xFFF00000	boot high (standard configuration)
 * 0xFE000000	boot low
 * 0x00100000	boot from RAM (for testing only)
 */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFF00000	/* Standard: boot high */
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000

#define CONFIG_SYS_CACHELINE_SIZE	32

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	4	/* console is on PSC4  */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCI_BOOTDELAY	250

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_BZIP2

/*
 * Video
 */

#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_MB862xx
#define CONFIG_VIDEO_MB862xx_ACCEL
#define CONFIG_VIDEO_CORALP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */

/* Coral-PA clock frequency, geo and other both 133MHz */
#define CONFIG_SYS_MB862xx_CCF	0x00050000
/* Video SDRAM parameters */
#define CONFIG_SYS_MB862xx_MMR	0x11d7fa72
#endif

/*
 * Command line configuration.
 */
#ifdef CONFIG_VIDEO
#define CONFIG_CMD_BMP
#endif
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IDE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PCI
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SAVES

#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
#define CONFIG_SYS_LOWBOOT	1
#endif

/*
 * Autobooting
 */

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"fw_image=digsyMPC.img\0"					\
	"mtcb_start=mtc led diag orange; run mtcb_1\0"			\
	"mtcb_clearled=for x in user1 user2 usbpwr usbbusy; "		\
		"do mtc led $x; done\0"					\
	"mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; "	\
		"else run mtcb_fw; fi\0"				\
	"mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; "		\
		"else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0"	\
	"mtcb_update=mtc led user1 orange;"				\
		"while mtc key; do ; done; run mtcb_2;\0"		\
	"mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0"	\
	"mtcb_usb1=if fatload usb 0 400000 script.img; "		\
		"then run mtcb_doscript; else run mtcb_usb2; fi\0"	\
	"mtcb_usb2=if fatload usb 0 400000 $fw_image; "			\
		"then run mtcb_dousb; else run mtcb_ide; fi\0"		\
	"mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; "	\
		"run mtcb_wait_flickr mtcb_ds_1;\0"			\
	"mtcb_ds_1=if imi 400000; then mtc led usbbusy; "		\
		"source 400000; else run mtcb_error; fi\0"		\
	"mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0"	\
	"mtcb_du_1=if imi 400000; then run mtcb_du_2; "			\
		"else run mtcb_error; fi\0"				\
	"mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; "		\
		"run mtcb_checkfw\0"					\
	"mtcb_checkfw=if imi ff000000; then run mtcb_success; "		\
		"else run mtcb_error; fi\0"				\
	"mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0"	\
	"mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0"		\
	"mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
	"mtcb_uledflckr=mtc led user1 orange 11\0"			\
	"mtcb_error=mtc led user1 red\0"				\
	"mtcb_clear=erase ff000000 ff0fffff\0"				\
	"mtcb_prog=cp.b 400000 ff000000 ${filesize}\0"			\
	"mtcb_success=mtc led user1 green\0"				\
	"mtcb_ide=if fatload ide 0 400000 $fw_image;"			\
		"then run mtcb_doide; else run mtcb_error; fi\0"	\
	"mtcb_doide=mtc led user2 green 1;"				\
		"run mtcb_wait_flickr mtcb_di_1;\0"			\
	"mtcb_di_1=if imi 400000; then run mtcb_di_2;"			\
		"else run mtcb_error; fi\0"				\
	"mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0"	\
	"ramdisk_num_sector=16\0"					\
	"flash_base=ff000000\0"						\
	"flashdisk_size=e00000\0"					\
	"env_sector=fff60000\0"						\
	"flashdisk_start=ff100000\0"					\
	"load_cmd=tftp 400000 digsyMPC.img\0"				\
	"clear_cmd=erase ff000000 ff0fffff\0"				\
	"flash_cmd=cp.b 400000 ff000000 ${filesize}\0"			\
	"update_cmd=run load_cmd; "					\
	"iminfo 400000; "						\
	"run clear_cmd flash_cmd; "					\
	"iminfo ff000000\0"						\
	"spi_driver=yes\0"						\
	"spi_watchdog=no\0"						\
	"ftps_start=yes\0"						\
	"ftps_user1=admin\0"						\
	"ftps_pass1=admin\0"						\
	"ftps_base1=/\0"						\
	"ftps_home1=/\0"						\
	"plc_sio_srv=no\0"						\
	"plc_sio_baud=57600\0"						\
	"plc_sio_parity=no\0"						\
	"plc_sio_stop=1\0"						\
	"plc_sio_com=2\0"						\
	"plc_eth_srv=yes\0"						\
	"plc_eth_port=1200\0"						\
	"plc_root=/ide/\0"						\
	"diag_level=0\0"						\
	"webvisu=no\0"							\
	"plc_can1_routing=no\0"						\
	"plc_can1_baudrate=250\0"					\
	"plc_can2_routing=no\0"						\
	"plc_can2_baudrate=250\0"					\
	"plc_can3_routing=no\0"						\
	"plc_can3_baudrate=250\0"					\
	"plc_can4_routing=no\0"						\
	"plc_can4_baudrate=250\0"					\
	"netdev=eth0\0"							\
	"console=ttyPSC0\0"						\
	"kernel_addr_r=400000\0"					\
	"fdt_addr_r=600000\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
	"nfsroot=${serverip}:${rootpath}\0"				\
	"addip=setenv bootargs ${bootargs} "				\
	"ip=${ipaddr}:${serverip}:${gatewayip}:"			\
	"${netmask}:${hostname}:${netdev}:off panic=1\0"		\
	"addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
		"tftp ${fdt_addr_r} ${fdt_file};"			\
		"run nfsargs addip addcons;"				\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"load=tftp 200000 ${u-boot}\0"					\
	"update=protect off FFF00000 +${filesize};"			\
		"erase FFF00000 +${filesize};"				\
		"cp.b 200000 FFF00000 ${filesize};"			\
		"protect on FFF00000 +${filesize}\0"			\
	""

#define CONFIG_BOOTCOMMAND	"run mtcb_start"

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1
#define CONFIG_SYS_I2C_MODULE	1
#define CONFIG_SYS_I2C_SPEED	100000
#define CONFIG_SYS_I2C_SLAVE	0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 	1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * RTC configuration
 */
#if defined(CONFIG_DIGSY_REV5)
#define CONFIG_SYS_I2C_RTC_ADDR	0x56
#define CONFIG_RTC_RV3029
/* Enable 5k Ohm trickle charge resistor */
#define CONFIG_SYS_RV3029_TCR	0x20
#else
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR	0x68
#define CONFIG_SYS_DS1339_TCR_VAL	0xAB	/* diode + 4k resistor */
#endif

/*
 * Flash configuration
 */
#define	CONFIG_SYS_FLASH_CFI		1
#define	CONFIG_FLASH_CFI_DRIVER	1

#if defined(CONFIG_DIGSY_REV5)
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_BASE_CS1	0xFC000000
#define CONFIG_SYS_MAX_FLASH_BANKS	2
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, \
					CONFIG_SYS_FLASH_BASE_CS1}
#define CONFIG_SYS_UPDATE_FLASH_SIZE
#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
#else
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#endif

#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_FLASH_16BIT
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_SIZE	0x01000000
#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500

#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)

#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#if defined(CONFIG_LOWBOOT)
#define CONFIG_ENV_ADDR		0xFF060000
#else	/* CONFIG_LOWBOOT */
#define CONFIG_ENV_ADDR		0xFFF60000
#endif	/* CONFIG_LOWBOOT */
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
#else
#define CONFIG_SYS_DEFAULT_MBAR	0xF0000000
#endif

/*
 *  Use SRAM until RAM will be available
 */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE

#define CONFIG_SYS_GBL_DATA_OFFSET	\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
#define CONFIG_SYS_MALLOC_LEN	(4096 << 10)
#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
#if defined(CONFIG_DIGSY_REV5)
#define CONFIG_PHY_ADDR		0x01
#else
#define CONFIG_PHY_ADDR		0x00
#endif
#define CONFIG_PHY_RESET_DELAY	1000

#define CONFIG_NETCONSOLE		/* include NetConsole support	*/

/*
 * GPIO configuration
 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
 *  Bit 0   (mask 0x80000000) : 0x1
 * SPI on Tmr2/3/4/5 pins
 *  Bit 2:3 (mask 0x30000000) : 0x2
 * ATA cs0/1 on csb_4/5
 *  Bit 6:7 (mask 0x03000000) : 0x2
 * Ethernet 100Mbit with MD
 *  Bits 12:15 (mask 0x000f0000): 0x5
 * USB - Two UARTs
 *  Bits 18:19 (mask 0x00003000) : 0x2
 * PSC3 - USB2 on PSC3
 *  Bits 20:23 (mask 0x00000f00) : 0x1
 * PSC2 - CAN1&2 on PSC2 pins
 *  Bits 25:27 (mask 0x00000070) : 0x1
 * PSC1 - AC97 functionality
 *  Bits 29:31 (mask 0x00000007) : 0x2
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0xA2552112

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE	1
#define CONFIG_CMDLINE_EDITING	1

#define CONFIG_MX_CYCLIC	1

#define CONFIG_SYS_CBSIZE		1024
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS		32
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_SCRATCH	0x00001000
#define CONFIG_SYS_MEMTEST_START	0x00010000
#define CONFIG_SYS_MEMTEST_END		0x019fffff

#define CONFIG_SYS_LOAD_ADDR		0x00100000

/*
 * Various low-level settings
 */
#define CONFIG_SYS_SDRAM_CS1		1
#define CONFIG_SYS_XLB_PIPELINING	1

#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#if defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x0002DD00
#endif

#define CONFIG_SYS_CS4_START		0x60000000
#define CONFIG_SYS_CS4_SIZE		0x1000
#define CONFIG_SYS_CS4_CFG		0x0008FC00

#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS0_CFG		0x0002DD00

#if defined(CONFIG_DIGSY_REV5)
#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE_CS1
#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_CFG		0x0002DD00
#endif

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x11111111

#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
#else
#define CONFIG_SYS_RESET_ADDRESS	0xff000100
#endif

/*
 * USB
 */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_OHCI_BE_CONTROLLER

#define CONFIG_USB_CLOCK	0x00013333
#define CONFIG_USB_CONFIG	0x00002000

#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
#define CONFIG_SYS_USB_OHCI_CPU_INIT

/*
 * IDE/ATA
 */
#define CONFIG_IDE_RESET
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_ATA_CS_ON_I2C2
#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	1

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
#define CONFIG_SYS_ATA_STRIDE		4

#define CONFIG_ATAPI		1
#define CONFIG_LBA48		1

#endif /* __CONFIG_H */
Commit	Line	Data
5c4fa9b4 GB	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2005-2007
	6	* Modified for InterControl digsyMTC MPC5200 board by
	7	* Frank Bodammer, GCD Hard- & Software GmbH,
	8	* frank.bodammer@gcd-solutions.de
	9	*
	10	* (C) Copyright 2009 Semihalf
	11	* Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
	12	*
1a459660	13	* SPDX-License-Identifier: GPL-2.0+
5c4fa9b4 GB	14	*/
	15
	16	#ifndef __CONFIG_H
	17	#define __CONFIG_H
	18
	19	/*
	20	* High Level Configuration Options
	21	*/
	22
b2a6dfe4	23	#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
5c4fa9b4 GB	24	#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
5c4fa9b4 GB	25
2ae18241 WD	26	/*
	27	* Valid values for CONFIG_SYS_TEXT_BASE are:
	28	* 0xFFF00000 boot high (standard configuration)
	29	* 0xFE000000 boot low
	30	* 0x00100000 boot from RAM (for testing only)
	31	*/
	32	#ifndef CONFIG_SYS_TEXT_BASE
	33	#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
	34	#endif
	35
5c4fa9b4 GB	36	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
5c4fa9b4 GB	37
5c4fa9b4 GB	38	#define CONFIG_SYS_CACHELINE_SIZE 32
	39
	40	/*
	41	* Serial console configuration
	42	*/
	43	#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
5c4fa9b4 GB	44	#define CONFIG_SYS_BAUDRATE_TABLE \
	45	{ 9600, 19200, 38400, 57600, 115200, 230400 }
	46
	47	/*
	48	* PCI Mapping:
	49	* 0x40000000 - 0x4fffffff - PCI Memory
	50	* 0x50000000 - 0x50ffffff - PCI IO Space
	51	*/
5c4fa9b4	52	#define CONFIG_PCI_SCAN_SHOW 1
4fc823dd	53	#define CONFIG_PCI_BOOTDELAY 250
5c4fa9b4 GB	54
	55	#define CONFIG_PCI_MEM_BUS 0x40000000
	56	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	57	#define CONFIG_PCI_MEM_SIZE 0x10000000
	58
	59	#define CONFIG_PCI_IO_BUS 0x50000000
	60	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	61	#define CONFIG_PCI_IO_SIZE 0x01000000
	62
5c4fa9b4 GB	63	#define CONFIG_BZIP2
5c4fa9b4 GB	64
a59996e3 AG	65	/*
	66	* Video
	67	*/
a59996e3 AG	68
	69	#ifdef CONFIG_VIDEO
	70	#define CONFIG_VIDEO_MB862xx
	71	#define CONFIG_VIDEO_MB862xx_ACCEL
	72	#define CONFIG_VIDEO_CORALP
a59996e3	73	#define CONFIG_VIDEO_LOGO
348de314	74	#define CONFIG_VIDEO_BMP_LOGO
a59996e3 AG	75	#define CONFIG_SPLASH_SCREEN
	76	#define CONFIG_VIDEO_BMP_GZIP
	77	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
	78
	79	/* Coral-PA clock frequency, geo and other both 133MHz */
	80	#define CONFIG_SYS_MB862xx_CCF 0x00050000
	81	/* Video SDRAM parameters */
	82	#define CONFIG_SYS_MB862xx_MMR 0x11d7fa72
	83	#endif
	84
5c4fa9b4 GB	85	/*
	86	* Command line configuration.
	87	*/
a59996e3 AG	88	#ifdef CONFIG_VIDEO
	89	#define CONFIG_CMD_BMP
	90	#endif
5c4fa9b4	91	#define CONFIG_CMD_DATE
5c4fa9b4 GB	92	#define CONFIG_CMD_DIAG
5c4fa9b4 GB	93	#define CONFIG_CMD_EEPROM
5c4fa9b4 GB	94	#define CONFIG_CMD_IDE
5c4fa9b4 GB	95	#define CONFIG_CMD_IRQ
5c4fa9b4	96	#define CONFIG_CMD_PCI
5c4fa9b4 GB	97	#define CONFIG_CMD_REGINFO
5c4fa9b4 GB	98	#define CONFIG_CMD_SAVES
5c4fa9b4	99
14d0a02a	100	#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
5c4fa9b4 GB	101	#define CONFIG_SYS_LOWBOOT 1
	102	#endif
	103
	104	/*
	105	* Autobooting
	106	*/
5c4fa9b4 GB	107
	108	#undef CONFIG_BOOTARGS
	109
ff27650b DZ	110	#define CONFIG_EXTRA_ENV_SETTINGS \
	111	"fw_image=digsyMPC.img\0" \
	112	"mtcb_start=mtc led diag orange; run mtcb_1\0" \
	113	"mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \
	114	"do mtc led $x; done\0" \
	115	"mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \
	116	"else run mtcb_fw; fi\0" \
	117	"mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \
	118	"else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \
	119	"mtcb_update=mtc led user1 orange;" \
	120	"while mtc key; do ; done; run mtcb_2;\0" \
	121	"mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \
	122	"mtcb_usb1=if fatload usb 0 400000 script.img; " \
	123	"then run mtcb_doscript; else run mtcb_usb2; fi\0" \
	124	"mtcb_usb2=if fatload usb 0 400000 $fw_image; " \
	125	"then run mtcb_dousb; else run mtcb_ide; fi\0" \
	126	"mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \
	127	"run mtcb_wait_flickr mtcb_ds_1;\0" \
	128	"mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \
	129	"source 400000; else run mtcb_error; fi\0" \
	130	"mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \
	131	"mtcb_du_1=if imi 400000; then run mtcb_du_2; " \
	132	"else run mtcb_error; fi\0" \
	133	"mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \
	134	"run mtcb_checkfw\0" \
	135	"mtcb_checkfw=if imi ff000000; then run mtcb_success; " \
	136	"else run mtcb_error; fi\0" \
	137	"mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
	138	"mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \
	139	"mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
	140	"mtcb_uledflckr=mtc led user1 orange 11\0" \
	141	"mtcb_error=mtc led user1 red\0" \
	142	"mtcb_clear=erase ff000000 ff0fffff\0" \
	143	"mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \
	144	"mtcb_success=mtc led user1 green\0" \
	145	"mtcb_ide=if fatload ide 0 400000 $fw_image;" \
	146	"then run mtcb_doide; else run mtcb_error; fi\0" \
	147	"mtcb_doide=mtc led user2 green 1;" \
	148	"run mtcb_wait_flickr mtcb_di_1;\0" \
	149	"mtcb_di_1=if imi 400000; then run mtcb_di_2;" \
	150	"else run mtcb_error; fi\0" \
	151	"mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \
	152	"ramdisk_num_sector=16\0" \
	153	"flash_base=ff000000\0" \
	154	"flashdisk_size=e00000\0" \
	155	"env_sector=fff60000\0" \
	156	"flashdisk_start=ff100000\0" \
	157	"load_cmd=tftp 400000 digsyMPC.img\0" \
	158	"clear_cmd=erase ff000000 ff0fffff\0" \
	159	"flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \
	160	"update_cmd=run load_cmd; " \
	161	"iminfo 400000; " \
	162	"run clear_cmd flash_cmd; " \
	163	"iminfo ff000000\0" \
	164	"spi_driver=yes\0" \
	165	"spi_watchdog=no\0" \
	166	"ftps_start=yes\0" \
	167	"ftps_user1=admin\0" \
	168	"ftps_pass1=admin\0" \
	169	"ftps_base1=/\0" \
	170	"ftps_home1=/\0" \
	171	"plc_sio_srv=no\0" \
	172	"plc_sio_baud=57600\0" \
	173	"plc_sio_parity=no\0" \
174	"plc_sio_stop=1\0" \
175	"plc_sio_com=2\0" \
176	"plc_eth_srv=yes\0" \
177	"plc_eth_port=1200\0" \
178	"plc_root=/ide/\0" \
179	"diag_level=0\0" \
180	"webvisu=no\0" \
181	"plc_can1_routing=no\0" \
182	"plc_can1_baudrate=250\0" \
183	"plc_can2_routing=no\0" \
184	"plc_can2_baudrate=250\0" \
185	"plc_can3_routing=no\0" \
186	"plc_can3_baudrate=250\0" \
187	"plc_can4_routing=no\0" \
188	"plc_can4_baudrate=250\0" \
189	"netdev=eth0\0" \
190	"console=ttyPSC0\0" \
191	"kernel_addr_r=400000\0" \
192	"fdt_addr_r=600000\0" \
193	"nfsargs=setenv bootargs root=/dev/nfs rw " \
194	"nfsroot=${serverip}:${rootpath}\0" \
195	"addip=setenv bootargs ${bootargs} " \
196	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
197	"${netmask}:${hostname}:${netdev}:off panic=1\0" \
5c4fa9b4	198	"addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
ff27650b DZ	199	"rootpath=/opt/eldk/ppc_6xx\0" \
	200	"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
	201	"tftp ${fdt_addr_r} ${fdt_file};" \
	202	"run nfsargs addip addcons;" \
	203	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
	204	"load=tftp 200000 ${u-boot}\0" \
	205	"update=protect off FFF00000 +${filesize};" \
	206	"erase FFF00000 +${filesize};" \
	207	"cp.b 200000 FFF00000 ${filesize};" \
	208	"protect on FFF00000 +${filesize}\0" \
5c4fa9b4 GB	209	""
5c4fa9b4 GB	210
ff27650b DZ	211	#define CONFIG_BOOTCOMMAND "run mtcb_start"
ff27650b DZ	212
5c4fa9b4 GB	213	/*
	214	* I2C configuration
	215	*/
	216	#define CONFIG_HARD_I2C 1
	217	#define CONFIG_SYS_I2C_MODULE 1
	218	#define CONFIG_SYS_I2C_SPEED 100000
	219	#define CONFIG_SYS_I2C_SLAVE 0x7F
	220
	221	/*
	222	* EEPROM configuration
	223	*/
	224	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	225	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	226	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	227	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
	228
	229	/*
	230	* RTC configuration
	231	*/
466f0137 HS	232	#if defined(CONFIG_DIGSY_REV5)
	233	#define CONFIG_SYS_I2C_RTC_ADDR 0x56
	234	#define CONFIG_RTC_RV3029
a01ebd96 HS	235	/* Enable 5k Ohm trickle charge resistor */
a01ebd96 HS	236	#define CONFIG_SYS_RV3029_TCR 0x20
466f0137	237	#else
5c4fa9b4 GB	238	#define CONFIG_RTC_DS1337
5c4fa9b4 GB	239	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
c569ad6e	240	#define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
466f0137	241	#endif
5c4fa9b4 GB	242
	243	/*
	244	* Flash configuration
	245	*/
	246	#define CONFIG_SYS_FLASH_CFI 1
	247	#define CONFIG_FLASH_CFI_DRIVER 1
	248
466f0137 HS	249	#if defined(CONFIG_DIGSY_REV5)
	250	#define CONFIG_SYS_FLASH_BASE 0xFE000000
	251	#define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000
	252	#define CONFIG_SYS_MAX_FLASH_BANKS 2
927d2cea HS	253	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
927d2cea HS	254	CONFIG_SYS_FLASH_BASE_CS1}
466f0137 HS	255	#define CONFIG_SYS_UPDATE_FLASH_SIZE
	256	#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
	257	#else
5c4fa9b4	258	#define CONFIG_SYS_FLASH_BASE 0xFF000000
5c4fa9b4	259	#define CONFIG_SYS_MAX_FLASH_BANKS 1
466f0137 HS	260	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	261	#endif
	262
5c4fa9b4 GB	263	#define CONFIG_SYS_MAX_FLASH_SECT 256
	264	#define CONFIG_FLASH_16BIT
	265	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
466f0137	266	#define CONFIG_SYS_FLASH_SIZE 0x01000000
5c4fa9b4 GB	267	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
	268	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
	269
5c4fa9b4 GB	270	#define OF_CPU "PowerPC,5200@0"
	271	#define OF_SOC "soc5200@f0000000"
	272	#define OF_TBCLK (bd->bi_busfreq / 4)
	273
	274	#define CONFIG_BOARD_EARLY_INIT_R
	275	#define CONFIG_MISC_INIT_R
	276
	277	/*
	278	* Environment settings
	279	*/
	280	#define CONFIG_ENV_IS_IN_FLASH 1
	281	#if defined(CONFIG_LOWBOOT)
	282	#define CONFIG_ENV_ADDR 0xFF060000
	283	#else /* CONFIG_LOWBOOT */
	284	#define CONFIG_ENV_ADDR 0xFFF60000
	285	#endif /* CONFIG_LOWBOOT */
	286	#define CONFIG_ENV_SIZE 0x10000
	287	#define CONFIG_ENV_SECT_SIZE 0x20000
	288	#define CONFIG_ENV_OVERWRITE 1
	289
	290	/*
	291	* Memory map
	292	*/
	293	#define CONFIG_SYS_MBAR 0xF0000000
	294	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	295	#if !defined(CONFIG_SYS_LOWBOOT)
	296	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
	297	#else
	298	#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
	299	#endif
	300
	301	/*
	302	* Use SRAM until RAM will be available
	303	*/
	304	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	305	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
5c4fa9b4	306
5c4fa9b4	307	#define CONFIG_SYS_GBL_DATA_OFFSET \
25ddd1fb	308	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
5c4fa9b4 GB	309	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5c4fa9b4 GB	310
14d0a02a	311	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
5c4fa9b4 GB	312	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	313	#define CONFIG_SYS_RAMBOOT 1
	314	#endif
	315
	316	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
	317	#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
	318	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
	319
	320	/*
	321	* Ethernet configuration
	322	*/
	323	#define CONFIG_MPC5xxx_FEC 1
	324	#define CONFIG_MPC5xxx_FEC_MII100
1b41493d HS	325	#if defined(CONFIG_DIGSY_REV5)
	326	#define CONFIG_PHY_ADDR 0x01
	327	#else
5c4fa9b4	328	#define CONFIG_PHY_ADDR 0x00
1b41493d	329	#endif
5c4fa9b4 GB	330	#define CONFIG_PHY_RESET_DELAY 1000
	331
	332	#define CONFIG_NETCONSOLE /* include NetConsole support */
	333
	334	/*
	335	* GPIO configuration
12602339 GB	336	* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
	337	* Bit 0 (mask 0x80000000) : 0x1
	338	* SPI on Tmr2/3/4/5 pins
	339	* Bit 2:3 (mask 0x30000000) : 0x2
	340	* ATA cs0/1 on csb_4/5
	341	* Bit 6:7 (mask 0x03000000) : 0x2
	342	* Ethernet 100Mbit with MD
	343	* Bits 12:15 (mask 0x000f0000): 0x5
	344	* USB - Two UARTs
	345	* Bits 18:19 (mask 0x00003000) : 0x2
	346	* PSC3 - USB2 on PSC3
	347	* Bits 20:23 (mask 0x00000f00) : 0x1
	348	* PSC2 - CAN1&2 on PSC2 pins
	349	* Bits 25:27 (mask 0x00000070) : 0x1
	350	* PSC1 - AC97 functionality
	351	* Bits 29:31 (mask 0x00000007) : 0x2
5c4fa9b4 GB	352	*/
	353	#define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
	354
	355	/*
	356	* Miscellaneous configurable options
	357	*/
	358	#define CONFIG_SYS_LONGHELP
	359	#define CONFIG_AUTO_COMPLETE 1
a781de12	360	#define CONFIG_CMDLINE_EDITING 1
5c4fa9b4	361
5c4fa9b4	362	#define CONFIG_MX_CYCLIC 1
5c4fa9b4 GB	363
	364	#define CONFIG_SYS_CBSIZE 1024
	365	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	366	#define CONFIG_SYS_MAXARGS 32
	367	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	368
	369	#define CONFIG_SYS_ALT_MEMTEST
	370	#define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000
	371	#define CONFIG_SYS_MEMTEST_START 0x00010000
	372	#define CONFIG_SYS_MEMTEST_END 0x019fffff
	373
	374	#define CONFIG_SYS_LOAD_ADDR 0x00100000
	375
5c4fa9b4 GB	376	/*
	377	* Various low-level settings
	378	*/
	379	#define CONFIG_SYS_SDRAM_CS1 1
	380	#define CONFIG_SYS_XLB_PIPELINING 1
	381
	382	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
	383	#define CONFIG_SYS_HID0_FINAL HID0_ICE
	384
	385	#if defined(CONFIG_SYS_LOWBOOT)
	386	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	387	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	388	#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
	389	#endif
	390
	391	#define CONFIG_SYS_CS4_START 0x60000000
	392	#define CONFIG_SYS_CS4_SIZE 0x1000
	393	#define CONFIG_SYS_CS4_CFG 0x0008FC00
	394
	395	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	396	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
	397	#define CONFIG_SYS_CS0_CFG 0x0002DD00
	398
466f0137 HS	399	#if defined(CONFIG_DIGSY_REV5)
	400	#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1
	401	#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
	402	#define CONFIG_SYS_CS1_CFG 0x0002DD00
	403	#endif
	404
5c4fa9b4 GB	405	#define CONFIG_SYS_CS_BURST 0x00000000
	406	#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
	407
	408	#if !defined(CONFIG_SYS_LOWBOOT)
	409	#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
	410	#else
	411	#define CONFIG_SYS_RESET_ADDRESS 0xff000100
	412	#endif
	413
	414	/*
	415	* USB
	416	*/
	417	#define CONFIG_USB_OHCI_NEW
	418	#define CONFIG_SYS_OHCI_BE_CONTROLLER
5c4fa9b4 GB	419
	420	#define CONFIG_USB_CLOCK 0x00013333
	421	#define CONFIG_USB_CONFIG 0x00002000
	422
	423	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
	424	#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
	425	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
	426	#define CONFIG_SYS_USB_OHCI_CPU_INIT
	427
	428	/*
	429	* IDE/ATA
	430	*/
	431	#define CONFIG_IDE_RESET
	432	#define CONFIG_IDE_PREINIT
	433
	434	#define CONFIG_SYS_ATA_CS_ON_I2C2
	435	#define CONFIG_SYS_IDE_MAXBUS 1
	436	#define CONFIG_SYS_IDE_MAXDEVICE 1
	437
	438	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	439	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
	440	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
	441	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
	442	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
	443	#define CONFIG_SYS_ATA_STRIDE 4
	444
	445	#define CONFIG_ATAPI 1
	446	#define CONFIG_LBA48 1
	447
	448	#endif /* __CONFIG_H */