[people/ms/u-boot.git] / include / configs / ep8248.h

/*
 * Copyright (C) 2004 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 *
 * U-Boot configuration for Embedded Planet EP8248 boards.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_MPC8248
#define CPU_ID_STR		"MPC8248"

#define CONFIG_EP8248			/* Embedded Planet EP8248 board */

#undef DEBUG

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/

/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_ENV_OVERWRITE

/*
 * Select serial console configuration
 *
 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 */
#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
#undef	CONFIG_CONS_NONE		/* It's not on external UART */
#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */

#define CFG_BCSR		0xFA000000

/*
 * Select ethernet configuration
 *
 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
 * SCC, 1-3 for FCC)
 *
 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
 * must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */

#ifdef CONFIG_ETHER_ON_FCC

#define CONFIG_ETHER_INDEX	1	/* FCC1 is used for Ethernet */

#if   (CONFIG_ETHER_INDEX == 1)

/* - Rx clock is CLK10
 * - Tx clock is CLK11
 * - BDs/buffers on 60x bus
 * - Full duplex
 */
#define CFG_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
#define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
#define CFG_CPMFCR_RAMTYPE	0
#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#elif (CONFIG_ETHER_INDEX == 2)

/* - Rx clock is CLK13
 * - Tx clock is CLK14
 * - BDs/buffers on 60x bus
 * - Full duplex
 */
#define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
#define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
#define CFG_CPMFCR_RAMTYPE	0
#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#endif /* CONFIG_ETHER_INDEX */

#define CONFIG_MII			/* MII PHY management        */
#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT		0	/* Not used - implemented in BCSR */
#define MDIO_ACTIVE		(*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
#define MDIO_TRISTATE		(*(vu_char *)(CFG_BCSR + 8) |= 0x04)
#define MDIO_READ		(*(vu_char *)(CFG_BCSR + 8) & 1)

#define MDIO(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFE

#define MDC(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFD

#define MIIDELAY		udelay(1)

#endif /* CONFIG_ETHER_ON_FCC */

#ifndef CONFIG_8260_CLKIN
#define CONFIG_8260_CLKIN	66000000	/* in Hz */
#endif

#define CONFIG_BAUDRATE		38400


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING


#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND	"bootm FF860000"	/* autoboot command */
#define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"

#if defined(CONFIG_CMD_KGDB)
#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	1	/* which serial channel for kgdb */
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
#endif

#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */

/*
 * Miscellaneous configurable options
 */
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
#define CFG_MAXARGS		16		/* max number of command args */
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CFG_FLASH_BASE		0xFF800000
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */

#define	CFG_DIRECT_FLASH_TFTP

#if defined(CONFIG_CMD_JFFS2)
#define CFG_JFFS2_FIRST_BANK	0
#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
#define CFG_JFFS2_FIRST_SECTOR  0
#define CFG_JFFS2_LAST_SECTOR   62
#define CFG_JFFS2_SORT_FRAGMENTS
#define CFG_JFFS_CUSTOM_PART
#endif

#if defined(CONFIG_CMD_I2C)
#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
#define CFG_I2C_SPEED		100000	/* I2C speed			*/
#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
#endif

#define CFG_MONITOR_BASE	TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#endif

#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256KB for Monitor */

#define CFG_ENV_IS_IN_FLASH

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE	0x20000
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#endif /* CFG_ENV_IS_IN_FLASH */

#define CFG_DEFAULT_IMMR	0x00010000

#define CFG_IMMR		0xF0000000

#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/* Hard reset configuration word */
#define CFG_HRCW_MASTER		0x0C40025A /* Not used - provided by FPGA */
/* No slaves */
#define CFG_HRCW_SLAVE1 	0
#define CFG_HRCW_SLAVE2 	0
#define CFG_HRCW_SLAVE3 	0
#define CFG_HRCW_SLAVE4 	0
#define CFG_HRCW_SLAVE5 	0
#define CFG_HRCW_SLAVE6 	0
#define CFG_HRCW_SLAVE7 	0

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot                  */

#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)

#define CFG_HID2		0

#define CFG_SIUMCR		0x01240200
#define CFG_SYPCR		0xFFFF0683
#define CFG_BCR			0x00000000
#define CFG_SCCR		SCCR_DFBRG01

#define CFG_RMR			RMR_CSRE
#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
#define CFG_RCCR		0

#define CFG_MPTPR		0x1300
#define CFG_PSDMR		0x82672522
#define CFG_PSRT		0x4B

#define CFG_SDRAM_BASE		0x00000000
#define CFG_SDRAM_BR		(CFG_SDRAM_BASE | 0x00001841)
#define CFG_SDRAM_OR		0xFF0030C0

#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00001801)
#define CFG_OR0_PRELIM		0xFF8008C2
#define CFG_BR2_PRELIM		(CFG_BCSR | 0x00000801)
#define CFG_OR2_PRELIM		0xFFF00864

#define CFG_RESET_ADDRESS	0xC0000000

#endif /* __CONFIG_H */
Commit	Line	Data
f901a83b WD	1	/*
	2	* Copyright (C) 2004 Arabella Software Ltd.
	3	* Yuli Barcohen <yuli@arabellasw.com>
	4	*
	5	* U-Boot configuration for Embedded Planet EP8248 boards.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	#define CONFIG_MPC8248
	30	#define CPU_ID_STR "MPC8248"
	31
	32	#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
	33
	34	#undef DEBUG
	35
	36	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	37
	38	/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
	39	#define CONFIG_ENV_OVERWRITE
	40
	41	/*
	42	* Select serial console configuration
	43	*
	44	* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	45	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	46	* for SCC).
	47	*/
	48	#define CONFIG_CONS_ON_SMC /* Console is on SMC */
	49	#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
	50	#undef CONFIG_CONS_NONE /* It's not on external UART */
	51	#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
	52
	53	#define CFG_BCSR 0xFA000000
	54
	55	/*
	56	* Select ethernet configuration
	57	*
	58	* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
	59	* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
	60	* SCC, 1-3 for FCC)
	61	*
	62	* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
639221c7 JL	63	* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
639221c7 JL	64	* must be unset.
f901a83b WD	65	*/
	66	#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
	67	#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
	68	#undef CONFIG_ETHER_NONE /* No external Ethernet */
	69
	70	#ifdef CONFIG_ETHER_ON_FCC
	71
	72	#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
	73
	74	#if (CONFIG_ETHER_INDEX == 1)
	75
	76	/* - Rx clock is CLK10
	77	* - Tx clock is CLK11
	78	* - BDs/buffers on 60x bus
	79	* - Full duplex
	80	*/
	81	#define CFG_CMXFCR_MASK (CMXFCR_FC1 \| CMXFCR_RF1CS_MSK \| CMXFCR_TF1CS_MSK)
	82	#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 \| CMXFCR_TF1CS_CLK11)
	83	#define CFG_CPMFCR_RAMTYPE 0
	84	#define CFG_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB)
	85
	86	#elif (CONFIG_ETHER_INDEX == 2)
	87
	88	/* - Rx clock is CLK13
	89	* - Tx clock is CLK14
	90	* - BDs/buffers on 60x bus
	91	* - Full duplex
	92	*/
	93	#define CFG_CMXFCR_MASK (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
	94	#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
	95	#define CFG_CPMFCR_RAMTYPE 0
	96	#define CFG_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB)
	97
	98	#endif /* CONFIG_ETHER_INDEX */
	99
	100	#define CONFIG_MII /* MII PHY management */
	101	#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
	102	/*
	103	* GPIO pins used for bit-banged MII communications
	104	*/
	105	#define MDIO_PORT 0 /* Not used - implemented in BCSR */
	106	#define MDIO_ACTIVE ((vu_char )(CFG_BCSR + 8) &= 0xFB)
	107	#define MDIO_TRISTATE ((vu_char )(CFG_BCSR + 8) \|= 0x04)
	108	#define MDIO_READ ((vu_char )(CFG_BCSR + 8) & 1)
	109
	110	#define MDIO(bit) if(bit) (vu_char )(CFG_BCSR + 8) \|= 0x01; \
	111	else (vu_char )(CFG_BCSR + 8) &= 0xFE
	112
	113	#define MDC(bit) if(bit) (vu_char )(CFG_BCSR + 8) \|= 0x02; \
	114	else (vu_char )(CFG_BCSR + 8) &= 0xFD
	115
	116	#define MIIDELAY udelay(1)
	117
	118	#endif /* CONFIG_ETHER_ON_FCC */
	119
	120	#ifndef CONFIG_8260_CLKIN
	121	#define CONFIG_8260_CLKIN 66000000 /* in Hz */
	122	#endif
	123
	124	#define CONFIG_BAUDRATE 38400
	125
1bec3d30	126
80ff4f99 JL	127	/*
	128	* BOOTP options
	129	*/
	130	#define CONFIG_BOOTP_BOOTFILESIZE
	131	#define CONFIG_BOOTP_BOOTPATH
	132	#define CONFIG_BOOTP_GATEWAY
	133	#define CONFIG_BOOTP_HOSTNAME
	134
	135
1bec3d30 JL	136	/*
	137	* Command line configuration.
	138	*/
	139	#include <config_cmd_default.h>
	140
	141	#define CONFIG_CMD_DHCP
	142	#define CONFIG_CMD_ECHO
	143	#define CONFIG_CMD_I2C
	144	#define CONFIG_CMD_IMMAP
	145	#define CONFIG_CMD_MII
	146	#define CONFIG_CMD_PING
	147
f901a83b WD	148
	149	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	150	#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
	151	#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
	152
1bec3d30	153	#if defined(CONFIG_CMD_KGDB)
f901a83b WD	154	#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
	155	#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
	156	#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
	157	#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
	158	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
	159	#endif
	160
	161	#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
	162	#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
	163
	164	/*
	165	* Miscellaneous configurable options
	166	*/
	167	#define CFG_HUSH_PARSER
	168	#define CFG_PROMPT_HUSH_PS2 "> "
	169	#define CFG_LONGHELP /* undef to save memory */
	170	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
1bec3d30	171	#if defined(CONFIG_CMD_KGDB)
f901a83b WD	172	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	173	#else
	174	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	175	#endif
	176	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	177	#define CFG_MAXARGS 16 /* max number of command args */
	178	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	179
	180	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	181	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	182
	183	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	184
	185	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	186
	187	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	188
	189	#define CFG_FLASH_BASE 0xFF800000
	190	#define CFG_FLASH_CFI
	191	#define CFG_FLASH_CFI_DRIVER
	192	#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
	193	#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
	194
	195	#define CFG_DIRECT_FLASH_TFTP
	196
1bec3d30	197	#if defined(CONFIG_CMD_JFFS2)
f901a83b WD	198	#define CFG_JFFS2_FIRST_BANK 0
	199	#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
	200	#define CFG_JFFS2_FIRST_SECTOR 0
	201	#define CFG_JFFS2_LAST_SECTOR 62
	202	#define CFG_JFFS2_SORT_FRAGMENTS
	203	#define CFG_JFFS_CUSTOM_PART
80ff4f99	204	#endif
f901a83b	205
1bec3d30	206	#if defined(CONFIG_CMD_I2C)
f901a83b WD	207	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
	208	#define CFG_I2C_SPEED 100000 /* I2C speed */
	209	#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
80ff4f99	210	#endif
f901a83b WD	211
	212	#define CFG_MONITOR_BASE TEXT_BASE
	213	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	214	#define CFG_RAMBOOT
	215	#endif
	216
	217	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
	218
	219	#define CFG_ENV_IS_IN_FLASH
	220
	221	#ifdef CFG_ENV_IS_IN_FLASH
	222	#define CFG_ENV_SECT_SIZE 0x20000
	223	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
	224	#endif /* CFG_ENV_IS_IN_FLASH */
	225
	226	#define CFG_DEFAULT_IMMR 0x00010000
	227
	228	#define CFG_IMMR 0xF0000000
	229
	230	#define CFG_INIT_RAM_ADDR CFG_IMMR
	231	#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
	232	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	233	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	234	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	235
	236	/* Hard reset configuration word */
	237	#define CFG_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
	238	/* No slaves */
	239	#define CFG_HRCW_SLAVE1 0
	240	#define CFG_HRCW_SLAVE2 0
	241	#define CFG_HRCW_SLAVE3 0
	242	#define CFG_HRCW_SLAVE4 0
	243	#define CFG_HRCW_SLAVE5 0
	244	#define CFG_HRCW_SLAVE6 0
	245	#define CFG_HRCW_SLAVE7 0
	246
	247	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	248	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	249
	250	#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
	251	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	252
	253	#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
1bec3d30	254	#if defined(CONFIG_CMD_KGDB)
f901a83b WD	255	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	256	#endif
	257
	258	#define CFG_HID0_INIT 0
	259	#define CFG_HID0_FINAL (HID0_ICE \| HID0_IFEM \| HID0_ABE)
	260
	261	#define CFG_HID2 0
	262
	263	#define CFG_SIUMCR 0x01240200
	264	#define CFG_SYPCR 0xFFFF0683
	265	#define CFG_BCR 0x00000000
	266	#define CFG_SCCR SCCR_DFBRG01
	267
	268	#define CFG_RMR RMR_CSRE
	269	#define CFG_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
	270	#define CFG_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
	271	#define CFG_RCCR 0
	272
	273	#define CFG_MPTPR 0x1300
	274	#define CFG_PSDMR 0x82672522
	275	#define CFG_PSRT 0x4B
	276
	277	#define CFG_SDRAM_BASE 0x00000000
	278	#define CFG_SDRAM_BR (CFG_SDRAM_BASE \| 0x00001841)
	279	#define CFG_SDRAM_OR 0xFF0030C0
	280
	281	#define CFG_BR0_PRELIM (CFG_FLASH_BASE \| 0x00001801)
	282	#define CFG_OR0_PRELIM 0xFF8008C2
	283	#define CFG_BR2_PRELIM (CFG_BCSR \| 0x00000801)
	284	#define CFG_OR2_PRELIM 0xFFF00864
	285
	286	#define CFG_RESET_ADDRESS 0xC0000000
	287
	288	#endif /* __CONFIG_H */