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14c32614 TS |
1 | /* |
2 | * (C) Copyright 2011 | |
3 | * egnite GmbH <info@egnite.de> | |
4 | * | |
5 | * Configuation settings for Ethernut 5 with AT91SAM9XE. | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
14c32614 TS |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | #include <asm/hardware.h> | |
14 | ||
15 | /* The first stage boot loader expects u-boot running at this address. */ | |
16 | #define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */ | |
17 | ||
18 | /* The first stage boot loader takes care of low level initialization. */ | |
19 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
20 | ||
21 | /* Set our official architecture number. */ | |
14c32614 TS |
22 | #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 |
23 | ||
24 | /* CPU information */ | |
14c32614 TS |
25 | #define CONFIG_ARCH_CPU_INIT |
26 | ||
27 | /* ARM asynchronous clock */ | |
28 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ | |
29 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ | |
14c32614 TS |
30 | |
31 | /* 32kB internal SRAM */ | |
32 | #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ | |
33 | #define CONFIG_SRAM_SIZE (32 << 10) | |
3d6ba91e RH |
34 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \ |
35 | GENERATED_GBL_DATA_SIZE) | |
14c32614 TS |
36 | |
37 | /* 128MB SDRAM in 1 bank */ | |
38 | #define CONFIG_NR_DRAM_BANKS 1 | |
39 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 | |
40 | #define CONFIG_SYS_SDRAM_SIZE (128 << 20) | |
41 | #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE | |
42 | #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR | |
43 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) | |
44 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
45 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \ | |
46 | - CONFIG_SYS_MALLOC_LEN) | |
47 | ||
48 | /* 512kB on-chip NOR flash */ | |
49 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
50 | # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ | |
51 | # define CONFIG_AT91_EFLASH | |
52 | # define CONFIG_SYS_MAX_FLASH_SECT 32 | |
53 | # define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */ | |
54 | # define CONFIG_EFLASH_PROTSECTORS 1 | |
55 | ||
56 | /* 512kB DataFlash at NPCS0 */ | |
57 | #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 | |
58 | #define CONFIG_HAS_DATAFLASH | |
14c32614 TS |
59 | #define CONFIG_ATMEL_DATAFLASH_SPI |
60 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 | |
61 | #define DATAFLASH_TCSS (0x1a << 16) | |
62 | #define DATAFLASH_TCHS (0x1 << 24) | |
63 | ||
64 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
65 | #define CONFIG_ENV_OFFSET 0x3DE000 | |
66 | #define CONFIG_ENV_SECT_SIZE (132 << 10) | |
67 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
68 | #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \ | |
69 | + CONFIG_ENV_OFFSET) | |
70 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \ | |
71 | + 0x042000) | |
72 | ||
73 | /* SPI */ | |
74 | #define CONFIG_ATMEL_SPI | |
14c32614 TS |
75 | #define AT91_SPI_CLK 15000000 |
76 | ||
77 | /* Serial port */ | |
78 | #define CONFIG_ATMEL_USART | |
79 | #define CONFIG_USART3 /* USART 3 is DBGU */ | |
14c32614 TS |
80 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
81 | #define CONFIG_USART_ID ATMEL_ID_SYS | |
82 | ||
83 | /* Misc. hardware drivers */ | |
84 | #define CONFIG_AT91_GPIO | |
85 | ||
86 | /* Command line configuration */ | |
14c32614 | 87 | #define CONFIG_CMD_NAND |
14c32614 | 88 | |
ef0f2f57 | 89 | #ifndef MINIMAL_LOADER |
14c32614 TS |
90 | #define CONFIG_CMD_REISER |
91 | #define CONFIG_CMD_SAVES | |
14c32614 TS |
92 | #endif |
93 | ||
94 | /* NAND flash */ | |
95 | #ifdef CONFIG_CMD_NAND | |
96 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
97 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
98 | #define CONFIG_SYS_NAND_DBW_8 | |
99 | #define CONFIG_NAND_ATMEL | |
100 | /* our ALE is AD21 */ | |
101 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
102 | /* our CLE is AD22 */ | |
103 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
ac45bb16 | 104 | #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) |
14c32614 TS |
105 | #endif |
106 | ||
107 | /* JFFS2 */ | |
108 | #ifdef CONFIG_CMD_JFFS2 | |
14c32614 TS |
109 | #define CONFIG_JFFS2_CMDLINE |
110 | #define CONFIG_JFFS2_NAND | |
111 | #endif | |
112 | ||
113 | /* Ethernet */ | |
14c32614 TS |
114 | #define CONFIG_NET_RETRY_COUNT 20 |
115 | #define CONFIG_MACB | |
116 | #define CONFIG_RMII | |
117 | #define CONFIG_PHY_ID 0 | |
118 | #define CONFIG_MACB_SEARCH_PHY | |
119 | ||
120 | /* MMC */ | |
121 | #ifdef CONFIG_CMD_MMC | |
14c32614 TS |
122 | #define CONFIG_GENERIC_ATMEL_MCI |
123 | #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 | |
124 | #endif | |
125 | ||
126 | /* USB */ | |
127 | #ifdef CONFIG_CMD_USB | |
128 | #define CONFIG_USB_ATMEL | |
dcd2f1a0 | 129 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
14c32614 TS |
130 | #define CONFIG_USB_OHCI_NEW |
131 | #define CONFIG_SYS_USB_OHCI_CPU_INIT | |
132 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 | |
133 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" | |
134 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 | |
14c32614 TS |
135 | #endif |
136 | ||
137 | /* RTC */ | |
138 | #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) | |
139 | #define CONFIG_RTC_PCF8563 | |
140 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 | |
141 | #endif | |
142 | ||
143 | /* I2C */ | |
144 | #define CONFIG_SYS_MAX_I2C_BUS 1 | |
14c32614 | 145 | |
ea818dbb HS |
146 | #define CONFIG_SYS_I2C |
147 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
148 | #define CONFIG_SYS_I2C_SOFT_SPEED 100000 | |
149 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0 | |
150 | ||
14c32614 TS |
151 | #define I2C_SOFT_DECLARATIONS |
152 | ||
153 | #define GPIO_I2C_SCL AT91_PIO_PORTA, 24 | |
154 | #define GPIO_I2C_SDA AT91_PIO_PORTA, 23 | |
155 | ||
156 | #define I2C_INIT { \ | |
157 | at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \ | |
158 | at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ | |
159 | at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \ | |
160 | at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \ | |
161 | at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ | |
162 | } | |
163 | ||
164 | #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0) | |
165 | #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0) | |
166 | #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) | |
167 | #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) | |
168 | #define I2C_DELAY udelay(100) | |
169 | #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) | |
170 | ||
171 | /* DHCP/BOOTP options */ | |
172 | #ifdef CONFIG_CMD_DHCP | |
173 | #define CONFIG_BOOTP_BOOTFILESIZE | |
174 | #define CONFIG_BOOTP_BOOTPATH | |
175 | #define CONFIG_BOOTP_GATEWAY | |
176 | #define CONFIG_BOOTP_HOSTNAME | |
177 | #define CONFIG_SYS_AUTOLOAD "n" | |
178 | #endif | |
179 | ||
180 | /* File systems */ | |
181 | #define CONFIG_MTD_DEVICE | |
182 | #define CONFIG_MTD_PARTITIONS | |
183 | #if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND) | |
184 | #define MTDIDS_DEFAULT "nand0=atmel_nand" | |
185 | #define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)" | |
186 | #endif | |
14c32614 TS |
187 | |
188 | /* Boot command */ | |
14c32614 TS |
189 | #define CONFIG_CMDLINE_TAG |
190 | #define CONFIG_SETUP_MEMORY_TAGS | |
191 | #define CONFIG_INITRD_TAG | |
192 | #define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm" | |
193 | #if defined(CONFIG_CMD_NAND) | |
194 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ | |
195 | "root=/dev/mtdblock0 " \ | |
196 | MTDPARTS_DEFAULT \ | |
197 | " rw rootfstype=jffs2" | |
198 | #endif | |
199 | ||
200 | /* Misc. u-boot settings */ | |
14c32614 TS |
201 | #define CONFIG_SYS_CBSIZE 256 |
202 | #define CONFIG_SYS_MAXARGS 16 | |
203 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \ | |
204 | + sizeof(CONFIG_SYS_PROMPT)) | |
205 | #define CONFIG_SYS_LONGHELP | |
206 | #define CONFIG_CMDLINE_EDITING | |
207 | ||
208 | #endif |