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137fdd9f NG |
1 | /* |
2 | * (C) Copyright 2007 Netstal Maschinen AG | |
3 | * Niklaus Giger (Niklaus.Giger@netstal.com) | |
4 | * | |
5 | * (C) Copyright 2006-2007 | |
6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
7 | * | |
8 | * (C) Copyright 2006 | |
9 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
10 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | /************************************************************************ | |
29 | * hcu5.h - configuration for HCU5 board (derived from sequoia.h) | |
30 | ***********************************************************************/ | |
31 | ||
32 | #ifndef __CONFIG_H | |
33 | #define __CONFIG_H | |
34 | ||
35 | /*----------------------------------------------------------------------- | |
36 | * High Level Configuration Options | |
37 | *----------------------------------------------------------------------*/ | |
38 | #define CONFIG_HCU5 1 /* Board is HCU5 */ | |
39 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ | |
40 | #define CONFIG_440 1 /* ... PPC440 family */ | |
41 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
42 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ | |
43 | ||
44 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
45 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
137fdd9f NG |
46 | |
47 | /*----------------------------------------------------------------------- | |
48 | * Base addresses -- Note these are effective addresses where the | |
49 | * actual resources get mapped (not physical addresses) | |
50 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
51 | #define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */ |
52 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ | |
53 | ||
54 | #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 3 | |
55 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xfff00000 | |
56 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
57 | #define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ | |
58 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
59 | #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ | |
60 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE | |
61 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ | |
62 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
63 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 | |
64 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 | |
65 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 | |
137fdd9f NG |
66 | |
67 | /* Don't change either of these */ | |
6d0f6bcf | 68 | #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ |
137fdd9f | 69 | |
6d0f6bcf JCPV |
70 | #define CONFIG_SYS_USB2D0_BASE 0xe0000100 |
71 | #define CONFIG_SYS_USB_DEVICE 0xe0000000 | |
72 | #define CONFIG_SYS_USB_HOST 0xe0000400 | |
137fdd9f NG |
73 | |
74 | /*----------------------------------------------------------------------- | |
75 | * Initial RAM & stack pointer | |
76 | *----------------------------------------------------------------------*/ | |
77 | /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ | |
6d0f6bcf | 78 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ |
137fdd9f | 79 | |
6d0f6bcf JCPV |
80 | #define CONFIG_SYS_INIT_RAM_END (4 << 10) |
81 | #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ | |
82 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
83 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR | |
137fdd9f NG |
84 | |
85 | /*----------------------------------------------------------------------- | |
86 | * Serial Port | |
87 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 88 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
137fdd9f | 89 | #define CONFIG_BAUDRATE 9600 |
4371090e NG |
90 | #define CONFIG_SERIAL_MULTI 1 |
91 | /* needed to be able to define | |
137fdd9f NG |
92 | CONFIG_SERIAL_SOFTWARE_FIFO, but |
93 | CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */ | |
94 | /* Size (bytes) of interrupt driven serial port buffer. | |
95 | * Set to 0 to use polling instead of interrupts. | |
96 | * Setting to 0 will also disable RTS/CTS handshaking. | |
97 | */ | |
98 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
99 | #undef CONFIG_UART1_CONSOLE | |
100 | ||
4371090e | 101 | #undef CONFIG_CMD_HWFLOW |
6d0f6bcf | 102 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
137fdd9f NG |
103 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
104 | ||
105 | /*----------------------------------------------------------------------- | |
106 | * Environment | |
107 | *----------------------------------------------------------------------*/ | |
108 | ||
9314cee6 | 109 | #undef CONFIG_ENV_IS_IN_NVRAM |
5a1aceb0 | 110 | #define CONFIG_ENV_IS_IN_FLASH |
bb1f8b4f | 111 | #undef CONFIG_ENV_IS_IN_EEPROM |
93f6d725 | 112 | #undef CONFIG_ENV_IS_NOWHERE |
137fdd9f | 113 | |
bb1f8b4f | 114 | #ifdef CONFIG_ENV_IS_IN_EEPROM |
137fdd9f | 115 | /* Put the environment after the SDRAM and bootstrap configuration */ |
53677ef1 | 116 | #define PROM_SIZE 2048 |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_BOOSTRAP_OPTION_OFFSET 512 |
118 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_BOOSTRAP_OPTION_OFFSET + 0x10) | |
0e8d1586 | 119 | #define CONFIG_ENV_SIZE (PROM_SIZE-CONFIG_ENV_OFFSET) |
137fdd9f NG |
120 | #endif |
121 | ||
5a1aceb0 | 122 | #ifdef CONFIG_ENV_IS_IN_FLASH |
137fdd9f | 123 | /* Put the environment in Flash */ |
0e8d1586 | 124 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
6d0f6bcf | 125 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 126 | #define CONFIG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */ |
137fdd9f NG |
127 | |
128 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
129 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
130 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
4371090e | 131 | |
137fdd9f NG |
132 | #endif |
133 | ||
134 | /*----------------------------------------------------------------------- | |
135 | * DDR SDRAM | |
136 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
137 | #define CONFIG_SYS_MBYTES_SDRAM (128) /* 128 MB or 256 MB */ |
138 | #define CONFIG_SYS_DDR_CACHED_ADDR 0x50000000 /* setup 2nd TLB cached here */ | |
4371090e NG |
139 | #undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */ |
140 | #define CONFIG_DDR_ECC 1 /* enable ECC */ | |
141 | ||
142 | /* Following two definitions must be kept in sync with config.h of vxWorks */ | |
143 | #define USER_RESERVED_MEM ( 0) /* in kB */ | |
144 | #define PM_RESERVED_MEM ( 64) /* in kB: pmLib reserved area size */ | |
145 | #define CONFIG_PRAM ( USER_RESERVED_MEM + PM_RESERVED_MEM ) | |
137fdd9f NG |
146 | |
147 | /*----------------------------------------------------------------------- | |
148 | * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the | |
149 | * the second internal I2C controller of the PPC440EPx | |
150 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 151 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
137fdd9f | 152 | |
ef5b4f22 | 153 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
137fdd9f | 154 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
156 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
137fdd9f NG |
157 | |
158 | /* This is the 7bit address of the device, not including P. */ | |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
160 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
137fdd9f NG |
161 | |
162 | /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ | |
6d0f6bcf JCPV |
163 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
164 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
165 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
166 | #undef CONFIG_SYS_I2C_MULTI_EEPROMS | |
137fdd9f NG |
167 | |
168 | ||
169 | #define CONFIG_PREBOOT "echo;" \ | |
170 | "echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\ | |
171 | "echo" | |
172 | ||
173 | #undef CONFIG_BOOTARGS | |
174 | ||
175 | /* Setup some board specific values for the default environment variables */ | |
176 | #define CONFIG_HOSTNAME hcu5 | |
4371090e | 177 | #define CONFIG_IPADDR 172.25.1.99 |
53677ef1 | 178 | #define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ |
137fdd9f NG |
179 | #define CONFIG_OVERWRITE_ETHADDR_ONCE |
180 | #define CONFIG_SERVERIP 172.25.1.3 | |
181 | ||
6d0f6bcf | 182 | #define CONFIG_SYS_TFTP_LOADADDR 0x01000000 /* @16 MB */ |
137fdd9f | 183 | |
53677ef1 | 184 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
137fdd9f NG |
185 | "netdev=eth0\0" \ |
186 | "loadaddr=0x01000000\0" \ | |
187 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
188 | "nfsroot=${serverip}:${rootpath}\0" \ | |
189 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
190 | "addip=setenv bootargs ${bootargs} " \ | |
191 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
192 | ":${hostname}:${netdev}:off panic=1\0" \ | |
193 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
53677ef1 | 194 | "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ |
137fdd9f | 195 | "bootm\0" \ |
53677ef1 WD |
196 | "bootfile=hcu5/uImage\0" \ |
197 | "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \ | |
198 | "load=tftp 100000 hcu5/u-boot.bin\0" \ | |
ef5b4f22 NG |
199 | "update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \ |
200 | "cp.b 100000 FFFB0000 50000\0" \ | |
d8ab58b2 | 201 | "upd=run load update\0" \ |
ef5b4f22 NG |
202 | "vx_rom=hcu5/hcu5_vx_rom\0" \ |
203 | "vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \ | |
204 | "vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \ | |
205 | " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \ | |
53677ef1 | 206 | "usbargs=setenv bootargs root=/dev/sda1 ro\0" \ |
4371090e | 207 | "linux=usb start; ext2load usb 0 ${loadaddr} /boot/uImage;" \ |
53677ef1 | 208 | "run usbargs addip addtty; bootm\0" \ |
4371090e NG |
209 | "net_nfs_fdt=tftp 200000 ${bootfile};" \ |
210 | "tftp ${fdt_addr} ${fdt_file};" \ | |
211 | "run nfsargs addip addtty;" \ | |
212 | "bootm 200000 - ${fdt_addr}\0" \ | |
213 | "fdt_file=hcu5/hcu5.dtb\0" \ | |
214 | "fdt_addr=400000\0" \ | |
137fdd9f NG |
215 | "" |
216 | #define CONFIG_BOOTCOMMAND "run vx" | |
217 | ||
137fdd9f | 218 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
137fdd9f NG |
219 | |
220 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 221 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
137fdd9f NG |
222 | |
223 | #define CONFIG_M88E1111_PHY 1 | |
224 | #define CONFIG_IBM_EMAC4_V4 1 | |
225 | #define CONFIG_MII 1 /* MII PHY management */ | |
ef5b4f22 | 226 | #define CONFIG_PHY_ADDR 1 /* PHY address, like on HCU4 */ |
137fdd9f | 227 | |
ef5b4f22 | 228 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
137fdd9f NG |
229 | |
230 | #define CONFIG_HAS_ETH0 | |
6d0f6bcf | 231 | #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & desc. */ |
137fdd9f NG |
232 | |
233 | #define CONFIG_NET_MULTI 1 | |
ef5b4f22 NG |
234 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
235 | #define CONFIG_PHY1_ADDR 2 | |
137fdd9f NG |
236 | |
237 | /* USB */ | |
238 | #define CONFIG_USB_OHCI | |
239 | #define CONFIG_USB_STORAGE | |
240 | ||
241 | /* Comment this out to enable USB 1.1 device */ | |
242 | #define USB_2_0_DEVICE | |
243 | ||
137fdd9f NG |
244 | /* Partitions */ |
245 | #define CONFIG_MAC_PARTITION | |
246 | #define CONFIG_DOS_PARTITION | |
247 | #define CONFIG_ISO_PARTITION | |
248 | ||
3b3bff4c SR |
249 | /* |
250 | * BOOTP options | |
251 | */ | |
252 | #define CONFIG_BOOTP_BOOTFILESIZE | |
253 | #define CONFIG_BOOTP_BOOTPATH | |
254 | #define CONFIG_BOOTP_GATEWAY | |
255 | #define CONFIG_BOOTP_HOSTNAME | |
137fdd9f | 256 | |
3b3bff4c SR |
257 | /* |
258 | * Command line configuration. | |
259 | */ | |
260 | #include <config_cmd_default.h> | |
261 | ||
262 | #define CONFIG_CMD_ASKENV | |
3b3bff4c SR |
263 | #define CONFIG_CMD_DHCP |
264 | #define CONFIG_CMD_DIAG | |
265 | #define CONFIG_CMD_EEPROM | |
266 | #define CONFIG_CMD_ELF | |
267 | #define CONFIG_CMD_FLASH | |
268 | #define CONFIG_CMD_FAT | |
269 | #define CONFIG_CMD_I2C | |
270 | #define CONFIG_CMD_IMMAP | |
271 | #define CONFIG_CMD_IRQ | |
272 | #define CONFIG_CMD_MII | |
273 | #define CONFIG_CMD_NET | |
274 | #define CONFIG_CMD_NFS | |
275 | #define CONFIG_CMD_PING | |
276 | #define CONFIG_CMD_REGINFO | |
277 | #define CONFIG_CMD_SDRAM | |
278 | #define CONFIG_CMD_USB | |
137fdd9f | 279 | |
4371090e | 280 | /* POST support */ |
6d0f6bcf JCPV |
281 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
282 | CONFIG_SYS_POST_CPU | \ | |
283 | CONFIG_SYS_POST_UART | \ | |
284 | CONFIG_SYS_POST_I2C | \ | |
285 | CONFIG_SYS_POST_CACHE | \ | |
286 | CONFIG_SYS_POST_FPU | \ | |
287 | CONFIG_SYS_POST_ETHER | \ | |
288 | CONFIG_SYS_POST_SPR) | |
289 | #define CONFIG_SYS_POST_UART_TABLE {UART0_BASE} | |
290 | ||
291 | #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) | |
292 | #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ | |
293 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ | |
4371090e | 294 | |
3b3bff4c | 295 | #define CONFIG_SUPPORT_VFAT |
137fdd9f NG |
296 | |
297 | /*----------------------------------------------------------------------- | |
298 | * Miscellaneous configurable options | |
299 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
300 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
301 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
3b3bff4c | 302 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 303 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
137fdd9f | 304 | #else |
6d0f6bcf | 305 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
137fdd9f | 306 | #endif |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
308 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
309 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
137fdd9f | 310 | |
6d0f6bcf JCPV |
311 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
312 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
137fdd9f | 313 | |
6d0f6bcf JCPV |
314 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
315 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
137fdd9f | 316 | |
6d0f6bcf | 317 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
137fdd9f NG |
318 | |
319 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
320 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
321 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
137fdd9f NG |
322 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
323 | ||
324 | /*----------------------------------------------------------------------- | |
325 | * PCI stuff | |
326 | *----------------------------------------------------------------------*/ | |
327 | /* General PCI */ | |
4371090e | 328 | #define CONFIG_PCI 1 /* include pci support */ |
137fdd9f | 329 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
4371090e | 330 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 331 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr map to CONFIG_SYS_PCI_MEMBASE*/ |
137fdd9f NG |
332 | |
333 | /* Board-specific PCI */ | |
6d0f6bcf JCPV |
334 | #define CONFIG_SYS_PCI_TARGET_INIT |
335 | #define CONFIG_SYS_PCI_MASTER_INIT | |
137fdd9f | 336 | |
6d0f6bcf JCPV |
337 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
338 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
137fdd9f NG |
339 | |
340 | /* | |
341 | * For booting Linux, the board info and command line data | |
342 | * have to be in the first 8 MB of memory, since this is | |
343 | * the maximum mapped by the Linux kernel during initialization. | |
344 | */ | |
6d0f6bcf | 345 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
4371090e NG |
346 | |
347 | /*----------------------------------------------------------------------- | |
348 | * Flash | |
349 | *----------------------------------------------------------------------*/ | |
350 | ||
a0794948 | 351 | /* Use common CFI driver */ |
6d0f6bcf | 352 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 353 | #define CONFIG_FLASH_CFI_DRIVER |
a0794948 NG |
354 | /* board provides its own flash_init code */ |
355 | #define CONFIG_FLASH_CFI_LEGACY 1 | |
6d0f6bcf JCPV |
356 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT |
357 | #define CONFIG_SYS_FLASH_LEGACY_512Kx8 1 | |
a0794948 NG |
358 | |
359 | /* print 'E' for empty sector on flinfo */ | |
6d0f6bcf | 360 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
a0794948 | 361 | |
6d0f6bcf JCPV |
362 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
363 | #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ | |
4371090e | 364 | |
137fdd9f NG |
365 | /*----------------------------------------------------------------------- |
366 | * External Bus Controller (EBC) Setup | |
367 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
368 | #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE |
369 | #define CONFIG_SYS_CS_1 0xC8000000 /* CAN */ | |
370 | #define CONFIG_SYS_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */ | |
371 | #define CONFIG_SYS_CPLD CONFIG_SYS_CS_2 | |
372 | #define CONFIG_SYS_CS_3 0xCE000000 /* CPLD and IMC-Bus Fast */ | |
137fdd9f | 373 | |
6d0f6bcf JCPV |
374 | #define CONFIG_SYS_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */ |
375 | #define CONFIG_SYS_EBC_PB0AP 0x02005400 | |
376 | #define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* (CONFIG_SYS_FLASH | 0xda000) */ | |
377 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ | |
137fdd9f | 378 | |
4371090e | 379 | /* Memory Bank 1 CAN-Chips initialization */ |
6d0f6bcf JCPV |
380 | #define CONFIG_SYS_EBC_PB1AP 0x02054500 |
381 | #define CONFIG_SYS_EBC_PB1CR 0xC8018000 | |
137fdd9f | 382 | |
4371090e | 383 | /* Memory Bank 2 CPLD/IMC-Bus standard initialization */ |
6d0f6bcf JCPV |
384 | #define CONFIG_SYS_EBC_PB2AP 0x01840300 |
385 | #define CONFIG_SYS_EBC_PB2CR 0xCC0BA000 | |
137fdd9f | 386 | |
4371090e | 387 | /* Memory Bank 3 IMC-Bus fast mode initialization */ |
6d0f6bcf JCPV |
388 | #define CONFIG_SYS_EBC_PB3AP 0x01800300 |
389 | #define CONFIG_SYS_EBC_PB3CR 0xCE0BA000 | |
137fdd9f | 390 | |
4371090e | 391 | /* Memory Bank 4 (not used) initialization */ |
6d0f6bcf JCPV |
392 | #undef CONFIG_SYS_EBC_PB4AP |
393 | #undef CONFIG_SYS_EBC_PB4CR | |
137fdd9f | 394 | |
4371090e | 395 | /* Memory Bank 5 (not used) initialization */ |
6d0f6bcf JCPV |
396 | #undef CONFIG_SYS_EBC_PB5AP |
397 | #undef CONFIG_SYS_EBC_PB5CR | |
137fdd9f | 398 | |
6d0f6bcf JCPV |
399 | #define HCU_CPLD_VERSION_REGISTER ( CONFIG_SYS_CPLD + 0x0F00000 ) |
400 | #define HCU_HW_VERSION_REGISTER ( CONFIG_SYS_CPLD + 0x1400000 ) | |
137fdd9f | 401 | |
6d0f6bcf JCPV |
402 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
403 | #ifdef CONFIG_SYS_HUSH_PARSER | |
404 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
137fdd9f NG |
405 | #endif |
406 | ||
3b3bff4c | 407 | #if defined(CONFIG_CMD_KGDB) |
137fdd9f NG |
408 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
409 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
410 | #endif | |
4371090e NG |
411 | |
412 | /* pass open firmware flat tree */ | |
413 | #define CONFIG_OF_LIBFDT 1 | |
414 | #define CONFIG_OF_BOARD_SETUP 1 | |
415 | ||
137fdd9f | 416 | #endif /* __CONFIG_H */ |