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Convert CONFIG_BOOTCOUNT_I2C to Kconfig
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1/*
2 * (C) Copyright 2013
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * Based on:
6 * Copyright (c) 2011 IDS GmbH, Germany
7 * Sergej Stepanov <ste@ids.de>
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 */
18#define CONFIG_MPC831x
19#define CONFIG_MPC8313
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20
21#define CONFIG_FSL_ELBC
22
23#define CONFIG_MISC_INIT_R
24
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25#define CONFIG_BOOT_RETRY_TIME 900
26#define CONFIG_BOOT_RETRY_MIN 30
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27#define CONFIG_RESET_TO_RETRY
28
29#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
30#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
31
32#define CONFIG_SYS_IMMR 0xF0000000
33
34#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
35#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
36
37/*
38 * Hardware Reset Configuration Word
39 * if CLKIN is 66.000MHz, then
40 * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
41 */
42#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
43 HRCWL_DDR_TO_SCB_CLK_2X1 |\
44 HRCWL_CSB_TO_CLKIN_2X1 |\
45 HRCWL_CORE_TO_CSB_2X1)
46
47#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\
48 HRCWH_CORE_ENABLE |\
49 HRCWH_FROM_0XFFF00100 |\
50 HRCWH_BOOTSEQ_DISABLE |\
51 HRCWH_SW_WATCHDOG_DISABLE |\
52 HRCWH_ROM_LOC_LOCAL_8BIT |\
53 HRCWH_RL_EXT_LEGACY |\
54 HRCWH_TSEC1M_IN_MII |\
55 HRCWH_TSEC2M_IN_MII |\
56 HRCWH_BIG_ENDIAN)
57
58#define CONFIG_SYS_SICRH 0x00000000
59#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
60
61#define CONFIG_HWCONFIG
62
63#define CONFIG_SYS_HID0_INIT 0x000000000
64#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\
65 HID0_ENABLE_INSTRUCTION_CACHE |\
66 HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
67
68#define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
69
70/*
71 * Definitions for initial stack pointer and data area (in DCACHE )
72 */
73#define CONFIG_SYS_INIT_RAM_LOCK
74#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
75#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
76#define CONFIG_SYS_GBL_DATA_SIZE 0x100
77#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
78 - CONFIG_SYS_GBL_DATA_SIZE)
79#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
80
81/*
82 * Local Bus LCRR and LBCR regs
83 */
84#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
85#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
86#define CONFIG_SYS_LBC_LBCR (0x00040000 |\
87 (0xFF << LBCR_BMT_SHIFT) |\
88 0xF)
89
90#define CONFIG_SYS_LBC_MRTPR 0x20000000
91
92/*
93 * Internal Definitions
94 */
95/*
96 * DDR Setup
97 */
98#define CONFIG_SYS_DDR_BASE 0x00000000
99#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
100#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
101
102/*
103 * Manually set up DDR parameters,
104 * as this board has not the SPD connected to I2C.
105 */
106#define CONFIG_SYS_DDR_SIZE 256 /* MB */
107#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
108 0x00010000 |\
109 CSCONFIG_ROW_BIT_13 |\
110 CSCONFIG_COL_BIT_10)
111
112#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
113 CSCONFIG_BANK_BIT_3)
114
115#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
116#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
117 (3 << TIMING_CFG0_WRT_SHIFT) |\
118 (3 << TIMING_CFG0_RRT_SHIFT) |\
119 (3 << TIMING_CFG0_WWT_SHIFT) |\
120 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
121 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
122 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
123 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
124#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
125 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
126 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
127 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
128 (4 << TIMING_CFG1_REFREC_SHIFT) |\
129 (4 << TIMING_CFG1_WRREC_SHIFT) |\
130 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
131 (2 << TIMING_CFG1_WRTORD_SHIFT))
132#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
133 (5 << TIMING_CFG2_CPO_SHIFT) |\
134 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
135 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
136 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
137 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
138 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
139
140#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
141 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
142
143#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
144 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
145 SDRAM_CFG_DBW_32 |\
146 SDRAM_CFG_SDRAM_TYPE_DDR2)
147
148#define CONFIG_SYS_SDRAM_CFG2 0x00401000
149#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
150 (0x0242 << SDRAM_MODE_SD_SHIFT))
151#define CONFIG_SYS_DDR_MODE_2 0x00000000
152#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
153#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
154 DDRCDR_PZ_NOMZ |\
155 DDRCDR_NZ_NOMZ |\
156 DDRCDR_ODT |\
157 DDRCDR_M_ODR |\
158 DDRCDR_Q_DRN)
159
160/*
161 * on-board devices
162 */
163#define CONFIG_TSEC1
164#define CONFIG_TSEC2
165#define CONFIG_TSEC_ENET
eaf8c986 166#define CONFIG_HARD_SPI
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167
168/*
169 * NOR FLASH setup
170 */
171#define CONFIG_SYS_FLASH_CFI
172#define CONFIG_FLASH_CFI_DRIVER
173#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
174#define CONFIG_FLASH_SHOW_PROGRESS 50
175#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
176
177#define CONFIG_SYS_FLASH_BASE 0xFF800000
178#define CONFIG_SYS_FLASH_SIZE 8
179#define CONFIG_SYS_FLASH_PROTECTION
180
181#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
182#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016
183
184#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
185 BR_PS_8 |\
186 BR_MS_GPCM |\
187 BR_V)
188
189#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
190 OR_GPCM_SCY_10 |\
191 OR_GPCM_EHTR |\
192 OR_GPCM_TRLX |\
193 OR_GPCM_CSNT |\
194 OR_GPCM_EAD)
195#define CONFIG_SYS_MAX_FLASH_BANKS 1
196#define CONFIG_SYS_MAX_FLASH_SECT 128
197
198#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
199#define CONFIG_SYS_FLASH_WRITE_TOUT 500
200
201/*
202 * NAND FLASH setup
203 */
204#define CONFIG_SYS_NAND_BASE 0xE1000000
205#define CONFIG_SYS_MAX_NAND_DEVICE 1
206#define CONFIG_SYS_NAND_MAX_CHIPS 1
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207#define CONFIG_NAND_FSL_ELBC
208#define CONFIG_SYS_NAND_PAGE_SIZE (2048)
209#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
210#define NAND_CACHE_PAGES 64
211
212#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
213#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
214#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
215#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
216
217#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\
218 (2<<BR_DECC_SHIFT) |\
219 BR_PS_8 |\
220 BR_MS_FCM |\
221 BR_V)
222
223#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\
224 OR_FCM_PGS |\
225 OR_FCM_CSCT |\
226 OR_FCM_CST |\
227 OR_FCM_CHT |\
228 OR_FCM_SCY_4 |\
229 OR_FCM_TRLX |\
230 OR_FCM_EHTR |\
231 OR_FCM_RST)
232
233/*
234 * MRAM setup
235 */
236#define CONFIG_SYS_MRAM_BASE 0xE2000000
237#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
238#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE
239#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */
240
241#define CONFIG_SYS_OR_TIMING_MRAM
242
243#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\
244 BR_PS_8 |\
245 BR_MS_GPCM |\
246 BR_V)
247
248#define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74
249
250/*
251 * CPLD setup
252 */
253#define CONFIG_SYS_CPLD_BASE 0xE3000000
254#define CONFIG_SYS_CPLD_SIZE 0x8000
255#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE
256#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E
257
258#define CONFIG_SYS_OR_TIMING_MRAM
259
260#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\
261 BR_PS_8 |\
262 BR_MS_GPCM |\
263 BR_V)
264
265#define CONFIG_SYS_OR3_PRELIM 0xFFFF8814
266
267/*
268 * HW-Watchdog
269 */
270#define CONFIG_WATCHDOG 1
271#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
272
273/*
274 * I2C setup
275 */
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276#define CONFIG_SYS_I2C
277#define CONFIG_SYS_I2C_FSL
278#define CONFIG_SYS_FSL_I2C_SPEED 400000
279#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
280#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
281#define CONFIG_RTC_PCF8563
282#define CONFIG_SYS_I2C_RTC_ADDR 0x51
283
284/*
285 * SPI setup
286 */
287#ifdef CONFIG_HARD_SPI
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288#define CONFIG_SYS_GPIO1_PRELIM
289#define CONFIG_SYS_GPIO1_DIR 0x00000001
290#define CONFIG_SYS_GPIO1_DAT 0x00000001
291#endif
292
293/*
294 * Ethernet setup
295 */
296#ifdef CONFIG_TSEC1
297#define CONFIG_HAS_ETH0
298#define CONFIG_TSEC1_NAME "TSEC0"
299#define CONFIG_SYS_TSEC1_OFFSET 0x24000
300#define TSEC1_PHY_ADDR 0x1
301#define TSEC1_FLAGS TSEC_GIGABIT
302#define TSEC1_PHYIDX 0
303#endif
304
305#ifdef CONFIG_TSEC2
306#define CONFIG_HAS_ETH1
307#define CONFIG_TSEC2_NAME "TSEC1"
308#define CONFIG_SYS_TSEC2_OFFSET 0x25000
309#define TSEC2_PHY_ADDR 0x3
310#define TSEC2_FLAGS TSEC_GIGABIT
311#define TSEC2_PHYIDX 0
312#endif
313#define CONFIG_ETHPRIME "TSEC1"
314
315/*
316 * Serial Port
317 */
318#define CONFIG_CONS_INDEX 1
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319#define CONFIG_SYS_NS16550_SERIAL
320#define CONFIG_SYS_NS16550_REG_SIZE 1
321
322#define CONFIG_SYS_BAUDRATE_TABLE \
323 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
324#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
325#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
326#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
327
328#define CONFIG_HAS_FSL_DR_USB
329#define CONFIG_SYS_SCCR_USBDRCM 3
330
331/*
332 * BAT's
333 */
334#define CONFIG_HIGH_BATS
335
336/* DDR @ 0x00000000 */
337#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\
338 BATL_PP_10)
339#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\
340 BATU_BL_256M |\
341 BATU_VS |\
342 BATU_VP)
343#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
344#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
345
346/* Initial RAM @ 0xFD000000 */
347#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\
348 BATL_PP_10 |\
349 BATL_GUARDEDSTORAGE)
350#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\
351 BATU_BL_256K |\
352 BATU_VS |\
353 BATU_VP)
354#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
355#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
356
357/* FLASH @ 0xFF800000 */
358#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\
359 BATL_PP_10 |\
360 BATL_GUARDEDSTORAGE)
361#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\
362 BATU_BL_8M |\
363 BATU_VS |\
364 BATU_VP)
365#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\
366 BATL_PP_10 |\
367 BATL_CACHEINHIBIT |\
368 BATL_GUARDEDSTORAGE)
369#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
370
371#define CONFIG_SYS_IBAT3L (0)
372#define CONFIG_SYS_IBAT3U (0)
373#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
374#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
375
376#define CONFIG_SYS_IBAT4L (0)
377#define CONFIG_SYS_IBAT4U (0)
378#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
379#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
380
381/* IMMRBAR @ 0xF0000000 */
382#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\
383 BATL_PP_10 |\
384 BATL_CACHEINHIBIT |\
385 BATL_GUARDEDSTORAGE)
386#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\
387 BATU_BL_128M |\
388 BATU_VS |\
389 BATU_VP)
390#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
391#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
392
393/* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
394#define CONFIG_SYS_IBAT6L (0xE0000000 |\
395 BATL_PP_10 |\
396 BATL_GUARDEDSTORAGE)
397#define CONFIG_SYS_IBAT6U (0xE0000000 |\
398 BATU_BL_256M |\
399 BATU_VS |\
400 BATU_VP)
401#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
402#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
403
404#define CONFIG_SYS_IBAT7L (0)
405#define CONFIG_SYS_IBAT7U (0)
406#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
407#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
408
409/*
410 * U-Boot environment setup
411 */
eaf8c986 412#define CONFIG_BOOTP_BOOTFILESIZE
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413
414/*
415 * The reserved memory
416 */
417#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
418#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
419#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
420
421/*
422 * Environment Configuration
423 */
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424#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
425 + CONFIG_SYS_MONITOR_LEN)
426#define CONFIG_ENV_SIZE 0x20000
427#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
428#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
429
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430#define CONFIG_NETDEV eth1
431#define CONFIG_HOSTNAME ids8313
432#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
433#define CONFIG_BOOTFILE "ids8313/uImage"
434#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
435#define CONFIG_FDTFILE "ids8313/ids8313.dtb"
436#define CONFIG_LOADADDR 0x400000
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437#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
438
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439/* Initial Memory map for Linux*/
440#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
441
442/*
443 * Miscellaneous configurable options
444 */
eaf8c986 445#define CONFIG_SYS_CBSIZE 1024
eaf8c986 446#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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447
448#define CONFIG_SYS_MEMTEST_START 0x00001000
449#define CONFIG_SYS_MEMTEST_END 0x00C00000
450
451#define CONFIG_SYS_LOAD_ADDR 0x100000
452#define CONFIG_MII
453#define CONFIG_LOADS_ECHO
454#define CONFIG_TIMESTAMP
455#define CONFIG_PREBOOT "echo;" \
456 "echo Type \\\"run nfsboot\\\" " \
457 "to mount root filesystem over NFS;echo"
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458#define CONFIG_BOOTCOMMAND "run boot_cramfs"
459#undef CONFIG_SYS_LOADS_BAUD_CHANGE
460
461#define CONFIG_JFFS2_NAND
462#define CONFIG_JFFS2_DEV "0"
463
464/* mtdparts command line support */
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465#define CONFIG_FLASH_CFI_MTD
466#define CONFIG_MTD_DEVICE
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467
468#define CONFIG_EXTRA_ENV_SETTINGS \
469 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
470 "ethprime=TSEC1\0" \
471 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
472 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
473 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
474 " +${filesize}; " \
475 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
476 " +${filesize}; " \
477 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
478 " ${filesize}; " \
479 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
480 " +${filesize}; " \
481 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
482 " ${filesize}\0" \
483 "console=ttyS0\0" \
484 "fdtaddr=0x780000\0" \
485 "kernel_addr=ff800000\0" \
486 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
487 "setbootargs=setenv bootargs " \
488 "root=${rootdev} rw console=${console}," \
489 "${baudrate} ${othbootargs}\0" \
490 "setipargs=setenv bootargs root=${rootdev} rw " \
491 "nfsroot=${serverip}:${rootpath} " \
492 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
493 "${netmask}:${hostname}:${netdev}:off " \
494 "console=${console},${baudrate} ${othbootargs}\0" \
495 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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496 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
497 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
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498 "\0"
499
500#define CONFIG_NFSBOOTCOMMAND \
501 "setenv rootdev /dev/nfs;" \
502 "run setipargs;run addmtd;" \
503 "tftp ${loadaddr} ${bootfile};" \
504 "tftp ${fdtaddr} ${fdtfile};" \
505 "fdt addr ${fdtaddr};" \
506 "bootm ${loadaddr} - ${fdtaddr}"
507
508/* UBI Support */
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509#define CONFIG_MTD_PARTITIONS
510
511/* bootcount support */
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512#define CONFIG_BOOTCOUNT_ALEN 1
513#define CONFIG_SYS_BOOTCOUNT_ADDR 0x9
514
d835e91d 515#define CONFIG_IMAGE_FORMAT_LEGACY
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516
517#endif /* __CONFIG_H */