[people/ms/u-boot.git] / include / configs / inka4x0.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
#define CONFIG_INKA4X0		1	/* INKA4x0 board			*/

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

#define CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/

#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_SYS_XLB_PIPELINING	1

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB


#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */

#if (TEXT_BASE == 0xFFE00000)		/* Boot low */
#   define CONFIG_SYS_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_ETHADDR		00:a0:a4:03:00:00
#define	CONFIG_OVERWRITE_ETHADDR_ONCE

#define	CONFIG_IPADDR		192.168.100.2
#define	CONFIG_SERVERIP		192.168.100.1
#define	CONFIG_NETMASK		255.255.255.0
#define HOSTNAME		inka4x0
#define CONFIG_BOOTFILE		/tftpboot/inka4x0/uImage
#define	CONFIG_ROOTPATH		/opt/eldk/ppc_6xx

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addcons=setenv bootargs ${bootargs} "				\
		"console=ttyS0,${baudrate}\0"				\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp 200000 ${bootfile};"				\
		"run nfsargs addip addcons;bootm\0"			\
	"enable_disp=mw.l 100000 04000000 1;"				\
		"cp.l 100000 f0000b20 1;"				\
		"cp.l 100000 f0000b28 1\0"				\
	"ideargs=setenv bootargs root=/dev/hda1 rw\0"			\
	"ide_boot=ext2load ide 0:1 200000 uImage;"			\
		"run ideargs addip addcons enable_disp;bootm\0"		\
	"brightness=255\0"						\
	""

#define CONFIG_BOOTCOMMAND	"run ide_boot"

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1
#define CONFIG_SYS_FLASH_BASE		0xffe00000
#define CONFIG_SYS_FLASH_SIZE		0x00200000
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/*
 * SDRAM controller configuration
 */
#undef CONFIG_SDR_MT48LC16M16A2
#undef CONFIG_DDR_MT46V16M16
#undef CONFIG_DDR_MT46V32M16
#undef CONFIG_DDR_HYB25D512160BF
#define CONFIG_DDR_K4H511638C

/* Use ON-Chip SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
#else
#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
#endif


#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_MII

/*
 * GPIO configuration
 *
 * use CS1 as gpio_wkup_6 output
 *	Bit 0 (mask: 0x80000000): 0
 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 *	00 -> No Alternatives, I2C1 is used for onboard EEPROM
 *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 *	      EEPROM
 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
 *	011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x01001004

/*
 * RTC configuration
 */
#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/* Enable an alternate, more extensive memory test */
#define CONFIG_SYS_ALT_MEMTEST

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

/*
 * Enable loopw command.
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE
#else
#define CONFIG_SYS_HID0_INIT		0
#define CONFIG_SYS_HID0_FINAL		0
#endif

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00087800 /* for pci_clk  = 66 MHz */
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

/* 32Mbit SRAM @0x30000000 */
#define CONFIG_SYS_CS1_START		0x30000000
#define CONFIG_SYS_CS1_SIZE		0x00400000
#define CONFIG_SYS_CS1_CFG		0x31800 /* for pci_clk = 33 MHz */

/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
#define CONFIG_SYS_CS2_START		0x80000000
#define CONFIG_SYS_CS2_SIZE		0x0001000
#define CONFIG_SYS_CS2_CFG		0x21800  /* for pci_clk = 33 MHz */

/* GPIO in @0x30400000 */
#define CONFIG_SYS_CS3_START		0x30400000
#define CONFIG_SYS_CS3_SIZE		0x00100000
#define CONFIG_SYS_CS3_CFG		0x31800 /* for pci_clk = 33 MHz */

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_OHCI
#define CONFIG_USB_CLOCK	0x00015555
#define CONFIG_USB_CONFIG	0x00001000
#define CONFIG_USB_STORAGE

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0060	/* Offset for data I/O		*/
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x005C	/* Offset for alternate registers */
#define CONFIG_SYS_ATA_STRIDE          4	/* Interval between registers	*/

#define CONFIG_ATAPI            1

#define CONFIG_SYS_BRIGHTNESS          0xFF	/* LCD Default Brightness (255 = off) */

#endif /* __CONFIG_H */
Commit	Line	Data
138ff60c	1	/*
414eec35	2	* (C) Copyright 2003-2005
138ff60c WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
151ab83a WD	32	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	33	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	34	#define CONFIG_INKA4X0 1 /* INKA4x0 board */
138ff60c	35
6d0f6bcf	36	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
138ff60c	37
151ab83a WD	38	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
151ab83a WD	39	#define BOOTFLAG_WARM 0x02 /* Software reboot */
138ff60c	40
151ab83a WD	41	#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
151ab83a WD	42
31d82672 BB	43	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	44
138ff60c WD	45	/*
	46	* Serial console configuration
	47	*/
151ab83a WD	48	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
151ab83a WD	49	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	50	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
138ff60c	51
436be29c WD	52	/*
	53	* PCI Mapping:
	54	* 0x40000000 - 0x4fffffff - PCI Memory
	55	* 0x50000000 - 0x50ffffff - PCI IO Space
	56	*/
	57	#define CONFIG_PCI 1
	58	#define CONFIG_PCI_PNP 1
	59	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	60	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
436be29c WD	61
	62	#define CONFIG_PCI_MEM_BUS 0x40000000
	63	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	64	#define CONFIG_PCI_MEM_SIZE 0x10000000
	65
	66	#define CONFIG_PCI_IO_BUS 0x50000000
	67	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	68	#define CONFIG_PCI_IO_SIZE 0x01000000
	69
6d0f6bcf	70	#define CONFIG_SYS_XLB_PIPELINING 1
436be29c WD	71
	72	/* Partitions */
	73	#define CONFIG_MAC_PARTITION
	74	#define CONFIG_DOS_PARTITION
	75	#define CONFIG_ISO_PARTITION
	76
1d2c6bc4	77
7f5c0157 JL	78	/*
	79	* BOOTP options
	80	*/
	81	#define CONFIG_BOOTP_BOOTFILESIZE
	82	#define CONFIG_BOOTP_BOOTPATH
	83	#define CONFIG_BOOTP_GATEWAY
	84	#define CONFIG_BOOTP_HOSTNAME
	85
	86
138ff60c	87	/*
1d2c6bc4	88	* Command line configuration.
138ff60c	89	*/
1d2c6bc4 JL	90	#include <config_cmd_default.h>
	91
	92	#define CONFIG_CMD_DHCP
	93	#define CONFIG_CMD_EXT2
	94	#define CONFIG_CMD_FAT
	95	#define CONFIG_CMD_IDE
	96	#define CONFIG_CMD_NFS
	97	#define CONFIG_CMD_PCI
	98	#define CONFIG_CMD_SNTP
	99	#define CONFIG_CMD_USB
	100
138ff60c	101
b05dcb58 WD	102	#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
b05dcb58 WD	103
138ff60c	104	#if (TEXT_BASE == 0xFFE00000) /* Boot low */
6d0f6bcf	105	# define CONFIG_SYS_LOWBOOT 1
138ff60c WD	106	#endif
	107
	108	/*
	109	* Autobooting
	110	*/
84e106c0	111	#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
138ff60c WD	112
138ff60c WD	113	#define CONFIG_PREBOOT "echo;" \
32bf3d14	114	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
138ff60c WD	115	"echo"
	116
	117	#undef CONFIG_BOOTARGS
	118
84e106c0 WD	119	#define CONFIG_ETHADDR 00:a0:a4:03:00:00
	120	#define CONFIG_OVERWRITE_ETHADDR_ONCE
	121
	122	#define CONFIG_IPADDR 192.168.100.2
	123	#define CONFIG_SERVERIP 192.168.100.1
	124	#define CONFIG_NETMASK 255.255.255.0
	125	#define HOSTNAME inka4x0
	126	#define CONFIG_BOOTFILE /tftpboot/inka4x0/uImage
	127	#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
	128
138ff60c WD	129	#define CONFIG_EXTRA_ENV_SETTINGS \
	130	"netdev=eth0\0" \
	131	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	132	"nfsroot=${serverip}:${rootpath}\0" \
138ff60c	133	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	134	"addip=setenv bootargs ${bootargs} " \
	135	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	136	":${hostname}:${netdev}:off panic=1\0" \
84e106c0 WD	137	"addcons=setenv bootargs ${bootargs} " \
	138	"console=ttyS0,${baudrate}\0" \
	139	"flash_nfs=run nfsargs addip addcons;" \
fe126d8b	140	"bootm ${kernel_addr}\0" \
84e106c0 WD	141	"net_nfs=tftp 200000 ${bootfile};" \
	142	"run nfsargs addip addcons;bootm\0" \
	143	"enable_disp=mw.l 100000 04000000 1;" \
	144	"cp.l 100000 f0000b20 1;" \
	145	"cp.l 100000 f0000b28 1\0" \
	146	"ideargs=setenv bootargs root=/dev/hda1 rw\0" \
	147	"ide_boot=ext2load ide 0:1 200000 uImage;" \
f23cb34c	148	"run ideargs addip addcons enable_disp;bootm\0" \
84e106c0	149	"brightness=255\0" \
138ff60c WD	150	""
138ff60c WD	151
84e106c0	152	#define CONFIG_BOOTCOMMAND "run ide_boot"
138ff60c WD	153
	154	/*
	155	* IPB Bus clocking configuration.
	156	*/
6d0f6bcf	157	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
138ff60c WD	158
	159	/*
	160	* Flash configuration
	161	*/
6d0f6bcf	162	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	163	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	164	#define CONFIG_SYS_FLASH_BASE 0xffe00000
	165	#define CONFIG_SYS_FLASH_SIZE 0x00200000
	166	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	167	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	168	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
	169	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
138ff60c WD	170
	171	/*
	172	* Environment settings
	173	*/
5a1aceb0	174	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	175	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
0e8d1586 JCPV	176	#define CONFIG_ENV_SIZE 0x2000
0e8d1586 JCPV	177	#define CONFIG_ENV_SECT_SIZE 0x2000
138ff60c	178	#define CONFIG_ENV_OVERWRITE 1
6d0f6bcf	179	#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
138ff60c WD	180
	181	/*
	182	* Memory map
	183	*/
6d0f6bcf JCPV	184	#define CONFIG_SYS_MBAR 0xF0000000
	185	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	186	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
138ff60c	187
5fb6d719 MB	188	/*
	189	* SDRAM controller configuration
	190	*/
	191	#undef CONFIG_SDR_MT48LC16M16A2
	192	#undef CONFIG_DDR_MT46V16M16
	193	#undef CONFIG_DDR_MT46V32M16
	194	#undef CONFIG_DDR_HYB25D512160BF
	195	#define CONFIG_DDR_K4H511638C
138ff60c WD	196
138ff60c WD	197	/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf	198	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
138ff60c WD	199	#ifdef CONFIG_POST
138ff60c WD	200	/* preserve space for the post_word at end of on-chip SRAM */
6d0f6bcf	201	#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
138ff60c	202	#else
6d0f6bcf	203	#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
138ff60c WD	204	#endif
	205
	206
6d0f6bcf JCPV	207	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	208	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	209	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
138ff60c	210
6d0f6bcf JCPV	211	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	212	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	213	# define CONFIG_SYS_RAMBOOT 1
138ff60c WD	214	#endif
138ff60c WD	215
6d0f6bcf JCPV	216	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	217	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	218	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
138ff60c WD	219
	220	/*
	221	* Ethernet configuration
	222	*/
	223	#define CONFIG_MPC5xxx_FEC 1
	224	/*
	225	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	226	*/
	227	/* #define CONFIG_FEC_10MBIT 1 */
	228	#define CONFIG_PHY_ADDR 0x00
84e106c0	229	#define CONFIG_MII
138ff60c WD	230
	231	/*
	232	* GPIO configuration
	233	*
9f709b6c WD	234	* use CS1 as gpio_wkup_6 output
9f709b6c WD	235	* Bit 0 (mask: 0x80000000): 0
138ff60c WD	236	* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
	237	* 00 -> No Alternatives, I2C1 is used for onboard EEPROM
	238	* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
	239	* EEPROM
	240	* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
	241	* use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
	242	* 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
138ff60c	243	*/
6d0f6bcf	244	#define CONFIG_SYS_GPS_PORT_CONFIG 0x01001004
138ff60c WD	245
	246	/*
	247	* RTC configuration
	248	*/
	249	#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
	250
	251	/*
	252	* Miscellaneous configurable options
	253	*/
6d0f6bcf JCPV	254	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	255	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
1d2c6bc4	256	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	257	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
138ff60c	258	#else
6d0f6bcf	259	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
138ff60c	260	#endif
6d0f6bcf JCPV	261	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	262	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	263	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
138ff60c	264
6d0f6bcf	265	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
1d2c6bc4	266	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	267	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
1d2c6bc4 JL	268	#endif
1d2c6bc4 JL	269
138ff60c	270	/* Enable an alternate, more extensive memory test */
6d0f6bcf	271	#define CONFIG_SYS_ALT_MEMTEST
138ff60c	272
6d0f6bcf JCPV	273	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	274	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
138ff60c	275
6d0f6bcf	276	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
138ff60c	277
6d0f6bcf	278	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
138ff60c WD	279
138ff60c WD	280	/*
7f5c0157	281	* Enable loopw command.
138ff60c WD	282	*/
	283	#define CONFIG_LOOPW
	284
	285	/*
	286	* Various low-level settings
	287	*/
	288	#if defined(CONFIG_MPC5200)
6d0f6bcf JCPV	289	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	290	#define CONFIG_SYS_HID0_FINAL HID0_ICE
138ff60c	291	#else
6d0f6bcf JCPV	292	#define CONFIG_SYS_HID0_INIT 0
6d0f6bcf JCPV	293	#define CONFIG_SYS_HID0_FINAL 0
138ff60c WD	294	#endif
138ff60c WD	295
6d0f6bcf JCPV	296	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	297	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	298	#define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
	299	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	300	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
138ff60c	301
e58cf2a0	302	/* 32Mbit SRAM @0x30000000 */
6d0f6bcf JCPV	303	#define CONFIG_SYS_CS1_START 0x30000000
	304	#define CONFIG_SYS_CS1_SIZE 0x00400000
	305	#define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */
e58cf2a0 WD	306
e58cf2a0 WD	307	/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
6d0f6bcf JCPV	308	#define CONFIG_SYS_CS2_START 0x80000000
	309	#define CONFIG_SYS_CS2_SIZE 0x0001000
	310	#define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
e58cf2a0	311
f4733a07	312	/* GPIO in @0x30400000 */
6d0f6bcf JCPV	313	#define CONFIG_SYS_CS3_START 0x30400000
	314	#define CONFIG_SYS_CS3_SIZE 0x00100000
	315	#define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
f4733a07	316
6d0f6bcf JCPV	317	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	318	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
138ff60c	319
436be29c WD	320	/*-----------------------------------------------------------------------
	321	* USB stuff
	322	*-----------------------------------------------------------------------
	323	*/
	324	#define CONFIG_USB_OHCI
151ab83a WD	325	#define CONFIG_USB_CLOCK 0x00015555
151ab83a WD	326	#define CONFIG_USB_CONFIG 0x00001000
1968e615	327	#define CONFIG_USB_STORAGE
436be29c	328
b05dcb58 WD	329	/*-----------------------------------------------------------------------
	330	* IDE/ATA stuff Supports IDE harddisk
	331	*-----------------------------------------------------------------------
	332	*/
	333
	334	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	335
	336	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	337	#undef CONFIG_IDE_LED /* LED for ide not supported */
	338
	339	#define CONFIG_IDE_RESET /* reset for ide supported */
	340	#define CONFIG_IDE_PREINIT
	341
6d0f6bcf JCPV	342	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	343	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
b05dcb58	344
6d0f6bcf JCPV	345	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	346	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
	347	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */
	348	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
	349	#define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */
	350	#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
b05dcb58 WD	351
b05dcb58 WD	352	#define CONFIG_ATAPI 1
1806c759	353
6d0f6bcf	354	#define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */
b05dcb58	355
138ff60c	356	#endif /* __CONFIG_H */