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[people/ms/u-boot.git] / include / configs / innokom.h
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43d9616c
WD		 1/*
2 * (C) Copyright 2000, 2001, 2002
3 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
4 *
5 * Configuration for the Auerswald Innokom CPU board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * include/configs/innokom.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33#define DEBUG 1
34
35/*
36 * If we are developing, we might want to start U-Boot from ram
37 * so we MUST NOT initialize critical regs like mem-timing ...
38 */
39#define CONFIG_INIT_CRITICAL /* undef for developing */
40
41/*
42 * High Level Configuration Options
43 * (easy to change)
44 */
45#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
46#define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */
47
48#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
49 /* for timer/console/ethernet */
50/*
51 * Hardware drivers
52 */
53
54/*
55 * select serial console configuration
56 */
57#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
58
59/* allow to overwrite serial and ethaddr */
60#define CONFIG_ENV_OVERWRITE
61
62#define CONFIG_BAUDRATE 19200
63
64#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_I2C | CFG_CMD_EEPROM) & ~CFG_CMD_NET)
65
66/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
67#include <cmd_confdefs.h>
68
69#define CONFIG_BOOTDELAY 3
70/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
71#define CONFIG_BOOTARGS "console=ttyS0,19200"
72#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
73#define CONFIG_NETMASK 255.255.255.0
74#define CONFIG_IPADDR 192.168.1.56
75#define CONFIG_SERVERIP 192.168.1.2
76#define CONFIG_BOOTCOMMAND "bootm 0x40000"
77#define CONFIG_SHOW_BOOT_PROGRESS
78
79#define CONFIG_CMDLINE_TAG 1
80
81#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
82#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
83#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
84#endif
85
86/*
87 * Miscellaneous configurable options
88 */
89
90/*
91 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
92 * used for the RAM copy of the uboot code
93 */
94/* #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) */
95#define CFG_MALLOC_LEN (128*1024)
96
97#define CFG_LONGHELP /* undef to save memory */
98#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
99#define CFG_CBSIZE 128 /* Console I/O Buffer Size */
100#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
101#define CFG_MAXARGS 16 /* max number of command args */
102#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
103
104#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
105#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
106
107#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
108
109#define CFG_LOAD_ADDR 0xa7fe0000 /* default load address */
110 /* RS: where is this documented? */
111 /* RS: is this where U-Boot is */
112 /* RS: relocated to in RAM? */
113
114#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
115 /* RS: the oscillator is actually 3680130?? */
116
117#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
118 /* 0101000001 */
119 /* ^^^^^ Memory Speed 99.53 MHz */
120 /* ^^ Run Mode Speed = 2x Mem Speed */
121 /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
122
123#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
124
125 /* valid baudrates */
126#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
127
128/*
129 * I2C bus
130 */
131#define CONFIG_HARD_I2C 1
132#define CFG_I2C_SPEED 50000
133#define CFG_I2C_SLAVE 0xfe
134
135#define CFG_ENV_IS_IN_EEPROM 1
136
137#define CFG_ENV_OFFSET 0x00 /* environment starts here */
138#define CFG_ENV_SIZE 1024 /* 1 KiB */
139#define CFG_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */
140#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
141#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
142#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of address */
143#define CFG_EEPROM_SIZE 4096 /* size in bytes */
144
145/*
146 * Stack sizes
147 *
148 * The stack sizes are set up in start.S using the settings below
149 */
150#define CONFIG_STACKSIZE (128*1024) /* regular stack */
151#ifdef CONFIG_USE_IRQ
152#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
153#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
154#endif
155
156/*
157 * Physical Memory Map
158 */
159#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
160#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
161#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
162
163#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
164#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
165
166#define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */
167#define CFG_DRAM_SIZE 0x04000000
168
169#define CFG_FLASH_BASE PHYS_FLASH_1
170
171/*
172 * GPIO settings;
173 */
174
175/* GP15 == nCS1 is 1
176 * GP24 == SFRM is 1
177 * GP25 == TXD is 1
178 * GP33 == nCS5 is 1
179 * GP39 == FFTXD is 1
180 * GP41 == RTS is 1
181 * GP47 == TXD is 1
182 * GP49 == nPWE is 1
183 * GP62 == LED_B is 1
184 * GP63 == TDM_OE is 1
185 * GP78 == nCS2 is 1
186 * GP79 == nCS3 is 1
187 * GP80 == nCS4 is 1
188 */
189#define CFG_GPSR0_VAL 0x03008000
190#define CFG_GPSR1_VAL 0xC0028282
191#define CFG_GPSR2_VAL 0x0001C000
192
193/* GP02 == DON_RST is 0
194 * GP23 == SCLK is 0
195 * GP45 == USB_ACT is 0
196 * GP60 == PLLEN is 0
197 * GP61 == LED_A is 0
198 * GP73 == SWUPD_LED is 0
199 */
200#define CFG_GPCR0_VAL 0x00800004
201#define CFG_GPCR1_VAL 0x30002000
202#define CFG_GPCR2_VAL 0x00000100
203
204/* GP00 == DON_READY is input
205 * GP01 == DON_OK is input
206 * GP02 == DON_RST is output
207 * GP03 == RESET_IND is input
208 * GP07 == RES11 is input
209 * GP09 == RES12 is input
210 * GP11 == SWUPDATE is input
211 * GP14 == nPOWEROK is input
212 * GP15 == nCS1 is output
213 * GP17 == RES22 is input
214 * GP18 == RDY is input
215 * GP23 == SCLK is output
216 * GP24 == SFRM is output
217 * GP25 == TXD is output
218 * GP26 == RXD is input
219 * GP32 == RES21 is input
220 * GP33 == nCS5 is output
221 * GP34 == FFRXD is input
222 * GP35 == CTS is input
223 * GP39 == FFTXD is output
224 * GP41 == RTS is output
225 * GP42 == USB_OK is input
226 * GP45 == USB_ACT is output
227 * GP46 == RXD is input
228 * GP47 == TXD is output
229 * GP49 == nPWE is output
230 * GP58 == nCPUBUSINT is input
231 * GP59 == LANINT is input
232 * GP60 == PLLEN is output
233 * GP61 == LED_A is output
234 * GP62 == LED_B is output
235 * GP63 == TDM_OE is output
236 * GP64 == nDSPINT is input
237 * GP65 == STRAP0 is input
238 * GP67 == STRAP1 is input
239 * GP69 == STRAP2 is input
240 * GP70 == STRAP3 is input
241 * GP71 == STRAP4 is input
242 * GP73 == SWUPD_LED is output
243 * GP78 == nCS2 is output
244 * GP79 == nCS3 is output
245 * GP80 == nCS4 is output
246 */
247#define CFG_GPDR0_VAL 0x03808004
248#define CFG_GPDR1_VAL 0xF002A282
249#define CFG_GPDR2_VAL 0x0001C200
250
251/* GP15 == nCS1 is AF10
252 * GP18 == RDY is AF01
253 * GP23 == SCLK is AF10
254 * GP24 == SFRM is AF10
255 * GP25 == TXD is AF10
256 * GP26 == RXD is AF01
257 * GP33 == nCS5 is AF10
258 * GP34 == FFRXD is AF01
259 * GP35 == CTS is AF01
260 * GP39 == FFTXD is AF10
261 * GP41 == RTS is AF10
262 * GP46 == RXD is AF10
263 * GP47 == TXD is AF01
264 * GP49 == nPWE is AF10
265 * GP78 == nCS2 is AF10
266 * GP79 == nCS3 is AF10
267 * GP80 == nCS4 is AF10
268 */
269#define CFG_GAFR0_L_VAL 0x80000000
270#define CFG_GAFR0_U_VAL 0x001A8010
271#define CFG_GAFR1_L_VAL 0x60088058
272#define CFG_GAFR1_U_VAL 0x00000008
273#define CFG_GAFR2_L_VAL 0xA0000000
274#define CFG_GAFR2_U_VAL 0x00000002
275
276/* FIXME: set GPIO_RER/FER */
277
278/* RDH = 1
279 * PH = 1
280 * VFS = 1
281 * BFS = 1
282 * SSS = 1
283 */
284#define CFG_PSSR_VAL 0x37
285
286/*
287 * Memory settings
288 */
289
290/* This is the configuration for nCS0/1 -> flash banks
291 * configuration for nCS1:
292 * [31] 0 - Slower Device
293 * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
294 * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
295 * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
296 * [19] 1 - 16 Bit bus width
297 * [18:16] 000 - nonburst RAM or FLASH
298 * configuration for nCS0:
299 * [15] 0 - Slower Device
300 * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
301 * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
302 * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
303 * [03] 1 - 16 Bit bus width
304 * [02:00] 000 - nonburst RAM or FLASH
305 */
306#define CFG_MSC0_VAL 0x25b825b8 /* flash banks */
307
308/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
309 * configuration for nCS3: DSP
310 * [31] 0 - Slower Device
311 * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
312 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
313 * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
314 * [19] 1 - 16 Bit bus width
315 * [18:16] 100 - variable latency I/O
316 * configuration for nCS2: TDM-Switch
317 * [15] 0 - Slower Device
318 * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
319 * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
320 * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
321 * [03] 1 - 16 Bit bus width
322 * [02:00] 100 - variable latency I/O
323 */
324#define CFG_MSC1_VAL 0x132C593C /* TDM switch, DSP */
325
326/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
327 *
328 * configuration for nCS5: LAN Controller
329 * [31] 0 - Slower Device
330 * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
331 * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
332 * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
333 * [19] 1 - 16 Bit bus width
334 * [18:16] 100 - variable latency I/O
335 * configuration for nCS4: ExtBus
336 * [15] 0 - Slower Device
337 * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
338 * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
339 * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
340 * [03] 1 - 16 Bit bus width
341 * [02:00] 100 - variable latency I/O
342 */
343#define CFG_MSC2_VAL 0x132C6CDC /* extra bus, LAN controller */
344
345/* MDCNFG: SDRAM Configuration Register
346 *
347 * [31:29] 000 - reserved
348 * [28] 0 - no SA1111 compatiblity mode
349 * [27] 0 - latch return data with return clock
350 * [26] 0 - alternate addressing for pair 2/3
351 * [25:24] 00 - timings
352 * [23] 0 - internal banks in lower partition 2/3 (not used)
353 * [22:21] 00 - row address bits for partition 2/3 (not used)
354 * [20:19] 00 - column address bits for partition 2/3 (not used)
355 * [18] 0 - SDRAM partition 2/3 width is 32 bit
356 * [17] 0 - SDRAM partition 3 disabled
357 * [16] 0 - SDRAM partition 2 disabled
358 * [15:13] 000 - reserved
359 * [12] 1 - SA1111 compatiblity mode
360 * [11] 1 - latch return data with return clock
361 * [10] 0 - no alternate addressing for pair 0/1
362 * [09:08] 01 - tRP=2*MemClk; CL=2; tRCD=2*MemClk; tRAS=5*MemClk; tRC=8*MemClk
363 * [7] 1 - 4 internal banks in lower partition pair
364 * [06:05] 10 - 13 row address bits for partition 0/1
365 * [04:03] 01 - 9 column address bits for partition 0/1
366 * [02] 0 - SDRAM partition 0/1 width is 32 bit
367 * [01] 0 - disable SDRAM partition 1
368 * [00] 1 - enable SDRAM partition 0
369 *
370 * use the configuration above but disable partition 0
371 */
372#define CFG_MDCNFG_VAL 0x000019c8
373
374/* MDREFR: SDRAM Refresh Control Register
375 *
376 * [32:26] 0 - reserved
377 * [25] 0 - K2FREE: not free running
378 * [24] 0 - K1FREE: not free running
379 * [23] 0 - K0FREE: not free running
380 * [22] 0 - SLFRSH: self refresh disabled
381 * [21] 0 - reserved
382 * [20] 0 - APD: no auto power down
383 * [19] 0 - K2DB2: SDCLK2 is MemClk
384 * [18] 0 - K2RUN: disable SDCLK2
385 * [17] 0 - K1DB2: SDCLK1 is MemClk
386 * [16] 1 - K1RUN: enable SDCLK1
387 * [15] 1 - E1PIN: SDRAM clock enable
388 * [14] 1 - K0DB2: SDCLK0 is MemClk
389 * [13] 1 - K0RUN: disable SDCLK0
390 * [12] 1 - E0PIN: disable SDCKE0
391 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
392 */
393#define CFG_MDREFR_VAL 0x0001F018
394
395/* MDMRS: Mode Register Set Configuration Register
396 *
397 * [31] 0 - reserved
398 * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
399 * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
400 * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
401 * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
402 * [15] 0 - reserved
403 * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
404 * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
405 * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
406 * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
407 */
408#define CFG_MDMRS_VAL 0x00020022
409
410/*
411 * PCMCIA and CF Interfaces
412 */
413#define CFG_MECR_VAL 0x00000000
414#define CFG_MCMEM0_VAL 0x00000000
415#define CFG_MCMEM1_VAL 0x00000000
416#define CFG_MCATT0_VAL 0x00000000
417#define CFG_MCATT1_VAL 0x00000000
418#define CFG_MCIO0_VAL 0x00000000
419#define CFG_MCIO1_VAL 0x00000000
420
421/*
422#define CSB226_USER_LED0 0x00000008
423#define CSB226_USER_LED1 0x00000010
424#define CSB226_USER_LED2 0x00000020
425*/
426
427/*
428 * FLASH and environment organization
429 */
430#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
431#define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
432
433/* timeout values are in ticks */
434#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
435#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
436
437#if 0
438#define CFG_ENV_IS_IN_FLASH 1
439#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000)
440 /* Addr of Environment Sector */
441#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
442#endif
443
444#endif /* __CONFIG_H */
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