[people/ms/u-boot.git] / include / configs / innokom.h

/*
 * (C) Copyright 2000, 2001, 2002
 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
 *
 * Configuration for the Auerswald Innokom CPU board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * include/configs/innokom.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_PXA250 		1	/* This is an PXA250 CPU            */
#define CONFIG_INNOKOM		1	/* on an Auerswald Innokom board    */

#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
					/* for timer/console/ethernet       */
/*
 * Hardware drivers
 */

/*
 * select serial console configuration
 */
#define CONFIG_FFUART		1	/* we use FFUART on CSB226 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		19200
#define CONFIG_MISC_INIT_R	1	/* we have a misc_init_r() function */


/*
 * Command line configuration.
 */

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BDI
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMI
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_RUN


#define CONFIG_BOOTDELAY	3
/* #define CONFIG_BOOTARGS	"root=/dev/nfs ip=bootp console=ttyS0,19200" */
#define CONFIG_BOOTARGS		"console=ttyS0,19200"
#define CONFIG_ETHADDR		FF:FF:FF:FF:FF:FF
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		192.168.1.56
#define CONFIG_SERVERIP		192.168.1.2
#define CONFIG_BOOTCOMMAND	"bootm 0x40000"
#define CONFIG_SHOW_BOOT_PROGRESS

#define CONFIG_CMDLINE_TAG	1

/*
 * Miscellaneous configurable options
 */

/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN		(256*1024)
#define CFG_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */

#define CFG_LONGHELP				/* undef to save memory         */
#define CFG_PROMPT		"uboot> "	/* Monitor Command Prompt       */
#define CFG_CBSIZE		256		/* Console I/O Buffer Size      */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args   */
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */

#define CFG_MEMTEST_START	0xa0400000      /* memtest works on     */
#define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */

#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */

#define CFG_LOAD_ADDR           0xa3000000      /* load kernel to this address   */

#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
						/* RS: the oscillator is actually 3680130?? */

#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
						/* 0101000001 */
						/*      ^^^^^ Memory Speed 99.53 MHz         */
						/*    ^^      Run Mode Speed = 2x Mem Speed  */
						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */

#define CFG_MONITOR_LEN		0x20000		/* 128 KiB */

						/* valid baudrates */
#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }

/*
 * I2C bus
 */
#define CONFIG_HARD_I2C 		1
#define CFG_I2C_SPEED 			50000
#define CFG_I2C_SLAVE 			0xfe

#define CFG_ENV_IS_IN_EEPROM 		1

#define CFG_ENV_OFFSET			0x00	/* environment starts here  */
#define CFG_ENV_SIZE			1024	/* 1 KiB                    */
#define CFG_I2C_EEPROM_ADDR		0x50	/* A0 = 0 (hardwired)       */
#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets       */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	15	/* between stop and start   */
#define CFG_I2C_EEPROM_ADDR_LEN		2	/* length of address        */
#define CFG_EEPROM_SIZE			4096	/* size in bytes            */
#define CFG_I2C_INIT_BOARD		1	/* board has it's own init  */

/*
 * SMSC91C111 Network Card
 */
#define CONFIG_DRIVER_SMC91111		1
#define CONFIG_SMC91111_BASE		0x14000000 /* chip select 5         */
#undef  CONFIG_SMC_USE_32_BIT		           /* 16 bit bus access     */
#undef  CONFIG_SMC_91111_EXT_PHY		   /* we use internal phy   */
#define CONFIG_SMC_AUTONEG_TIMEOUT	10	   /* timeout 10 seconds    */
#undef  CONFIG_SHOW_ACTIVITY
#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */

/*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
#ifdef  CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
#endif

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM   */
#define PHYS_SDRAM_1		0xa0000000	/* SDRAM Bank #1            */
#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB                    */

#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1            */
#define PHYS_FLASH_SIZE		0x01000000	/* 16 MB                    */

#define CFG_DRAM_BASE		0xa0000000	/* RAM starts here          */
#define CFG_DRAM_SIZE		0x04000000

#define CFG_FLASH_BASE          PHYS_FLASH_1

/*
 * JFFS2 partitions
 *
 */
/* development flash */
#define CONFIG_MTD_INNOKOM_16MB	1
#undef CONFIG_MTD_INNOKOM_64MB

/* production flash */
/*
#define CONFIG_MTD_INNOKOM_64MB	1
#undef CONFIG_MTD_INNOKOM_16MB
*/

/* No command line, one static partition, whole device */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=innokom-0"
*/

/* development flash */
/*
#define MTDPARTS_DEFAULT	"mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
*/

/* production flash */
/*
#define MTDPARTS_DEFAULT	"mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
*/

/*
 * GPIO settings
 *
 * GP15 == nCS1      is 1
 * GP24 == SFRM      is 1
 * GP25 == TXD       is 1
 * GP33 == nCS5      is 1
 * GP39 == FFTXD     is 1
 * GP41 == RTS       is 1
 * GP47 == TXD       is 1
 * GP49 == nPWE      is 1
 * GP62 == LED_B     is 1
 * GP63 == TDM_OE    is 1
 * GP78 == nCS2      is 1
 * GP79 == nCS3      is 1
 * GP80 == nCS4      is 1
 */
#define CFG_GPSR0_VAL       0x03008000
#define CFG_GPSR1_VAL       0xC0028282
#define CFG_GPSR2_VAL       0x0001C000

/* GP02 == DON_RST   is 0
 * GP23 == SCLK      is 0
 * GP45 == USB_ACT   is 0
 * GP60 == PLLEN     is 0
 * GP61 == LED_A     is 0
 * GP73 == SWUPD_LED is 0
 */
#define CFG_GPCR0_VAL       0x00800004
#define CFG_GPCR1_VAL       0x30002000
#define CFG_GPCR2_VAL       0x00000100

/* GP00 == DON_READY is input
 * GP01 == DON_OK    is input
 * GP02 == DON_RST   is output
 * GP03 == RESET_IND is input
 * GP07 == RES11     is input
 * GP09 == RES12     is input
 * GP11 == SWUPDATE  is input
 * GP14 == nPOWEROK  is input
 * GP15 == nCS1      is output
 * GP17 == RES22     is input
 * GP18 == RDY       is input
 * GP23 == SCLK      is output
 * GP24 == SFRM      is output
 * GP25 == TXD       is output
 * GP26 == RXD       is input
 * GP32 == RES21     is input
 * GP33 == nCS5      is output
 * GP34 == FFRXD     is input
 * GP35 == CTS       is input
 * GP39 == FFTXD     is output
 * GP41 == RTS       is output
 * GP42 == USB_OK    is input
 * GP45 == USB_ACT   is output
 * GP46 == RXD       is input
 * GP47 == TXD       is output
 * GP49 == nPWE      is output
 * GP58 == nCPUBUSINT is input
 * GP59 == LANINT    is input
 * GP60 == PLLEN     is output
 * GP61 == LED_A     is output
 * GP62 == LED_B     is output
 * GP63 == TDM_OE    is output
 * GP64 == nDSPINT   is input
 * GP65 == STRAP0    is input
 * GP67 == STRAP1    is input
 * GP69 == STRAP2    is input
 * GP70 == STRAP3    is input
 * GP71 == STRAP4    is input
 * GP73 == SWUPD_LED is output
 * GP78 == nCS2      is output
 * GP79 == nCS3      is output
 * GP80 == nCS4      is output
 */
#define CFG_GPDR0_VAL       0x03808004
#define CFG_GPDR1_VAL       0xF002A282
#define CFG_GPDR2_VAL       0x0001C200

/* GP15 == nCS1  is AF10
 * GP18 == RDY   is AF01
 * GP23 == SCLK  is AF10
 * GP24 == SFRM  is AF10
 * GP25 == TXD   is AF10
 * GP26 == RXD   is AF01
 * GP33 == nCS5  is AF10
 * GP34 == FFRXD is AF01
 * GP35 == CTS   is AF01
 * GP39 == FFTXD is AF10
 * GP41 == RTS   is AF10
 * GP46 == RXD   is AF10
 * GP47 == TXD   is AF01
 * GP49 == nPWE  is AF10
 * GP78 == nCS2  is AF10
 * GP79 == nCS3  is AF10
 * GP80 == nCS4  is AF10
 */
#define CFG_GAFR0_L_VAL     0x80000000
#define CFG_GAFR0_U_VAL     0x001A8010
#define CFG_GAFR1_L_VAL     0x60088058
#define CFG_GAFR1_U_VAL     0x00000008
#define CFG_GAFR2_L_VAL     0xA0000000
#define CFG_GAFR2_U_VAL     0x00000002


/* FIXME: set GPIO_RER/FER */

/* RDH = 1
 * PH  = 1
 * VFS = 1
 * BFS = 1
 * SSS = 1
 */
#define CFG_PSSR_VAL		0x37

/*
 * Memory settings
 *
 * This is the configuration for nCS0/1 -> flash banks
 * configuration for nCS1:
 * [31]    0    - Slower Device
 * [30:28] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
 * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
 * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
 * [19]    1    - 16 Bit bus width
 * [18:16] 000  - nonburst RAM or FLASH
 * configuration for nCS0:
 * [15]    0    - Slower Device
 * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
 * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
 * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
 * [03]    1    - 16 Bit bus width
 * [02:00] 000  - nonburst RAM or FLASH
 */
#define CFG_MSC0_VAL		0x25b825b8 /* flash banks                   */

/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
 * configuration for nCS3: DSP
 * [31]    0    - Slower Device
 * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
 * [19]    1    - 16 Bit bus width
 * [18:16] 100  - variable latency I/O
 * configuration for nCS2: TDM-Switch
 * [15]    0    - Slower Device
 * [14:12] 101  - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
 * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
 * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
 * [03]    1    - 16 Bit bus width
 * [02:00] 100  - variable latency I/O
 */
#define CFG_MSC1_VAL		0x123C593C /* TDM switch, DSP               */

/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
 *
 * configuration for nCS5: LAN Controller
 * [31]    0    - Slower Device
 * [30:28] 001  - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
 * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
 * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
 * [19]    1    - 16 Bit bus width
 * [18:16] 100  - variable latency I/O
 * configuration for nCS4: ExtBus
 * [15]    0    - Slower Device
 * [14:12] 110  - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
 * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
 * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
 * [03]    1    - 16 Bit bus width
 * [02:00] 100  - variable latency I/O
 */
#define CFG_MSC2_VAL		0x123C6CDC /* extra bus, LAN controller     */

/* MDCNFG: SDRAM Configuration Register
 *
 * [31:29]   000 - reserved
 * [28]      0	 - no SA1111 compatiblity mode
 * [27]      0   - latch return data with return clock
 * [26]      0   - alternate addressing for pair 2/3
 * [25:24]   00  - timings
 * [23]      0   - internal banks in lower partition 2/3 (not used)
 * [22:21]   00  - row address bits for partition 2/3 (not used)
 * [20:19]   00  - column address bits for partition 2/3 (not used)
 * [18]      0   - SDRAM partition 2/3 width is 32 bit
 * [17]      0   - SDRAM partition 3 disabled
 * [16]      0   - SDRAM partition 2 disabled
 * [15:13]   000 - reserved
 * [12]      1	 - SA1111 compatiblity mode
 * [11]      1   - latch return data with return clock
 * [10]      0   - no alternate addressing for pair 0/1
 * [09:08]   01  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
 * [7]       1   - 4 internal banks in lower partition pair
 * [06:05]   10  - 13 row address bits for partition 0/1
 * [04:03]   01  - 9 column address bits for partition 0/1
 * [02]      0   - SDRAM partition 0/1 width is 32 bit
 * [01]      0   - disable SDRAM partition 1
 * [00]      1   - enable  SDRAM partition 0
 */
/* use the configuration above but disable partition 0 */
#define CFG_MDCNFG_VAL		0x000019c8

/* MDREFR: SDRAM Refresh Control Register
 *
 * [32:26] 0     - reserved
 * [25]    0     - K2FREE: not free running
 * [24]    0     - K1FREE: not free running
 * [23]    1     - K0FREE: not free running
 * [22]    0     - SLFRSH: self refresh disabled
 * [21]    0     - reserved
 * [20]    0     - APD: no auto power down
 * [19]    0     - K2DB2: SDCLK2 is MemClk
 * [18]    0     - K2RUN: disable SDCLK2
 * [17]    0     - K1DB2: SDCLK1 is MemClk
 * [16]    1     - K1RUN: enable SDCLK1
 * [15]    1     - E1PIN: SDRAM clock enable
 * [14]    1     - K0DB2: SDCLK0 is MemClk
 * [13]    0     - K0RUN: disable SDCLK0
 * [12]    1     - E0PIN: disable SDCKE0
 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
 */
#define CFG_MDREFR_VAL		0x0081D018

/* MDMRS: Mode Register Set Configuration Register
 *
 * [31]      0       - reserved
 * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
 * [22:20]   000     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
 * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
 * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
 * [15]      0       - reserved
 * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
 * [06:04]   010     - MDCL0:  SDRAM0/1 Cas Latency.
 * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
 * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
 */
#define CFG_MDMRS_VAL		0x00020022

/*
 * PCMCIA and CF Interfaces
 */
#define CFG_MECR_VAL		0x00000000
#define CFG_MCMEM0_VAL		0x00000000
#define CFG_MCMEM1_VAL		0x00000000
#define CFG_MCATT0_VAL		0x00000000
#define CFG_MCATT1_VAL		0x00000000
#define CFG_MCIO0_VAL		0x00000000
#define CFG_MCIO1_VAL		0x00000000

/*
#define CSB226_USER_LED0	0x00000008
#define CSB226_USER_LED1	0x00000010
#define CSB226_USER_LED2	0x00000020
*/

/*
 * FLASH and environment organization
 */
#define CFG_MAX_FLASH_BANKS     1	/* max number of memory banks       */
#define CFG_MAX_FLASH_SECT	128	/* max number of sect. on one chip  */

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase       */
#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write       */

#endif  /* __CONFIG_H */
Commit	Line	Data
43d9616c WD	1	/*
	2	* (C) Copyright 2000, 2001, 2002
	3	* Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
	4	*
	5	* Configuration for the Auerswald Innokom CPU board.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/*
	27	* include/configs/innokom.h - configuration options, board specific
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32
43d9616c WD	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37	#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
	38	#define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */
	39
	40	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	41	/* for timer/console/ethernet */
	42	/*
	43	* Hardware drivers
	44	*/
	45
	46	/*
	47	* select serial console configuration
	48	*/
	49	#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
	50
	51	/* allow to overwrite serial and ethaddr */
	52	#define CONFIG_ENV_OVERWRITE
	53
	54	#define CONFIG_BAUDRATE 19200
06d01dbe	55	#define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */
43d9616c	56
1d2c6bc4 JL	57
	58	/*
	59	* Command line configuration.
	60	*/
	61
	62	#define CONFIG_CMD_ASKENV
	63	#define CONFIG_CMD_BDI
	64	#define CONFIG_CMD_CACHE
	65	#define CONFIG_CMD_DHCP
	66	#define CONFIG_CMD_ECHO
	67	#define CONFIG_CMD_ENV
	68	#define CONFIG_CMD_FLASH
	69	#define CONFIG_CMD_I2C
	70	#define CONFIG_CMD_IMI
	71	#define CONFIG_CMD_LOADB
	72	#define CONFIG_CMD_MEMORY
	73	#define CONFIG_CMD_NET
	74	#define CONFIG_CMD_RUN
	75
43d9616c WD	76
	77	#define CONFIG_BOOTDELAY 3
	78	/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
	79	#define CONFIG_BOOTARGS "console=ttyS0,19200"
	80	#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
	81	#define CONFIG_NETMASK 255.255.255.0
	82	#define CONFIG_IPADDR 192.168.1.56
	83	#define CONFIG_SERVERIP 192.168.1.2
	84	#define CONFIG_BOOTCOMMAND "bootm 0x40000"
	85	#define CONFIG_SHOW_BOOT_PROGRESS
	86
	87	#define CONFIG_CMDLINE_TAG 1
	88
43d9616c WD	89	/*
	90	* Miscellaneous configurable options
	91	*/
	92
	93	/*
f6e20fc6	94	* Size of malloc() pool
43d9616c	95	*/
06d01dbe	96	#define CFG_MALLOC_LEN (256*1024)
a8c7c708	97	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
43d9616c WD	98
	99	#define CFG_LONGHELP /* undef to save memory */
	100	#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
06d01dbe	101	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
43d9616c WD	102	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	103	#define CFG_MAXARGS 16 /* max number of command args */
	104	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	105
	106	#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
	107	#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
	108
	109	#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
	110
06d01dbe	111	#define CFG_LOAD_ADDR 0xa3000000 /* load kernel to this address */
43d9616c WD	112
	113	#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
	114	/* RS: the oscillator is actually 3680130?? */
	115
	116	#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
	117	/* 0101000001 */
	118	/* ^^^^^ Memory Speed 99.53 MHz */
	119	/* ^^ Run Mode Speed = 2x Mem Speed */
	120	/* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
	121
	122	#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
	123
8bde7f77	124	/* valid baudrates */
43d9616c WD	125	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	126
	127	/*
	128	* I2C bus
	129	*/
06d01dbe WD	130	#define CONFIG_HARD_I2C 1
	131	#define CFG_I2C_SPEED 50000
	132	#define CFG_I2C_SLAVE 0xfe
43d9616c WD	133
	134	#define CFG_ENV_IS_IN_EEPROM 1
	135
	136	#define CFG_ENV_OFFSET 0x00 /* environment starts here */
	137	#define CFG_ENV_SIZE 1024 /* 1 KiB */
	138	#define CFG_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */
	139	#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
06d01dbe	140	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */
43d9616c WD	141	#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of address */
43d9616c WD	142	#define CFG_EEPROM_SIZE 4096 /* size in bytes */
06d01dbe WD	143	#define CFG_I2C_INIT_BOARD 1 /* board has it's own init */
	144
	145	/*
	146	* SMSC91C111 Network Card
	147	*/
	148	#define CONFIG_DRIVER_SMC91111 1
	149	#define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */
	150	#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
	151	#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
f39748ae	152	#define CONFIG_SMC_AUTONEG_TIMEOUT 10 /* timeout 10 seconds */
06d01dbe WD	153	#undef CONFIG_SHOW_ACTIVITY
06d01dbe WD	154	#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
43d9616c WD	155
	156	/*
	157	* Stack sizes
	158	*
	159	* The stack sizes are set up in start.S using the settings below
	160	*/
	161	#define CONFIG_STACKSIZE (1281024) / regular stack */
	162	#ifdef CONFIG_USE_IRQ
	163	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	164	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	165	#endif
	166
	167	/*
	168	* Physical Memory Map
	169	*/
	170	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	171	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	172	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	173
	174	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	175	#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
	176
	177	#define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */
	178	#define CFG_DRAM_SIZE 0x04000000
	179
	180	#define CFG_FLASH_BASE PHYS_FLASH_1
	181
	182	/*
700a0c64 WD	183	* JFFS2 partitions
700a0c64 WD	184	*
43d9616c	185	*/
700a0c64 WD	186	/* development flash */
	187	#define CONFIG_MTD_INNOKOM_16MB 1
	188	#undef CONFIG_MTD_INNOKOM_64MB
	189
	190	/* production flash */
	191	/*
	192	#define CONFIG_MTD_INNOKOM_64MB 1
	193	#undef CONFIG_MTD_INNOKOM_16MB
	194	*/
	195
	196	/* No command line, one static partition, whole device */
	197	#undef CONFIG_JFFS2_CMDLINE
	198	#define CONFIG_JFFS2_DEV "nor0"
	199	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	200	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	201
	202	/* mtdparts command line support */
	203	/* Note: fake mtd_id used, no linux mtd map file */
	204	/*
	205	#define CONFIG_JFFS2_CMDLINE
	206	#define MTDIDS_DEFAULT "nor0=innokom-0"
	207	*/
	208
	209	/* development flash */
	210	/*
	211	#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
	212	*/
43d9616c	213
700a0c64 WD	214	/* production flash */
	215	/*
	216	#define MTDPARTS_DEFAULT "mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
	217	*/
06d01dbe WD	218
06d01dbe WD	219	/*
3e38691e	220	* GPIO settings
06d01dbe WD	221	*
06d01dbe WD	222	* GP15 == nCS1 is 1
43d9616c WD	223	* GP24 == SFRM is 1
	224	* GP25 == TXD is 1
	225	* GP33 == nCS5 is 1
	226	* GP39 == FFTXD is 1
	227	* GP41 == RTS is 1
	228	* GP47 == TXD is 1
	229	* GP49 == nPWE is 1
	230	* GP62 == LED_B is 1
	231	* GP63 == TDM_OE is 1
	232	* GP78 == nCS2 is 1
	233	* GP79 == nCS3 is 1
	234	* GP80 == nCS4 is 1
	235	*/
	236	#define CFG_GPSR0_VAL 0x03008000
	237	#define CFG_GPSR1_VAL 0xC0028282
	238	#define CFG_GPSR2_VAL 0x0001C000
	239
	240	/* GP02 == DON_RST is 0
	241	* GP23 == SCLK is 0
	242	* GP45 == USB_ACT is 0
	243	* GP60 == PLLEN is 0
	244	* GP61 == LED_A is 0
	245	* GP73 == SWUPD_LED is 0
	246	*/
	247	#define CFG_GPCR0_VAL 0x00800004
	248	#define CFG_GPCR1_VAL 0x30002000
	249	#define CFG_GPCR2_VAL 0x00000100
	250
	251	/* GP00 == DON_READY is input
	252	* GP01 == DON_OK is input
	253	* GP02 == DON_RST is output
	254	* GP03 == RESET_IND is input
	255	* GP07 == RES11 is input
	256	* GP09 == RES12 is input
	257	* GP11 == SWUPDATE is input
	258	* GP14 == nPOWEROK is input
	259	* GP15 == nCS1 is output
	260	* GP17 == RES22 is input
	261	* GP18 == RDY is input
	262	* GP23 == SCLK is output
	263	* GP24 == SFRM is output
	264	* GP25 == TXD is output
	265	* GP26 == RXD is input
	266	* GP32 == RES21 is input
	267	* GP33 == nCS5 is output
	268	* GP34 == FFRXD is input
	269	* GP35 == CTS is input
	270	* GP39 == FFTXD is output
	271	* GP41 == RTS is output
	272	* GP42 == USB_OK is input
	273	* GP45 == USB_ACT is output
	274	* GP46 == RXD is input
	275	* GP47 == TXD is output
	276	* GP49 == nPWE is output
	277	* GP58 == nCPUBUSINT is input
	278	* GP59 == LANINT is input
	279	* GP60 == PLLEN is output
	280	* GP61 == LED_A is output
	281	* GP62 == LED_B is output
	282	* GP63 == TDM_OE is output
	283	* GP64 == nDSPINT is input
	284	* GP65 == STRAP0 is input
	285	* GP67 == STRAP1 is input
	286	* GP69 == STRAP2 is input
287	* GP70 == STRAP3 is input
288	* GP71 == STRAP4 is input
289	* GP73 == SWUPD_LED is output
290	* GP78 == nCS2 is output
291	* GP79 == nCS3 is output
292	* GP80 == nCS4 is output
293	*/
294	#define CFG_GPDR0_VAL 0x03808004
295	#define CFG_GPDR1_VAL 0xF002A282
296	#define CFG_GPDR2_VAL 0x0001C200
297
298	/* GP15 == nCS1 is AF10
299	* GP18 == RDY is AF01
300	* GP23 == SCLK is AF10
301	* GP24 == SFRM is AF10
302	* GP25 == TXD is AF10
303	* GP26 == RXD is AF01
304	* GP33 == nCS5 is AF10
305	* GP34 == FFRXD is AF01
306	* GP35 == CTS is AF01
307	* GP39 == FFTXD is AF10
308	* GP41 == RTS is AF10
309	* GP46 == RXD is AF10
310	* GP47 == TXD is AF01
311	* GP49 == nPWE is AF10
312	* GP78 == nCS2 is AF10
313	* GP79 == nCS3 is AF10
314	* GP80 == nCS4 is AF10
315	*/
316	#define CFG_GAFR0_L_VAL 0x80000000
317	#define CFG_GAFR0_U_VAL 0x001A8010
318	#define CFG_GAFR1_L_VAL 0x60088058
319	#define CFG_GAFR1_U_VAL 0x00000008
320	#define CFG_GAFR2_L_VAL 0xA0000000
321	#define CFG_GAFR2_U_VAL 0x00000002
322
06d01dbe	323
43d9616c WD	324	/* FIXME: set GPIO_RER/FER */
	325
	326	/* RDH = 1
	327	* PH = 1
	328	* VFS = 1
	329	* BFS = 1
	330	* SSS = 1
	331	*/
	332	#define CFG_PSSR_VAL 0x37
	333
	334	/*
	335	* Memory settings
06d01dbe WD	336	*
06d01dbe WD	337	* This is the configuration for nCS0/1 -> flash banks
43d9616c WD	338	* configuration for nCS1:
	339	* [31] 0 - Slower Device
	340	* [30:28] 010 - CS deselect to CS time: 2(2MemClk) = 40 ns
	341	* [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
	342	* [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
	343	* [19] 1 - 16 Bit bus width
	344	* [18:16] 000 - nonburst RAM or FLASH
	345	* configuration for nCS0:
	346	* [15] 0 - Slower Device
	347	* [14:12] 010 - CS deselect to CS time: 2(2MemClk) = 40 ns
	348	* [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
	349	* [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
	350	* [03] 1 - 16 Bit bus width
	351	* [02:00] 000 - nonburst RAM or FLASH
	352	*/
	353	#define CFG_MSC0_VAL 0x25b825b8 /* flash banks */
	354
	355	/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
	356	* configuration for nCS3: DSP
	357	* [31] 0 - Slower Device
	358	* [30:28] 001 - RRR3: CS deselect to CS time: 1(2MemClk) = 20 ns
	359	* [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
	360	* [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
	361	* [19] 1 - 16 Bit bus width
	362	* [18:16] 100 - variable latency I/O
	363	* configuration for nCS2: TDM-Switch
	364	* [15] 0 - Slower Device
	365	* [14:12] 101 - RRR2: CS deselect to CS time: 5(2MemClk) = 100 ns
	366	* [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
	367	* [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
	368	* [03] 1 - 16 Bit bus width
	369	* [02:00] 100 - variable latency I/O
	370	*/
06d01dbe	371	#define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */
43d9616c WD	372
	373	/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
	374	*
	375	* configuration for nCS5: LAN Controller
	376	* [31] 0 - Slower Device
	377	* [30:28] 001 - RRR5: CS deselect to CS time: 1(2MemClk) = 20 ns
	378	* [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
	379	* [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
	380	* [19] 1 - 16 Bit bus width
	381	* [18:16] 100 - variable latency I/O
	382	* configuration for nCS4: ExtBus
	383	* [15] 0 - Slower Device
	384	* [14:12] 110 - RRR4: CS deselect to CS time: 6(2MemClk) = 120 ns
	385	* [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
	386	* [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
	387	* [03] 1 - 16 Bit bus width
	388	* [02:00] 100 - variable latency I/O
	389	*/
06d01dbe	390	#define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
43d9616c WD	391
	392	/* MDCNFG: SDRAM Configuration Register
	393	*
	394	* [31:29] 000 - reserved
	395	* [28] 0 - no SA1111 compatiblity mode
	396	* [27] 0 - latch return data with return clock
	397	* [26] 0 - alternate addressing for pair 2/3
	398	* [25:24] 00 - timings
	399	* [23] 0 - internal banks in lower partition 2/3 (not used)
	400	* [22:21] 00 - row address bits for partition 2/3 (not used)
	401	* [20:19] 00 - column address bits for partition 2/3 (not used)
	402	* [18] 0 - SDRAM partition 2/3 width is 32 bit
	403	* [17] 0 - SDRAM partition 3 disabled
	404	* [16] 0 - SDRAM partition 2 disabled
	405	* [15:13] 000 - reserved
	406	* [12] 1 - SA1111 compatiblity mode
	407	* [11] 1 - latch return data with return clock
	408	* [10] 0 - no alternate addressing for pair 0/1
06d01dbe	409	* [09:08] 01 - tRP=2MemClk CL=2 tRCD=2MemClk tRAS=5MemClk tRC=8MemClk
43d9616c WD	410	* [7] 1 - 4 internal banks in lower partition pair
	411	* [06:05] 10 - 13 row address bits for partition 0/1
	412	* [04:03] 01 - 9 column address bits for partition 0/1
	413	* [02] 0 - SDRAM partition 0/1 width is 32 bit
	414	* [01] 0 - disable SDRAM partition 1
	415	* [00] 1 - enable SDRAM partition 0
43d9616c	416	*/
06d01dbe	417	/* use the configuration above but disable partition 0 */
43d9616c WD	418	#define CFG_MDCNFG_VAL 0x000019c8
	419
	420	/* MDREFR: SDRAM Refresh Control Register
	421	*
	422	* [32:26] 0 - reserved
	423	* [25] 0 - K2FREE: not free running
	424	* [24] 0 - K1FREE: not free running
3e38691e	425	* [23] 1 - K0FREE: not free running
43d9616c WD	426	* [22] 0 - SLFRSH: self refresh disabled
	427	* [21] 0 - reserved
	428	* [20] 0 - APD: no auto power down
	429	* [19] 0 - K2DB2: SDCLK2 is MemClk
	430	* [18] 0 - K2RUN: disable SDCLK2
	431	* [17] 0 - K1DB2: SDCLK1 is MemClk
	432	* [16] 1 - K1RUN: enable SDCLK1
	433	* [15] 1 - E1PIN: SDRAM clock enable
	434	* [14] 1 - K0DB2: SDCLK0 is MemClk
3e38691e	435	* [13] 0 - K0RUN: disable SDCLK0
43d9616c WD	436	* [12] 1 - E0PIN: disable SDCKE0
	437	* [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
	438	*/
3e38691e	439	#define CFG_MDREFR_VAL 0x0081D018
43d9616c WD	440
	441	/* MDMRS: Mode Register Set Configuration Register
	442	*
	443	* [31] 0 - reserved
	444	* [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
	445	* [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
	446	* [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
	447	* [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
	448	* [15] 0 - reserved
	449	* [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
	450	* [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
	451	* [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
	452	* [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
	453	*/
	454	#define CFG_MDMRS_VAL 0x00020022
	455
	456	/*
	457	* PCMCIA and CF Interfaces
	458	*/
	459	#define CFG_MECR_VAL 0x00000000
	460	#define CFG_MCMEM0_VAL 0x00000000
	461	#define CFG_MCMEM1_VAL 0x00000000
	462	#define CFG_MCATT0_VAL 0x00000000
	463	#define CFG_MCATT1_VAL 0x00000000
	464	#define CFG_MCIO0_VAL 0x00000000
	465	#define CFG_MCIO1_VAL 0x00000000
	466
	467	/*
	468	#define CSB226_USER_LED0 0x00000008
	469	#define CSB226_USER_LED1 0x00000010
	470	#define CSB226_USER_LED2 0x00000020
	471	*/
	472
	473	/*
	474	* FLASH and environment organization
	475	*/
	476	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	477	#define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
	478
	479	/* timeout values are in ticks */
	480	#define CFG_FLASH_ERASE_TOUT (2CFG_HZ) / Timeout for Flash Erase */
	481	#define CFG_FLASH_WRITE_TOUT (2CFG_HZ) / Timeout for Flash Write */
	482
43d9616c	483	#endif /* __CONFIG_H */