[people/ms/u-boot.git] / include / configs / jupiter.h

/*
 * (C) Copyright 2007
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* especially an MPC5200 */
#define CONFIG_JUPITER		1	/* ... on Jupiter board */

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define CONFIG_BOARD_EARLY_INIT_R	1
#define CONFIG_BOARD_EARLY_INIT_F	1

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
/*#define CONFIG_PCI		*/

#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000
#endif

#define CONFIG_SYS_XLB_PIPELINING	1

#define CONFIG_NET_MULTI	1
#define CONFIG_MII		1
#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP

#if defined(CONFIG_PCI)
#define CODFIG_CMD_PCI
#endif


/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"addcons=setenv bootargs ${bootargs} console=${contyp},"	\
		"${baudrate}\0"						\
	"contyp=ttyS0\0"						\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;"	\
		"bootm\0"						\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"bootfile=/tftpboot/jupiter/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBSPEED_133			/* define for 133MHz speed */

#if 0
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 8)
#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
#endif

#if 0
/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
#endif

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_FLASH_SIZE		0x01000000

#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CONFIG_ENV_ADDR		(TEXT_BASE + 0x40000) /* third sector */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
#define CONFIG_SYS_UPDATE_FLASH_SIZE	1
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x20000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_OVERWRITE	1

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */


#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
#ifdef	CONFIG_SYS_HUSH_PARSER
#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#endif
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
#define CONFIG_SYS_ALT_MEMTEST		1

#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047801
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

#endif /* __CONFIG_H */
Commit	Line	Data
2605e90b HS	1	/*
	2	* (C) Copyright 2007
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
	32	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	33	#define CONFIG_MPC5200 1 /* especially an MPC5200 */
	34	#define CONFIG_JUPITER 1 /* ... on Jupiter board */
	35
6d0f6bcf	36	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
2605e90b HS	37
	38	#define CONFIG_BOARD_EARLY_INIT_R 1
	39	#define CONFIG_BOARD_EARLY_INIT_F 1
	40
	41	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	42	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	43
31d82672 BB	44	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	45
2605e90b HS	46	/*
	47	* Serial console configuration
	48	*/
	49	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	50	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	51	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
2605e90b HS	52
	53	/*
	54	* PCI Mapping:
	55	* 0x40000000 - 0x4fffffff - PCI Memory
	56	* 0x50000000 - 0x50ffffff - PCI IO Space
	57	*/
769104c9	58	/#define CONFIG_PCI /
2605e90b HS	59
	60	#if defined(CONFIG_PCI)
	61	#define CONFIG_PCI_PNP 1
	62	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	63	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
2605e90b HS	64
	65	#define CONFIG_PCI_MEM_BUS 0x40000000
	66	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	67	#define CONFIG_PCI_MEM_SIZE 0x10000000
	68
	69	#define CONFIG_PCI_IO_BUS 0x50000000
	70	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	71	#define CONFIG_PCI_IO_SIZE 0x01000000
2605e90b HS	72	#endif
2605e90b HS	73
6d0f6bcf	74	#define CONFIG_SYS_XLB_PIPELINING 1
2605e90b HS	75
	76	#define CONFIG_NET_MULTI 1
	77	#define CONFIG_MII 1
6d0f6bcf	78	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
2605e90b HS	79
	80	/* Partitions */
	81	#define CONFIG_MAC_PARTITION
	82	#define CONFIG_DOS_PARTITION
	83	#define CONFIG_ISO_PARTITION
	84
	85	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	86
bc234c12	87
7f5c0157 JL	88	/*
	89	* BOOTP options
	90	*/
	91	#define CONFIG_BOOTP_BOOTFILESIZE
	92	#define CONFIG_BOOTP_BOOTPATH
	93	#define CONFIG_BOOTP_GATEWAY
	94	#define CONFIG_BOOTP_HOSTNAME
	95
	96
2605e90b	97	/*
bc234c12	98	* Command line configuration.
2605e90b	99	*/
bc234c12 JL	100	#include <config_cmd_default.h>
	101
	102	#define CONFIG_CMD_NFS
	103	#define CONFIG_CMD_SNTP
2605e90b	104
7f5c0157 JL	105	#if defined(CONFIG_PCI)
	106	#define CODFIG_CMD_PCI
	107	#endif
	108
2605e90b HS	109
	110	/*
	111	* Autobooting
	112	*/
	113	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	114
	115	#define CONFIG_PREBOOT "echo;" \
32bf3d14	116	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
2605e90b HS	117	"echo"
	118
	119	#undef CONFIG_BOOTARGS
	120
	121	#define CONFIG_EXTRA_ENV_SETTINGS \
	122	"netdev=eth0\0" \
	123	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	124	"nfsroot=${serverip}:${rootpath}\0" \
	125	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	126	"addip=setenv bootargs ${bootargs} " \
	127	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	128	":${hostname}:${netdev}:off panic=1\0" \
a7090b99	129	"flash_nfs=run nfsargs addip addcons;" \
2605e90b HS	130	"bootm ${kernel_addr}\0" \
	131	"flash_self=run ramargs addip;" \
	132	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
a7090b99	133	"addcons=setenv bootargs ${bootargs} console=${contyp}," \
8502e30a HS	134	"${baudrate}\0" \
8502e30a HS	135	"contyp=ttyS0\0" \
a7090b99	136	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
8502e30a HS	137	"bootm\0" \
8502e30a HS	138	"rootpath=/opt/eldk/ppc_6xx\0" \
2605e90b HS	139	"bootfile=/tftpboot/jupiter/uImage\0" \
	140	""
	141
	142	#define CONFIG_BOOTCOMMAND "run flash_self"
	143
	144	/*
	145	* IPB Bus clocking configuration.
	146	*/
6d0f6bcf	147	#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
2605e90b HS	148
	149	#if 0
	150	/* pass open firmware flat tree */
cf2817a8	151	#define CONFIG_OF_LIBFDT 1
2605e90b HS	152	#define CONFIG_OF_BOARD_SETUP 1
2605e90b HS	153
2605e90b HS	154	#define OF_CPU "PowerPC,5200@0"
	155	#define OF_SOC "soc5200@f0000000"
	156	#define OF_TBCLK (bd->bi_busfreq / 8)
	157	#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
	158	#endif
	159
	160	#if 0
	161	/*
	162	* I2C configuration
	163	*/
	164	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	165	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
2605e90b	166
6d0f6bcf JCPV	167	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	168	#define CONFIG_SYS_I2C_SLAVE 0x7F
2605e90b HS	169
	170	/*
	171	* EEPROM configuration
	172	*/
6d0f6bcf JCPV	173	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	174	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	175	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	176	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
2605e90b HS	177	#endif
	178
	179	/*
	180	* Flash configuration
	181	*/
6d0f6bcf JCPV	182	#define CONFIG_SYS_FLASH_BASE 0xFF000000
6d0f6bcf JCPV	183	#define CONFIG_SYS_FLASH_SIZE 0x01000000
2605e90b	184
6d0f6bcf	185	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
2605e90b	186
0e8d1586	187	#define CONFIG_ENV_ADDR (TEXT_BASE + 0x40000) /* third sector */
2605e90b	188
6d0f6bcf JCPV	189	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	190	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
2605e90b	191
6d0f6bcf	192	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
2605e90b	193
00b1883a	194	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	195	#define CONFIG_SYS_FLASH_CFI
	196	#define CONFIG_SYS_FLASH_EMPTY_INFO
	197	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
	198	#define CONFIG_SYS_UPDATE_FLASH_SIZE 1
	199	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
2605e90b HS	200
	201	/*
	202	* Environment settings
	203	*/
5a1aceb0	204	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	205	#define CONFIG_ENV_SIZE 0x20000
0e8d1586 JCPV	206	#define CONFIG_ENV_SECT_SIZE 0x20000
2605e90b HS	207	#define CONFIG_ENV_OVERWRITE 1
2605e90b HS	208
8502e30a	209	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	210	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	211	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
8502e30a	212
2605e90b HS	213	/*
	214	* Memory map
	215	*/
6d0f6bcf JCPV	216	#define CONFIG_SYS_MBAR 0xF0000000
	217	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	218	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
2605e90b HS	219
2605e90b HS	220	/* Use SRAM until RAM will be available */
6d0f6bcf JCPV	221	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
6d0f6bcf JCPV	222	#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
2605e90b HS	223
2605e90b HS	224
6d0f6bcf JCPV	225	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	226	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	227	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
2605e90b	228
6d0f6bcf JCPV	229	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	230	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	231	# define CONFIG_SYS_RAMBOOT 1
2605e90b HS	232	#endif
2605e90b HS	233
6d0f6bcf JCPV	234	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	235	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	236	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
2605e90b HS	237
	238	/*
	239	* Ethernet configuration
	240	*/
	241	#define CONFIG_MPC5xxx_FEC 1
	242	/*
	243	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	244	*/
	245	/* #define CONFIG_FEC_10MBIT 1 */
	246	#define CONFIG_PHY_ADDR 0x00
	247
	248	/*
	249	* GPIO configuration
	250	*/
6d0f6bcf	251	#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
2605e90b HS	252
	253	/*
	254	* Miscellaneous configurable options
	255	*/
6d0f6bcf JCPV	256	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	257	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
8502e30a HS	258
8502e30a HS	259	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
6d0f6bcf JCPV	260	#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
	261	#ifdef CONFIG_SYS_HUSH_PARSER
	262	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
8502e30a	263	#endif
bc234c12	264	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	265	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
2605e90b	266	#else
6d0f6bcf	267	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
2605e90b	268	#endif
6d0f6bcf JCPV	269	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	270	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	271	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
2605e90b	272
6d0f6bcf JCPV	273	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
	274	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	275	#define CONFIG_SYS_ALT_MEMTEST 1
2605e90b	276
6d0f6bcf	277	#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
2605e90b	278
6d0f6bcf	279	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
2605e90b	280
6d0f6bcf	281	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
bc234c12	282	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	283	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
bc234c12 JL	284	#endif
bc234c12 JL	285
2605e90b HS	286	/*
	287	* Various low-level settings
	288	*/
6d0f6bcf JCPV	289	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	290	#define CONFIG_SYS_HID0_FINAL HID0_ICE
2605e90b	291
6d0f6bcf JCPV	292	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	293	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	294	#define CONFIG_SYS_BOOTCS_CFG 0x00047801
	295	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	296	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
2605e90b	297
6d0f6bcf JCPV	298	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	299	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
2605e90b	300
6d0f6bcf	301	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
2605e90b HS	302
2605e90b HS	303	#endif /* __CONFIG_H */