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67fa8c25 HS |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Marvell Semiconductor <www.marvell.com> | |
4 | * Prafulla Wadaskar <prafulla@marvell.com> | |
5 | * | |
6 | * (C) Copyright 2009 | |
7 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
8 | * | |
b11f53f3 HS |
9 | * (C) Copyright 2010-2011 |
10 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
11 | * | |
1a459660 | 12 | * SPDX-License-Identifier: GPL-2.0+ |
67fa8c25 HS |
13 | */ |
14 | ||
b11f53f3 HS |
15 | /* |
16 | * for linking errors see | |
17 | * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html | |
18 | */ | |
67fa8c25 HS |
19 | |
20 | #ifndef _CONFIG_KM_ARM_H | |
21 | #define _CONFIG_KM_ARM_H | |
22 | ||
8e59f8bb | 23 | |
8620ca2a VL |
24 | /* We got removed from Linux mach-types.h */ |
25 | #define MACH_TYPE_KM_KIRKWOOD 2255 | |
26 | ||
67fa8c25 HS |
27 | /* |
28 | * High Level Configuration Options (easy to change) | |
29 | */ | |
30 | #define CONFIG_MARVELL | |
67fa8c25 | 31 | #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ |
67fa8c25 | 32 | #define CONFIG_KW88F6281 /* SOC Name */ |
802d9963 | 33 | #define CONFIG_MACH_KM_KIRKWOOD /* Machine type */ |
67fa8c25 | 34 | |
8620ca2a VL |
35 | #define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD |
36 | ||
dfeafde4 HB |
37 | #define CONFIG_NAND_ECC_BCH |
38 | #define CONFIG_BCH | |
39 | ||
67fa8c25 HS |
40 | /* include common defines/options for all Keymile boards */ |
41 | #include "keymile-common.h" | |
de3ad13d | 42 | |
b5befd82 | 43 | #define CONFIG_CMD_NAND |
b5befd82 | 44 | |
f46b4a1a VL |
45 | /* SPI NOR Flash default params, used by sf commands */ |
46 | #define CONFIG_SF_DEFAULT_SPEED 8100000 | |
47 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 | |
48 | ||
8170aefc HB |
49 | #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR |
50 | #define CONFIG_ENV_SPI_BUS 0 | |
51 | #define CONFIG_ENV_SPI_CS 0 | |
05c8e81f | 52 | #define CONFIG_ENV_SPI_MAX_HZ 8100000 |
8170aefc HB |
53 | #define CONFIG_ENV_SPI_MODE SPI_MODE_3 |
54 | #endif | |
55 | ||
ac5b00e0 VL |
56 | /* Reserve 4 MB for malloc */ |
57 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
58 | ||
b5befd82 HB |
59 | #include "asm/arch/config.h" |
60 | ||
e5847b77 | 61 | #define CONFIG_SYS_TEXT_BASE 0x07d00000 /* code address before reloc */ |
de3ad13d HB |
62 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ |
63 | #define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ | |
64 | #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ | |
65 | ||
66 | /* pseudo-non volatile RAM [hex] */ | |
67 | #define CONFIG_KM_PNVRAM 0x80000 | |
68 | /* physical RAM MTD size [hex] */ | |
69 | #define CONFIG_KM_PHRAM 0x17F000 | |
70 | ||
71 | #define CONFIG_KM_CRAMFS_ADDR 0x2400000 | |
7b2268b8 GF |
72 | #define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 3098KBytes */ |
73 | #define CONFIG_KM_FDT_ADDR 0x23E0000 /* 128KBytes */ | |
de3ad13d | 74 | |
db0bb572 HB |
75 | /* architecture specific default bootargs */ |
76 | #define CONFIG_KM_DEF_BOOT_ARGS_CPU \ | |
66072a8c HB |
77 | "bootcountaddr=${bootcountaddr} ${mtdparts}" \ |
78 | " boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}" | |
db0bb572 | 79 | |
de3ad13d | 80 | #define CONFIG_KM_DEF_ENV_CPU \ |
93ea89f0 | 81 | "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0" \ |
af85f085 | 82 | CONFIG_KM_UPDATE_UBOOT \ |
b1c2a7ae | 83 | "set_fdthigh=setenv fdt_high ${kernelmem}\0" \ |
c6d32dfd VL |
84 | "checkfdt=" \ |
85 | "if cramfsls fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; " \ | |
86 | "then true; else setenv cramfsloadfdt true; " \ | |
87 | "setenv boot bootm ${load_addr_r}; " \ | |
88 | "echo No FDT found, booting with the kernel " \ | |
89 | "appended one; fi\0" \ | |
de3ad13d HB |
90 | "" |
91 | ||
67fa8c25 | 92 | #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
67fa8c25 HS |
93 | #define CONFIG_MISC_INIT_R |
94 | ||
95 | /* | |
96 | * NS16550 Configuration | |
97 | */ | |
67fa8c25 HS |
98 | #define CONFIG_SYS_NS16550_SERIAL |
99 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
100 | #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK | |
101 | #define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE | |
3d3c7096 | 102 | #define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE |
67fa8c25 HS |
103 | |
104 | /* | |
105 | * Serial Port configuration | |
106 | * The following definitions let you select what serial you want to use | |
107 | * for your console driver. | |
108 | */ | |
109 | ||
110 | #define CONFIG_CONS_INDEX 1 /* Console on UART0 */ | |
111 | ||
112 | /* | |
113 | * For booting Linux, the board info and command line data | |
114 | * have to be in the first 8 MB of memory, since this is | |
115 | * the maximum mapped by the Linux kernel during initialization. | |
116 | */ | |
117 | #define CONFIG_BOOTMAPSZ (8 << 20) /* Initial Memmap for Linux */ | |
118 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
119 | #define CONFIG_INITRD_TAG /* enable INITRD tag */ | |
499b1a4d | 120 | #define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ |
67fa8c25 HS |
121 | |
122 | /* | |
123 | * Commands configuration | |
124 | */ | |
67fa8c25 | 125 | #define CONFIG_CMD_MTDPARTS |
67fa8c25 HS |
126 | |
127 | /* | |
128 | * Without NOR FLASH we need this | |
129 | */ | |
130 | #define CONFIG_SYS_NO_FLASH | |
67fa8c25 HS |
131 | |
132 | /* | |
133 | * NAND Flash configuration | |
134 | */ | |
135 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
67fa8c25 HS |
136 | |
137 | #define BOOTFLASH_START 0x0 | |
138 | ||
3d3c7096 HB |
139 | /* Kirkwood has two serial IF */ |
140 | #if (CONFIG_CONS_INDEX == 2) | |
141 | #define CONFIG_KM_CONSOLE_TTY "ttyS1" | |
142 | #else | |
67fa8c25 | 143 | #define CONFIG_KM_CONSOLE_TTY "ttyS0" |
3d3c7096 | 144 | #endif |
67fa8c25 | 145 | |
67fa8c25 HS |
146 | /* |
147 | * Other required minimal configurations | |
148 | */ | |
149 | #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ | |
150 | #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ | |
151 | #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ | |
67fa8c25 | 152 | #define CONFIG_NR_DRAM_BANKS 4 |
67fa8c25 HS |
153 | #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ |
154 | ||
155 | /* | |
156 | * Ethernet Driver configuration | |
157 | */ | |
158 | #define CONFIG_NETCONSOLE /* include NetConsole support */ | |
67fa8c25 | 159 | #define CONFIG_MII /* expose smi ove miiphy interface */ |
d44265ad | 160 | #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ |
67fa8c25 | 161 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ |
d44265ad | 162 | #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ |
67fa8c25 HS |
163 | #define CONFIG_PHY_BASE_ADR 0 |
164 | #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ | |
99f6249a | 165 | #define CONFIG_KM_COMMON_ETH_INIT /* standard km ethernet_present for piggy */ |
67fa8c25 HS |
166 | |
167 | /* | |
168 | * UBI related stuff | |
169 | */ | |
170 | #define CONFIG_SYS_USE_UBI | |
171 | ||
172 | /* | |
173 | * I2C related stuff | |
174 | */ | |
ea818dbb HS |
175 | #undef CONFIG_I2C_MVTWSI |
176 | #define CONFIG_SYS_I2C | |
177 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
0a4f88b9 | 178 | #define CONFIG_SYS_I2C_INIT_BOARD |
ea818dbb | 179 | |
67fa8c25 | 180 | #define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */ |
ea818dbb HS |
181 | #define CONFIG_SYS_NUM_I2C_BUSES 6 |
182 | #define CONFIG_SYS_I2C_MAX_HOPS 1 | |
183 | #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ | |
184 | {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ | |
185 | {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ | |
186 | {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ | |
187 | {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ | |
188 | {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ | |
189 | } | |
190 | ||
67fa8c25 | 191 | #ifndef __ASSEMBLY__ |
ea385723 | 192 | #include <asm/arch/gpio.h> |
67fa8c25 | 193 | extern void __set_direction(unsigned pin, int high); |
499b1a4d HB |
194 | void set_sda(int state); |
195 | void set_scl(int state); | |
196 | int get_sda(void); | |
197 | int get_scl(void); | |
44097e26 HS |
198 | #define KM_KIRKWOOD_SDA_PIN 8 |
199 | #define KM_KIRKWOOD_SCL_PIN 9 | |
c471d848 | 200 | #define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300 |
44097e26 HS |
201 | #define KM_KIRKWOOD_ENV_WP 38 |
202 | ||
203 | #define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0) | |
204 | #define I2C_TRISTATE __set_direction(KM_KIRKWOOD_SDA_PIN, 1) | |
205 | #define I2C_READ (kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0) | |
206 | #define I2C_SDA(bit) kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit) | |
207 | #define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit) | |
67fa8c25 HS |
208 | #endif |
209 | ||
9e9c6d7c | 210 | #define I2C_DELAY udelay(1) |
67fa8c25 HS |
211 | #define I2C_SOFT_DECLARATIONS |
212 | ||
ea818dbb HS |
213 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x0 |
214 | #define CONFIG_SYS_I2C_SOFT_SPEED 100000 | |
67fa8c25 | 215 | |
4daea6ff | 216 | /* EEprom support 24C128, 24C256 valid for environment eeprom */ |
4daea6ff SB |
217 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE |
218 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */ | |
219 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
220 | ||
67fa8c25 HS |
221 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
222 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
223 | ||
331a30dc HS |
224 | /* |
225 | * Environment variables configurations | |
226 | */ | |
8170aefc HB |
227 | #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR |
228 | #define CONFIG_ENV_IS_IN_SPI_FLASH /* use SPI-Flash for environment vars */ | |
229 | #define CONFIG_ENV_OFFSET 0xc0000 /* no bracets! */ | |
230 | #define CONFIG_ENV_SIZE 0x02000 /* Size of Environment */ | |
231 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
232 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ | |
233 | CONFIG_ENV_SECT_SIZE) | |
234 | #define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */ | |
235 | #else | |
331a30dc HS |
236 | #define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ |
237 | #define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 | |
238 | #define CONFIG_ENV_EEPROM_IS_ON_I2C | |
239 | #define CONFIG_SYS_EEPROM_WREN | |
240 | #define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ | |
331a30dc | 241 | #define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) |
716e4ffe | 242 | #define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */ |
331a30dc HS |
243 | #define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ |
244 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
8170aefc HB |
245 | #endif |
246 | ||
247 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT | |
331a30dc | 248 | |
331a30dc | 249 | |
0c25defc VL |
250 | /* SPI bus claim MPP configuration */ |
251 | #define CONFIG_SYS_KW_SPI_MPP 0x0 | |
252 | ||
331a30dc | 253 | #define FLASH_GPIO_PIN 0x00010000 |
0c25defc | 254 | #define KM_FLASH_GPIO_PIN 16 |
331a30dc | 255 | |
cf73639d AH |
256 | #ifndef MTDIDS_DEFAULT |
257 | # define MTDIDS_DEFAULT "nand0=orion_nand" | |
258 | #endif /* MTDIDS_DEFAULT */ | |
259 | ||
260 | #ifndef MTDPARTS_DEFAULT | |
261 | # define MTDPARTS_DEFAULT "mtdparts=" \ | |
262 | "orion_nand:" \ | |
263 | "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" | |
264 | #endif /* MTDPARTS_DEFAULT */ | |
331a30dc | 265 | |
af85f085 | 266 | #define CONFIG_KM_UPDATE_UBOOT \ |
331a30dc | 267 | "update=" \ |
0c25defc VL |
268 | "sf probe 0;sf erase 0 +${filesize};" \ |
269 | "sf write ${load_addr_r} 0 ${filesize};\0" | |
331a30dc | 270 | |
8170aefc HB |
271 | #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR |
272 | #define CONFIG_KM_NEW_ENV \ | |
273 | "newenv=sf probe 0;" \ | |
93ea89f0 MV |
274 | "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ |
275 | __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" | |
8170aefc HB |
276 | #else |
277 | #define CONFIG_KM_NEW_ENV \ | |
ea616d4d | 278 | "newenv=setenv addr 0x100000 && " \ |
67bfae36 HB |
279 | "i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; " \ |
280 | "mw.b ${addr} 0 4 && " \ | |
93ea89f0 MV |
281 | "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \ |
282 | " ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \ | |
283 | "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \ | |
284 | " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0" | |
8170aefc HB |
285 | #endif |
286 | ||
56cde177 HB |
287 | #ifndef CONFIG_KM_BOARD_EXTRA_ENV |
288 | #define CONFIG_KM_BOARD_EXTRA_ENV "" | |
289 | #endif | |
290 | ||
8170aefc HB |
291 | /* |
292 | * Default environment variables | |
293 | */ | |
294 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
56cde177 | 295 | CONFIG_KM_BOARD_EXTRA_ENV \ |
8170aefc HB |
296 | CONFIG_KM_DEF_ENV \ |
297 | CONFIG_KM_NEW_ENV \ | |
b648bfc2 | 298 | "arch=arm\0" \ |
ea616d4d VL |
299 | "" |
300 | ||
67fa8c25 | 301 | #if defined(CONFIG_SYS_NO_FLASH) |
67fa8c25 HS |
302 | #undef CONFIG_FLASH_CFI_MTD |
303 | #undef CONFIG_JFFS2_CMDLINE | |
304 | #endif | |
305 | ||
a784c01a | 306 | /* additions for new relocation code, must be added to all boards */ |
ab86f72c | 307 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
6b0ccc3b HS |
308 | /* Do early setups now in board_init_f() */ |
309 | #define CONFIG_BOARD_EARLY_INIT_F | |
f1fef1d8 HS |
310 | |
311 | /* | |
312 | * resereved pram area at the end of memroy [hex] | |
313 | * 8Mbytes for switch + 4Kbytes for bootcount | |
314 | */ | |
315 | #define CONFIG_KM_RESERVED_PRAM 0x801000 | |
a21b5d4b HB |
316 | /* address for the bootcount (taken from end of RAM) */ |
317 | #define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM) | |
0044c42e SR |
318 | /* Use generic bootcount RAM driver */ |
319 | #define CONFIG_BOOTCOUNT_RAM | |
f1fef1d8 | 320 | |
9400f8fa VL |
321 | /* enable POST tests */ |
322 | #define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS) | |
323 | #define CONFIG_POST_SKIP_ENV_FLAGS | |
324 | #define CONFIG_POST_EXTERNAL_WORD_FUNCS | |
325 | #define CONFIG_CMD_DIAG | |
326 | ||
b37f7724 | 327 | /* we do the whole PCIe FPGA config stuff here */ |
45bd01ef | 328 | #define CONFIG_BOARD_LATE_INIT |
b37f7724 | 329 | |
67fa8c25 | 330 | #endif /* _CONFIG_KM_ARM_H */ |