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1 | /* |
2 | * Copyright 2016 Freescale Semiconductor | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __LS1012A_COMMON_H | |
8 | #define __LS1012A_COMMON_H | |
9 | ||
10 | #define CONFIG_FSL_LAYERSCAPE | |
11 | #define CONFIG_FSL_LSCH2 | |
12 | #define CONFIG_LS1012A | |
13 | #define CONFIG_GICV2 | |
14 | ||
15 | #define CONFIG_SYS_HAS_SERDES | |
16 | ||
17 | #include <asm/arch/config.h> | |
18 | #define CONFIG_SYS_NO_FLASH | |
19 | ||
20 | #define CONFIG_SUPPORT_RAW_INITRD | |
21 | ||
22 | #define CONFIG_DISPLAY_BOARDINFO_LATE | |
23 | ||
24 | #define CONFIG_SYS_TEXT_BASE 0x40100000 | |
25 | ||
26 | #define CONFIG_SYS_FSL_CLK | |
27 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
28 | #define CONFIG_DDR_CLK_FREQ 125000000 | |
29 | ||
30 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
31 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
32 | ||
33 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) | |
34 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) | |
35 | ||
36 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 | |
37 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 | |
38 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
39 | ||
40 | /* Generic Timer Definitions */ | |
41 | #define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */ | |
42 | ||
43 | /* CSU */ | |
44 | #define CONFIG_LAYERSCAPE_NS_ACCESS | |
45 | ||
46 | /* Size of malloc() pool */ | |
47 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) | |
48 | ||
49 | /*SPI device */ | |
50 | #ifdef CONFIG_QSPI_BOOT | |
51 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
52 | #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 | |
53 | #define CONFIG_ENV_SPI_BUS 0 | |
54 | #define CONFIG_ENV_SPI_CS 0 | |
55 | #define CONFIG_ENV_SPI_MAX_HZ 1000000 | |
56 | #define CONFIG_ENV_SPI_MODE 0x03 | |
57 | #define CONFIG_SPI_FLASH_SPANSION | |
58 | #define CONFIG_FSL_SPI_INTERFACE | |
59 | #define CONFIG_SF_DATAFLASH | |
60 | ||
61 | #define CONFIG_FSL_QSPI | |
62 | #define QSPI0_AMBA_BASE 0x40000000 | |
63 | #define CONFIG_SPI_FLASH_SPANSION | |
64 | #define CONFIG_SPI_FLASH_BAR | |
65 | ||
66 | #define FSL_QSPI_FLASH_SIZE (1 << 24) | |
67 | #define FSL_QSPI_FLASH_NUM 2 | |
68 | ||
69 | /* | |
70 | * Environment | |
71 | */ | |
72 | #define CONFIG_ENV_OVERWRITE | |
73 | ||
74 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
75 | #define CONFIG_ENV_SIZE 0x40000 /* 256KB */ | |
76 | #define CONFIG_ENV_OFFSET 0x200000 /* 2MB */ | |
77 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
78 | #endif | |
79 | ||
80 | /* I2C */ | |
81 | #define CONFIG_SYS_I2C | |
82 | #define CONFIG_SYS_I2C_MXC | |
83 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ | |
84 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
85 | ||
86 | #define CONFIG_CONS_INDEX 1 | |
87 | #define CONFIG_SYS_NS16550_SERIAL | |
88 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
89 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
90 | ||
91 | #define CONFIG_BAUDRATE 115200 | |
92 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
93 | ||
94 | /* Command line configuration */ | |
95 | #define CONFIG_CMD_ENV | |
96 | #undef CONFIG_CMD_IMLS | |
97 | ||
98 | #define CONFIG_ARCH_EARLY_INIT_R | |
99 | ||
100 | #define CONFIG_SYS_HZ 1000 | |
101 | ||
102 | #define CONFIG_HWCONFIG | |
103 | #define HWCONFIG_BUFFER_SIZE 128 | |
104 | ||
105 | #define CONFIG_DISPLAY_CPUINFO | |
106 | ||
107 | /* Initial environment variables */ | |
108 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
109 | "initrd_high=0xffffffff\0" \ | |
110 | "verify=no\0" \ | |
111 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
112 | "loadaddr=0x80100000\0" \ | |
113 | "kernel_addr=0x100000\0" \ | |
114 | "ramdisk_addr=0x800000\0" \ | |
115 | "ramdisk_size=0x2000000\0" \ | |
116 | "fdt_high=0xffffffffffffffff\0" \ | |
117 | "initrd_high=0xffffffffffffffff\0" \ | |
118 | "kernel_start=0xa00000\0" \ | |
119 | "kernel_load=0xa0000000\0" \ | |
120 | "kernel_size=0x2800000\0" \ | |
121 | "console=ttyAMA0,38400n8\0" | |
122 | ||
123 | #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ | |
124 | "earlycon=uart8250,mmio,0x21c0500" | |
125 | #define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ | |
126 | "$kernel_start $kernel_size && "\ | |
127 | "bootm $kernel_load" | |
9d044fcb PK |
128 | |
129 | /* Monitor Command Prompt */ | |
130 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
131 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
132 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
133 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ | |
134 | #define CONFIG_SYS_LONGHELP | |
135 | #define CONFIG_CMDLINE_EDITING 1 | |
136 | #define CONFIG_AUTO_COMPLETE | |
137 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ | |
138 | ||
139 | #define CONFIG_PANIC_HANG | |
140 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
141 | ||
142 | #include <asm/fsl_secure_boot.h> | |
143 | ||
144 | #endif /* __LS1012A_COMMON_H */ |