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f3a8e2b7 MH |
1 | /* |
2 | * Copyright (C) 2015 Freescale Semiconductor | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __LS1043A_COMMON_H | |
8 | #define __LS1043A_COMMON_H | |
9 | ||
10 | #define CONFIG_REMAKE_ELF | |
11 | #define CONFIG_FSL_LAYERSCAPE | |
12 | #define CONFIG_FSL_LSCH2 | |
13 | #define CONFIG_LS1043A | |
14 | #define CONFIG_SYS_FSL_CLK | |
15 | #define CONFIG_GICV2 | |
16 | ||
17 | #include <asm/arch/config.h> | |
18 | #ifdef CONFIG_SYS_FSL_SRDS_1 | |
19 | #define CONFIG_SYS_HAS_SERDES | |
20 | #endif | |
21 | ||
22 | /* Link Definitions */ | |
23 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) | |
24 | ||
25 | #define CONFIG_SUPPORT_RAW_INITRD | |
26 | ||
27 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
28 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
29 | ||
30 | /* Flat Device Tree Definitions */ | |
31 | #define CONFIG_OF_LIBFDT | |
32 | #define CONFIG_OF_BOARD_SETUP | |
33 | ||
34 | /* new uImage format support */ | |
35 | #define CONFIG_FIT | |
36 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
37 | ||
38 | #ifndef CONFIG_SYS_FSL_DDR4 | |
39 | #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ | |
40 | #endif | |
41 | ||
42 | #define CONFIG_VERY_BIG_RAM | |
43 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 | |
44 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 | |
45 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
46 | ||
47 | /* Generic Timer Definitions */ | |
48 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ | |
49 | ||
50 | /* Size of malloc() pool */ | |
51 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) | |
52 | ||
53 | /* Serial Port */ | |
54 | #define CONFIG_CONS_INDEX 1 | |
55 | #define CONFIG_SYS_NS16550 | |
56 | #define CONFIG_SYS_NS16550_SERIAL | |
57 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
58 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) | |
59 | ||
60 | #define CONFIG_BAUDRATE 115200 | |
61 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
62 | ||
c7ca8b07 GQ |
63 | /* SD boot SPL */ |
64 | #ifdef CONFIG_SD_BOOT | |
65 | #define CONFIG_SPL_FRAMEWORK | |
66 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" | |
67 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
68 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
69 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
70 | #define CONFIG_SPL_ENV_SUPPORT | |
71 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
72 | #define CONFIG_SPL_WATCHDOG_SUPPORT | |
73 | #define CONFIG_SPL_I2C_SUPPORT | |
74 | #define CONFIG_SPL_SERIAL_SUPPORT | |
75 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT | |
76 | #define CONFIG_SPL_MMC_SUPPORT | |
77 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0 | |
78 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 | |
79 | ||
80 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
81 | #define CONFIG_SPL_MAX_SIZE 0x1d000 | |
82 | #define CONFIG_SPL_STACK 0x1001e000 | |
83 | #define CONFIG_SPL_PAD_TO 0x1d000 | |
84 | ||
85 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ | |
86 | CONFIG_SYS_MONITOR_LEN) | |
87 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
88 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
89 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
90 | #define CONFIG_SYS_MONITOR_LEN 0xa0000 | |
91 | #endif | |
92 | ||
3ad44729 GQ |
93 | /* NAND SPL */ |
94 | #ifdef CONFIG_NAND_BOOT | |
95 | #define CONFIG_SPL_PBL_PAD | |
96 | #define CONFIG_SPL_FRAMEWORK | |
97 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" | |
98 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
99 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
100 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
101 | #define CONFIG_SPL_ENV_SUPPORT | |
102 | #define CONFIG_SPL_WATCHDOG_SUPPORT | |
103 | #define CONFIG_SPL_I2C_SUPPORT | |
104 | #define CONFIG_SPL_SERIAL_SUPPORT | |
105 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
106 | #define CONFIG_SPL_NAND_SUPPORT | |
107 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT | |
108 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
109 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
110 | #define CONFIG_SPL_STACK 0x1001d000 | |
111 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE | |
112 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
113 | #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 | |
114 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
115 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
116 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
117 | #define CONFIG_SYS_MONITOR_LEN 0xa0000 | |
118 | #endif | |
119 | ||
f3a8e2b7 MH |
120 | /* IFC */ |
121 | #define CONFIG_FSL_IFC | |
122 | /* | |
123 | * CONFIG_SYS_FLASH_BASE has the final address (core view) | |
124 | * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) | |
125 | * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address | |
126 | * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting | |
127 | */ | |
128 | #define CONFIG_SYS_FLASH_BASE 0x60000000 | |
129 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
130 | #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 | |
131 | ||
132 | #ifndef CONFIG_SYS_NO_FLASH | |
133 | #define CONFIG_FLASH_CFI_DRIVER | |
134 | #define CONFIG_SYS_FLASH_CFI | |
135 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
136 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
137 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
138 | #endif | |
139 | ||
140 | /* I2C */ | |
141 | #define CONFIG_CMD_I2C | |
142 | #define CONFIG_SYS_I2C | |
143 | #define CONFIG_SYS_I2C_MXC | |
144 | #define CONFIG_SYS_I2C_MXC_I2C1 | |
145 | #define CONFIG_SYS_I2C_MXC_I2C2 | |
146 | #define CONFIG_SYS_I2C_MXC_I2C3 | |
147 | #define CONFIG_SYS_I2C_MXC_I2C4 | |
148 | ||
149 | /* PCIe */ | |
150 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
151 | #define CONFIG_PCIE1 /* PCIE controller 1 */ | |
152 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
153 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
154 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ | |
155 | #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" | |
156 | ||
157 | #define CONFIG_SYS_PCI_64BIT | |
158 | ||
159 | #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 | |
160 | #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ | |
161 | #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 | |
162 | #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ | |
163 | ||
164 | #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 | |
165 | #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 | |
166 | #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ | |
167 | ||
168 | #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 | |
169 | #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 | |
170 | #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ | |
171 | ||
172 | #ifdef CONFIG_PCI | |
173 | #define CONFIG_NET_MULTI | |
174 | #define CONFIG_PCI_PNP | |
175 | #define CONFIG_E1000 | |
176 | #define CONFIG_PCI_SCAN_SHOW | |
177 | #define CONFIG_CMD_PCI | |
178 | #endif | |
179 | ||
180 | /* Command line configuration */ | |
181 | #define CONFIG_CMD_CACHE | |
182 | #define CONFIG_CMD_DHCP | |
183 | #define CONFIG_CMD_ENV | |
184 | #define CONFIG_CMD_PING | |
185 | ||
8ef0d5c4 YL |
186 | /* MMC */ |
187 | #define CONFIG_MMC | |
188 | #ifdef CONFIG_MMC | |
189 | #define CONFIG_CMD_MMC | |
190 | #define CONFIG_CMD_FAT | |
191 | #define CONFIG_FSL_ESDHC | |
192 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
193 | #define CONFIG_GENERIC_MMC | |
194 | #define CONFIG_DOS_PARTITION | |
195 | #endif | |
196 | ||
e8297341 SX |
197 | /* FMan ucode */ |
198 | #define CONFIG_SYS_DPAA_FMAN | |
199 | #ifdef CONFIG_SYS_DPAA_FMAN | |
200 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 | |
201 | ||
202 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
203 | /* FMan fireware Pre-load address */ | |
204 | #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 | |
205 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
206 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
207 | #endif | |
208 | ||
f3a8e2b7 MH |
209 | /* Miscellaneous configurable options */ |
210 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) | |
211 | #define CONFIG_ARCH_EARLY_INIT_R | |
212 | #define CONFIG_BOARD_LATE_INIT | |
213 | ||
214 | #define CONFIG_HWCONFIG | |
215 | #define HWCONFIG_BUFFER_SIZE 128 | |
216 | ||
217 | /* Initial environment variables */ | |
218 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
219 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
220 | "loadaddr=0x80100000\0" \ | |
221 | "kernel_addr=0x100000\0" \ | |
222 | "ramdisk_addr=0x800000\0" \ | |
223 | "ramdisk_size=0x2000000\0" \ | |
224 | "fdt_high=0xffffffffffffffff\0" \ | |
225 | "initrd_high=0xffffffffffffffff\0" \ | |
226 | "kernel_start=0x61200000\0" \ | |
227 | "kernel_load=0x807f0000\0" \ | |
228 | "kernel_size=0x1000000\0" \ | |
229 | "console=ttyAMA0,38400n8\0" | |
230 | ||
231 | #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ | |
232 | "earlycon=uart8250,0x21c0500,115200" | |
233 | #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ | |
234 | "$kernel_size && bootm $kernel_load" | |
235 | #define CONFIG_BOOTDELAY 10 | |
236 | ||
237 | /* Monitor Command Prompt */ | |
238 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
239 | #define CONFIG_SYS_PROMPT "=> " | |
240 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
241 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
242 | #define CONFIG_SYS_HUSH_PARSER | |
243 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
244 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ | |
245 | #define CONFIG_SYS_LONGHELP | |
246 | #define CONFIG_CMDLINE_EDITING 1 | |
247 | #define CONFIG_AUTO_COMPLETE | |
248 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ | |
249 | ||
250 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
251 | ||
252 | #endif /* __LS1043A_COMMON_H */ |