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f749db3a YS |
1 | /* |
2 | * Copyright (C) 2014 Freescale Semiconductor | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __LS2_COMMON_H | |
8 | #define __LS2_COMMON_H | |
9 | ||
f749db3a | 10 | #define CONFIG_REMAKE_ELF |
9f3183d2 | 11 | #define CONFIG_FSL_LAYERSCAPE |
f749db3a | 12 | #define CONFIG_FSL_LSCH3 |
9f3183d2 | 13 | #define CONFIG_MP |
f749db3a | 14 | #define CONFIG_GICV3 |
9c66ce66 | 15 | #define CONFIG_FSL_TZPC_BP147 |
f749db3a | 16 | |
44937214 | 17 | #include <asm/arch/ls2080a_stream_id.h> |
9f3183d2 | 18 | #include <asm/arch/config.h> |
31d34c6c ML |
19 | #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) |
20 | #define CONFIG_SYS_HAS_SERDES | |
21 | #endif | |
22 | ||
9f3183d2 MH |
23 | /* Link Definitions */ |
24 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) | |
25 | ||
422cb08a BS |
26 | /* We need architecture specific misc initializations */ |
27 | #define CONFIG_ARCH_MISC_INIT | |
28 | ||
bcb55f67 AB |
29 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
30 | ||
f749db3a | 31 | /* Link Definitions */ |
a646f669 | 32 | #ifndef CONFIG_QSPI_BOOT |
b2d5ac59 SW |
33 | #ifdef CONFIG_SPL |
34 | #define CONFIG_SYS_TEXT_BASE 0x80400000 | |
35 | #else | |
f3f8c564 | 36 | #define CONFIG_SYS_TEXT_BASE 0x30100000 |
b2d5ac59 | 37 | #endif |
a646f669 | 38 | #endif |
f749db3a | 39 | |
e211c12e | 40 | #ifdef CONFIG_EMU |
f749db3a | 41 | #define CONFIG_SYS_NO_FLASH |
e211c12e | 42 | #endif |
f749db3a YS |
43 | |
44 | #define CONFIG_SUPPORT_RAW_INITRD | |
45 | ||
46 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
47 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
48 | ||
b2d5ac59 | 49 | #ifndef CONFIG_SPL |
f749db3a | 50 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ |
b2d5ac59 | 51 | #endif |
f749db3a YS |
52 | #ifndef CONFIG_SYS_FSL_DDR4 |
53 | #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ | |
54 | #define CONFIG_SYS_DDR_RAW_TIMING | |
55 | #endif | |
f749db3a YS |
56 | |
57 | #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ | |
58 | ||
9f3183d2 | 59 | #define CONFIG_VERY_BIG_RAM |
f749db3a YS |
60 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL |
61 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 | |
62 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
63 | #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL | |
d9c68b14 YS |
64 | #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 |
65 | ||
8bfa301b YS |
66 | /* |
67 | * SMP Definitinos | |
68 | */ | |
69 | #define CPU_RELEASE_ADDR secondary_boot_func | |
70 | ||
d9c68b14 | 71 | #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS |
44937214 | 72 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
d9c68b14 YS |
73 | #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL |
74 | /* | |
75 | * DDR controller use 0 as the base address for binding. | |
76 | * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. | |
77 | */ | |
78 | #define CONFIG_SYS_DP_DDR_BASE_PHY 0 | |
79 | #define CONFIG_DP_DDR_CTRL 2 | |
80 | #define CONFIG_DP_DDR_NUM_CTRLS 1 | |
44937214 | 81 | #endif |
f749db3a YS |
82 | |
83 | /* Generic Timer Definitions */ | |
207774b2 YS |
84 | /* |
85 | * This is not an accurate number. It is used in start.S. The frequency | |
86 | * will be udpated later when get_bus_freq(0) is available. | |
87 | */ | |
88 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ | |
f749db3a YS |
89 | |
90 | /* Size of malloc() pool */ | |
aa66acbf | 91 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) |
f749db3a YS |
92 | |
93 | /* I2C */ | |
f749db3a YS |
94 | #define CONFIG_SYS_I2C |
95 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
96 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
97 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e YS |
98 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
99 | #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ | |
f749db3a YS |
100 | |
101 | /* Serial Port */ | |
7288c2c2 | 102 | #define CONFIG_CONS_INDEX 1 |
f749db3a YS |
103 | #define CONFIG_SYS_NS16550_SERIAL |
104 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
105 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
106 | ||
107 | #define CONFIG_BAUDRATE 115200 | |
108 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
109 | ||
110 | /* IFC */ | |
111 | #define CONFIG_FSL_IFC | |
f3f8c564 | 112 | |
f749db3a | 113 | /* |
7288c2c2 YS |
114 | * During booting, IFC is mapped at the region of 0x30000000. |
115 | * But this region is limited to 256MB. To accommodate NOR, promjet | |
116 | * and FPGA. This region is divided as below: | |
117 | * 0x30000000 - 0x37ffffff : 128MB : NOR flash | |
118 | * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet | |
119 | * 0x3C000000 - 0x40000000 : 64MB : FPGA etc | |
120 | * | |
121 | * To accommodate bigger NOR flash and other devices, we will map IFC | |
122 | * chip selects to as below: | |
123 | * 0x5_1000_0000..0x5_1fff_ffff Memory Hole | |
124 | * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) | |
125 | * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB | |
126 | * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) | |
127 | * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) | |
128 | * | |
129 | * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. | |
f749db3a YS |
130 | * CONFIG_SYS_FLASH_BASE has the final address (core view) |
131 | * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) | |
132 | * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address | |
133 | * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting | |
134 | */ | |
7288c2c2 | 135 | |
f749db3a YS |
136 | #define CONFIG_SYS_FLASH_BASE 0x580000000ULL |
137 | #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 | |
138 | #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 | |
139 | ||
7288c2c2 YS |
140 | #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 |
141 | #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 | |
142 | ||
7288c2c2 YS |
143 | #ifndef __ASSEMBLY__ |
144 | unsigned long long get_qixis_addr(void); | |
145 | #endif | |
146 | #define QIXIS_BASE get_qixis_addr() | |
147 | #define QIXIS_BASE_PHYS 0x20000000 | |
148 | #define QIXIS_BASE_PHYS_EARLY 0xC000000 | |
8b06460e YL |
149 | #define QIXIS_STAT_PRES1 0xb |
150 | #define QIXIS_SDID_MASK 0x07 | |
151 | #define QIXIS_ESDHC_NO_ADAPTER 0x7 | |
7288c2c2 YS |
152 | |
153 | #define CONFIG_SYS_NAND_BASE 0x530000000ULL | |
154 | #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 | |
e211c12e | 155 | |
422cb08a | 156 | /* Debug Server firmware */ |
b0ba9d48 | 157 | #define CONFIG_FSL_DEBUG_SERVER |
422cb08a BS |
158 | /* 2 sec timeout */ |
159 | #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000) | |
160 | ||
f749db3a YS |
161 | /* MC firmware */ |
162 | #define CONFIG_FSL_MC_ENET | |
f749db3a | 163 | /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ |
125e2bc1 GR |
164 | #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 |
165 | #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 | |
166 | #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 | |
167 | #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 | |
3c1d218a | 168 | /* For LS2085A */ |
c1000c12 GR |
169 | #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 |
170 | #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 | |
f749db3a | 171 | |
5c055089 PK |
172 | /* |
173 | * Carve out a DDR region which will not be used by u-boot/Linux | |
174 | * | |
175 | * It will be used by MC and Debug Server. The MC region must be | |
176 | * 512MB aligned, so the min size to hide is 512MB. | |
177 | */ | |
422cb08a | 178 | #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) |
c0492141 | 179 | #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024) |
52c11d4f | 180 | #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) |
c0492141 | 181 | #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) |
f749db3a YS |
182 | #endif |
183 | ||
f3f8c564 | 184 | /* PCIe */ |
b38eaec5 RD |
185 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
186 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
187 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
188 | #define CONFIG_PCIE4 /* PCIE controller 4 */ | |
252b17e0 | 189 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ |
06b53010 | 190 | #ifdef CONFIG_LS2080A |
44937214 | 191 | #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" |
06b53010 PK |
192 | #endif |
193 | ||
f3f8c564 PK |
194 | #define CONFIG_SYS_PCI_64BIT |
195 | ||
196 | #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 | |
197 | #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ | |
198 | #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 | |
199 | #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ | |
200 | ||
201 | #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 | |
202 | #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 | |
203 | #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ | |
204 | ||
205 | #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 | |
206 | #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 | |
207 | #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ | |
208 | ||
f749db3a | 209 | /* Command line configuration */ |
f749db3a | 210 | #define CONFIG_CMD_ENV |
f749db3a YS |
211 | |
212 | /* Miscellaneous configurable options */ | |
213 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) | |
8bfa301b | 214 | #define CONFIG_ARCH_EARLY_INIT_R |
f749db3a YS |
215 | |
216 | /* Physical Memory Map */ | |
217 | /* fixme: these need to be checked against the board */ | |
218 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
f749db3a | 219 | |
d9c68b14 | 220 | #define CONFIG_NR_DRAM_BANKS 3 |
f749db3a | 221 | |
f749db3a YS |
222 | #define CONFIG_HWCONFIG |
223 | #define HWCONFIG_BUFFER_SIZE 128 | |
224 | ||
225 | #define CONFIG_DISPLAY_CPUINFO | |
226 | ||
1d3a76fa AW |
227 | /* Allow to overwrite serial and ethaddr */ |
228 | #define CONFIG_ENV_OVERWRITE | |
229 | ||
f749db3a YS |
230 | /* Initial environment variables */ |
231 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
232 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
233 | "loadaddr=0x80100000\0" \ | |
234 | "kernel_addr=0x100000\0" \ | |
235 | "ramdisk_addr=0x800000\0" \ | |
236 | "ramdisk_size=0x2000000\0" \ | |
f3f8c564 | 237 | "fdt_high=0xa0000000\0" \ |
f749db3a YS |
238 | "initrd_high=0xffffffffffffffff\0" \ |
239 | "kernel_start=0x581200000\0" \ | |
052ddd5c | 240 | "kernel_load=0xa0000000\0" \ |
97421bd2 | 241 | "kernel_size=0x2800000\0" \ |
16ed8560 PK |
242 | "console=ttyAMA0,38400n8\0" \ |
243 | "mcinitcmd=fsl_mc start mc 0x580300000" \ | |
244 | " 0x580800000 \0" | |
f749db3a | 245 | |
56cd0760 | 246 | #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ |
ed77b704 | 247 | "earlycon=uart8250,mmio,0x21c0500 " \ |
34cc7546 | 248 | "ramdisk_size=0x2000000 default_hugepagesz=2m" \ |
9e71bb9c | 249 | " hugepagesz=2m hugepages=256" |
9f3e1b8a PK |
250 | #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ |
251 | " cp.b $kernel_start $kernel_load" \ | |
252 | " $kernel_size && bootm $kernel_load" | |
f749db3a | 253 | |
f749db3a YS |
254 | /* Monitor Command Prompt */ |
255 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
f749db3a YS |
256 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
257 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
f749db3a YS |
258 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ |
259 | #define CONFIG_SYS_LONGHELP | |
260 | #define CONFIG_CMDLINE_EDITING 1 | |
f3f8c564 | 261 | #define CONFIG_AUTO_COMPLETE |
f749db3a YS |
262 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ |
263 | ||
f3f8c564 PK |
264 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
265 | ||
b2d5ac59 SW |
266 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 |
267 | #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 | |
b2d5ac59 | 268 | #define CONFIG_SPL_FRAMEWORK |
b2d5ac59 SW |
269 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" |
270 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
271 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
272 | #define CONFIG_SPL_MAX_SIZE 0x16000 | |
273 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
274 | #define CONFIG_SPL_NAND_SUPPORT | |
275 | #define CONFIG_SPL_SERIAL_SUPPORT | |
276 | #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) | |
277 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
278 | #define CONFIG_SPL_TEXT_BASE 0x1800a000 | |
279 | ||
280 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 | |
281 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST | |
282 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 | |
283 | #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 | |
74cac00c | 284 | #define CONFIG_SYS_MONITOR_LEN (640 * 1024) |
b2d5ac59 | 285 | |
34cc7546 BS |
286 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
287 | ||
bcb55f67 AB |
288 | /* Hash command with SHA acceleration supported in hardware */ |
289 | #ifdef CONFIG_FSL_CAAM | |
290 | #define CONFIG_CMD_HASH | |
291 | #define CONFIG_SHA_HW_ACCEL | |
292 | #endif | |
293 | ||
f749db3a | 294 | #endif /* __LS2_COMMON_H */ |