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rename CFG_ macros to CONFIG_SYS
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e2211743 1/*
414eec35 2 * (C) Copyright 2001-2005
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3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
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31/* External logbuffer support */
32#define CONFIG_LOGBUFFER
33
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34/*
35 * High Level Configuration Options
36 * (easy to change)
37 */
38
39#define CONFIG_MPC823 1 /* This is a MPC823E CPU */
40#define CONFIG_LWMON 1 /* ...on a LWMON board */
41
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42/* Default Ethernet MAC address */
43#define CONFIG_ETHADDR 00:11:B0:00:00:00
44
45/* The default Ethernet MAC address can be overwritten just once */
46#ifdef CONFIG_ETHADDR
47#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
48#endif
49
c837dcb1 50#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
4532cb69 51#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
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52
53#define CONFIG_LCD 1 /* use LCD controller ... */
54#define CONFIG_HLD1045 1 /* ... with a HLD1045 display */
55
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56#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
57#define CONFIG_LCD_INFO 1 /* ... and some board info */
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58#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
59
281e00a3 60#define CONFIG_SERIAL_MULTI 1
e2211743 61#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
281e00a3 62#define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */
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63
64#define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */
65
66#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
67
68#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
69
70/* pre-boot commands */
71#define CONFIG_PREBOOT "setenv bootdelay 15"
72
73#undef CONFIG_BOOTARGS
74
75/* POST support */
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76#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
77 CONFIG_SYS_POST_WATCHDOG | \
78 CONFIG_SYS_POST_RTC | \
79 CONFIG_SYS_POST_MEMORY | \
80 CONFIG_SYS_POST_CPU | \
81 CONFIG_SYS_POST_UART | \
82 CONFIG_SYS_POST_ETHER | \
83 CONFIG_SYS_POST_I2C | \
84 CONFIG_SYS_POST_SPI | \
85 CONFIG_SYS_POST_USB | \
86 CONFIG_SYS_POST_SPR | \
87 CONFIG_SYS_POST_SYSMON)
e2211743 88
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89/*
90 * Keyboard commands:
91 * # = 0x28 = ENTER : enable bootmessages on LCD
92 * 2 = 0x3A+0x3C = F1 + F3 : enable update mode
93 * 3 = 0x3C+0x3F = F3 + F6 : enable test mode
94 */
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95
96#define CONFIG_BOOTCOMMAND "autoscr 40040000;saveenv"
97
98/* "gatewayip=10.8.211.250\0" \ */
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99#define CONFIG_EXTRA_ENV_SETTINGS \
100 "kernel_addr=40080000\0" \
101 "ramdisk_addr=40280000\0" \
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102 "netmask=255.255.192.0\0" \
103 "serverip=10.8.2.101\0" \
104 "ipaddr=10.8.57.0\0" \
31a64923 105 "magic_keys=#23\0" \
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106 "key_magic#=28\0" \
107 "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
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108 "key_magic2=3A+3C\0" \
109 "key_cmd2=echo *** Entering Update Mode ***;" \
110 "if fatload ide 0:3 10000 update.scr;" \
111 "then autoscr 10000;" \
112 "else echo *** UPDATE FAILED ***;" \
113 "fi\0" \
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114 "key_magic3=3C+3F\0" \
115 "key_cmd3=echo *** Entering Test Mode ***;" \
116 "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
117 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
118 "ramargs=setenv bootargs root=/dev/ram rw\0" \
119 "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0" \
120 "addip=setenv bootargs $bootargs " \
121 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
122 "panic=1\0" \
123 "add_wdt=setenv bootargs $bootargs $wdt_args\0" \
124 "add_misc=setenv bootargs $bootargs runmode\0" \
125 "flash_nfs=run nfsargs addip add_wdt addfb add_misc;" \
126 "bootm $kernel_addr\0" \
127 "flash_self=run ramargs addip add_wdt addfb add_misc;" \
128 "bootm $kernel_addr $ramdisk_addr\0" \
129 "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \
130 "run nfsargs addip add_wdt addfb;bootm\0" \
131 "rootpath=/opt/eldk/ppc_8xx\0" \
132 "load=tftp 100000 /tftpboot/u-boot.bin\0" \
133 "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
134 "wdt_args=wdt_8xx=off\0" \
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135 "verify=no"
136
137#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf 138#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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139
140#define CONFIG_WATCHDOG 1 /* watchdog enabled */
6d0f6bcf 141#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 20)
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142
143#undef CONFIG_STATUS_LED /* Status LED disabled */
144
145/* enable I2C and select the hardware/software driver */
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146#undef CONFIG_HARD_I2C /* I2C with hardware support */
147#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
e2211743 148
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149#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
150#define CONFIG_SYS_I2C_SLAVE 0xFE
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151
152#ifdef CONFIG_SOFT_I2C
153/*
154 * Software (bit-bang) I2C driver configuration
155 */
156#define PB_SCL 0x00000020 /* PB 26 */
157#define PB_SDA 0x00000010 /* PB 27 */
158
159#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
160#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
161#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
162#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
163#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
164 else immr->im_cpm.cp_pbdat &= ~PB_SDA
165#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
166 else immr->im_cpm.cp_pbdat &= ~PB_SCL
4532cb69 167#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
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168#endif /* CONFIG_SOFT_I2C */
169
170
171#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
172
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173
174/*
175 * Command line configuration.
176 */
177#include <config_cmd_default.h>
178
179#define CONFIG_CMD_ASKENV
180#define CONFIG_CMD_BMP
181#define CONFIG_CMD_BSP
182#define CONFIG_CMD_DATE
183#define CONFIG_CMD_DHCP
184#define CONFIG_CMD_EEPROM
185#define CONFIG_CMD_FAT
186#define CONFIG_CMD_I2C
187#define CONFIG_CMD_IDE
188#define CONFIG_CMD_NFS
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189#define CONFIG_CMD_SNTP
190
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191#ifdef CONFIG_POST
192#define CONFIG_CMD_DIAG
193#endif
194
9bbb1c08 195
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196#define CONFIG_MAC_PARTITION
197#define CONFIG_DOS_PARTITION
198
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199/*
200 * BOOTP options
201 */
202#define CONFIG_BOOTP_SUBNETMASK
203#define CONFIG_BOOTP_GATEWAY
204#define CONFIG_BOOTP_HOSTNAME
205#define CONFIG_BOOTP_BOOTPATH
206#define CONFIG_BOOTP_BOOTFILESIZE
e2211743 207
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208
209/*
210 * Miscellaneous configurable options
211 */
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212#define CONFIG_SYS_LONGHELP /* undef to save memory */
213#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
e2211743 214
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215#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
216#ifdef CONFIG_SYS_HUSH_PARSER
217#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
f12e568c 218#endif
e2211743 219
9bbb1c08 220#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 221#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
e2211743 222#else
6d0f6bcf 223#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e2211743 224#endif
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225#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
226#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
227#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
e2211743 228
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229#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
230#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
e2211743 231
6d0f6bcf 232#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
e2211743 233
6d0f6bcf 234#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
e2211743 235
6d0f6bcf 236#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
e2211743 237
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238/*
239 * When the watchdog is enabled, output must be fast enough in Linux.
240 */
241#ifdef CONFIG_WATCHDOG
6d0f6bcf 242#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 57600, 115200 }
d0fb80c3 243#else
6d0f6bcf 244#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
d0fb80c3 245#endif
e2211743 246
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247/*----------------------------------------------------------------------*/
248#define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */
249#undef CONFIG_MODEM_SUPPORT_DEBUG
250
ad12965d 251#define CONFIG_MODEM_KEY_MAGIC "3C+3D" /* press F3 + F4 keys to enable modem */
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252#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
253#if 0
254#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
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255#define CONFIG_AUTOBOOT_PROMPT \
256 "\nEnter password - autoboot in %d sec...\n", bootdelay
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257#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
258#endif
259/*----------------------------------------------------------------------*/
260
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261/*
262 * Low Level Configuration Settings
263 * (address mappings, register initial values, etc.)
264 * You should know what you are doing if you make changes here.
265 */
266/*-----------------------------------------------------------------------
267 * Internal Memory Mapped Register
268 */
6d0f6bcf 269#define CONFIG_SYS_IMMR 0xFFF00000
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270
271/*-----------------------------------------------------------------------
272 * Definitions for initial stack pointer and data area (in DPRAM)
273 */
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274#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
275#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
276#define CONFIG_SYS_GBL_DATA_SIZE 68 /* size in bytes reserved for initial data */
277#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
278#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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279
280/*-----------------------------------------------------------------------
281 * Start addresses for the final memory configuration
282 * (Set up by the startup code)
6d0f6bcf 283 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
e2211743 284 */
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285#define CONFIG_SYS_SDRAM_BASE 0x00000000
286#define CONFIG_SYS_FLASH_BASE 0x40000000
e4dbe1b2 287#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
6d0f6bcf 288#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
e2211743 289#else
6d0f6bcf 290#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
e2211743 291#endif
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292#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
293#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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294
295/*
296 * For booting Linux, the board info and command line data
297 * have to be in the first 8 MB of memory, since this is
298 * the maximum mapped by the Linux kernel during initialization.
299 */
6d0f6bcf 300#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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301/*-----------------------------------------------------------------------
302 * FLASH organization
303 */
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304#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
305#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
e2211743 306
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307#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
308#define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
309#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
310#define CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT 2048 /* Timeout for Flash Buffer Write (in ms) */
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311/* Buffer size.
312 We have two flash devices connected in parallel.
313 Each device incorporates a Write Buffer of 32 bytes.
314 */
6d0f6bcf 315#define CONFIG_SYS_FLASH_BUFFER_SIZE (2*32)
e2211743 316
31a64923 317/* Put environment in flash which is much faster to boot than using the EEPROM */
5a1aceb0 318#define CONFIG_ENV_IS_IN_FLASH 1
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319#define CONFIG_ENV_ADDR 0x40040000 /* Address of Environment Sector */
320#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */
321#define CONFIG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */
31a64923 322
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323/*-----------------------------------------------------------------------
324 * I2C/EEPROM Configuration
325 */
326
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327#define CONFIG_SYS_I2C_AUDIO_ADDR 0x28 /* Audio volume control */
328#define CONFIG_SYS_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */
329#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
330#define CONFIG_SYS_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */
331#define CONFIG_SYS_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */
332#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
333#define CONFIG_SYS_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */
e2211743 334
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335#undef CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */
336
e2211743 337#ifdef CONFIG_USE_FRAM /* use FRAM */
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338#define CONFIG_SYS_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */
339#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
e2211743 340#else /* use EEPROM */
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341#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
342#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
343#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
e2211743 344#endif /* CONFIG_USE_FRAM */
6d0f6bcf 345#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
e2211743 346
6aff3115 347/* List of I2C addresses to be verified by POST */
288b3d7f 348#ifdef CONFIG_USE_FRAM
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349#define I2C_ADDR_LIST { /* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
350 CONFIG_SYS_I2C_SYSMON_ADDR, \
351 CONFIG_SYS_I2C_RTC_ADDR, \
352 CONFIG_SYS_I2C_POWER_A_ADDR, \
353 CONFIG_SYS_I2C_POWER_B_ADDR, \
354 CONFIG_SYS_I2C_KEYBD_ADDR, \
355 CONFIG_SYS_I2C_PICIO_ADDR, \
356 CONFIG_SYS_I2C_EEPROM_ADDR, \
6aff3115 357 }
288b3d7f 358#else /* Use EEPROM - which show up on 8 consequtive addresses */
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359#define I2C_ADDR_LIST { /* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
360 CONFIG_SYS_I2C_SYSMON_ADDR, \
361 CONFIG_SYS_I2C_RTC_ADDR, \
362 CONFIG_SYS_I2C_POWER_A_ADDR, \
363 CONFIG_SYS_I2C_POWER_B_ADDR, \
364 CONFIG_SYS_I2C_KEYBD_ADDR, \
365 CONFIG_SYS_I2C_PICIO_ADDR, \
366 CONFIG_SYS_I2C_EEPROM_ADDR+0, \
367 CONFIG_SYS_I2C_EEPROM_ADDR+1, \
368 CONFIG_SYS_I2C_EEPROM_ADDR+2, \
369 CONFIG_SYS_I2C_EEPROM_ADDR+3, \
370 CONFIG_SYS_I2C_EEPROM_ADDR+4, \
371 CONFIG_SYS_I2C_EEPROM_ADDR+5, \
372 CONFIG_SYS_I2C_EEPROM_ADDR+6, \
373 CONFIG_SYS_I2C_EEPROM_ADDR+7, \
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374 }
375#endif /* CONFIG_USE_FRAM */
6aff3115 376
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377/*-----------------------------------------------------------------------
378 * Cache Configuration
379 */
6d0f6bcf 380#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
9bbb1c08 381#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 382#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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383#endif
384
385/*-----------------------------------------------------------------------
386 * SYPCR - System Protection Control 11-9
387 * SYPCR can only be written once after reset!
388 *-----------------------------------------------------------------------
389 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
390 */
391#if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */
6d0f6bcf 392#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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393 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
394#else
6d0f6bcf 395#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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396#endif
397
398/*-----------------------------------------------------------------------
399 * SIUMCR - SIU Module Configuration 11-6
400 *-----------------------------------------------------------------------
401 * PCMCIA config., multi-function pin tri-state
402 */
403/* EARB, DBGC and DBPC are initialised by the HCW */
404/* => 0x000000C0 */
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405#define CONFIG_SYS_SIUMCR (SIUMCR_GB5E)
406/*#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
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407
408/*-----------------------------------------------------------------------
409 * TBSCR - Time Base Status and Control 11-26
410 *-----------------------------------------------------------------------
411 * Clear Reference Interrupt Status, Timebase freezing enabled
412 */
6d0f6bcf 413#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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414
415/*-----------------------------------------------------------------------
416 * PISCR - Periodic Interrupt Status and Control 11-31
417 *-----------------------------------------------------------------------
418 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
419 */
6d0f6bcf 420#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
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421
422/*-----------------------------------------------------------------------
423 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
424 *-----------------------------------------------------------------------
425 * Reset PLL lock status sticky bit, timer expired status bit and timer
426 * interrupt status bit, set PLL multiplication factor !
427 */
428/* 0x00405000 */
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429#define CONFIG_SYS_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */
430#define CONFIG_SYS_PLPRCR \
431 ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
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432 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
433 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
434 PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
435 )
436
6d0f6bcf 437#define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*13200000)
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438
439/*-----------------------------------------------------------------------
440 * SCCR - System Clock and reset Control Register 15-27
441 *-----------------------------------------------------------------------
442 * Set clock output, timebase and RTC source and divider,
443 * power management and some other internal clocks
444 */
445#define SCCR_MASK SCCR_EBDF11
446/* 0x01800000 */
6d0f6bcf 447#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
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448 SCCR_RTDIV | SCCR_RTSEL | \
449 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
450 SCCR_EBDF00 | SCCR_DFSYNC00 | \
451 SCCR_DFBRG00 | SCCR_DFNL000 | \
452 SCCR_DFNH000 | SCCR_DFLCD100 | \
453 SCCR_DFALCD01)
454
455/*-----------------------------------------------------------------------
456 * RTCSC - Real-Time Clock Status and Control Register 11-27
457 *-----------------------------------------------------------------------
458 */
459/* 0x00C3 => 0x0003 */
6d0f6bcf 460#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
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461
462
463/*-----------------------------------------------------------------------
464 * RCCR - RISC Controller Configuration Register 19-4
465 *-----------------------------------------------------------------------
466 */
6d0f6bcf 467#define CONFIG_SYS_RCCR 0x0000
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468
469/*-----------------------------------------------------------------------
470 * RMDS - RISC Microcode Development Support Control Register
471 *-----------------------------------------------------------------------
472 */
6d0f6bcf 473#define CONFIG_SYS_RMDS 0
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474
475/*-----------------------------------------------------------------------
476 *
477 * Interrupt Levels
478 *-----------------------------------------------------------------------
479 */
6d0f6bcf 480#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
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481
482/*-----------------------------------------------------------------------
483 * PCMCIA stuff
484 *-----------------------------------------------------------------------
485 *
486 */
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487#define CONFIG_SYS_PCMCIA_MEM_ADDR (0x50000000)
488#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
489#define CONFIG_SYS_PCMCIA_DMA_ADDR (0x54000000)
490#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
491#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0x58000000)
492#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
493#define CONFIG_SYS_PCMCIA_IO_ADDR (0x5C000000)
494#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
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495
496/*-----------------------------------------------------------------------
497 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
498 *-----------------------------------------------------------------------
499 */
500
501#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
502
503#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
504#undef CONFIG_IDE_LED /* LED for ide not supported */
505#undef CONFIG_IDE_RESET /* reset for ide not supported */
506
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507#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
508#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
e2211743 509
6d0f6bcf 510#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
e2211743 511
6d0f6bcf 512#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
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513
514/* Offset for data I/O */
6d0f6bcf 515#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
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516
517/* Offset for normal register accesses */
6d0f6bcf 518#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
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519
520/* Offset for alternate registers */
6d0f6bcf 521#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
e2211743 522
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523#define CONFIG_SUPPORT_VFAT /* enable VFAT support */
524
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525/*-----------------------------------------------------------------------
526 *
527 *-----------------------------------------------------------------------
528 *
529 */
6d0f6bcf 530#define CONFIG_SYS_DER 0
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531
532/*
533 * Init Memory Controller:
534 *
535 * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
536 */
537
538#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
539#define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */
540
541/* used to re-map FLASH:
542 * restrict access enough to keep SRAM working (if any)
543 * but not too much to meddle with FLASH accesses
544 */
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545#define CONFIG_SYS_REMAP_OR_AM 0xFF000000 /* OR addr mask */
546#define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
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547
548/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
6d0f6bcf 549#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK)
e2211743 550
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551#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
552 CONFIG_SYS_OR_TIMING_FLASH)
553#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
554 CONFIG_SYS_OR_TIMING_FLASH)
e2211743 555/* 16 bit, bank valid */
6d0f6bcf 556#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
e2211743 557
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558#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
559#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
560#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
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561
562/*
563 * BR3/OR3: SDRAM
564 *
565 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
566 */
567#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
568#define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */
569#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
570
571#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */
572
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573#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
574#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
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575
576/*
577 * BR5/OR5: Touch Panel
578 *
579 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
580 */
581#define TOUCHPNL_BASE 0x20000000
582#define TOUCHPNL_OR_AM 0xFFFF8000
583#define TOUCHPNL_TIMING OR_SCY_0_CLK
584
6d0f6bcf 585#define CONFIG_SYS_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
e2211743 586 TOUCHPNL_TIMING )
6d0f6bcf 587#define CONFIG_SYS_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
e2211743 588
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589#define CONFIG_SYS_MEMORY_75
590#undef CONFIG_SYS_MEMORY_7E
591#undef CONFIG_SYS_MEMORY_8E
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592
593/*
594 * Memory Periodic Timer Prescaler
595 */
596
597/* periodic timer for refresh */
6d0f6bcf 598#define CONFIG_SYS_MPTPR 0x200
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599
600/*
601 * MAMR settings for SDRAM
602 */
603
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604#define CONFIG_SYS_MAMR_8COL 0x80802114
605#define CONFIG_SYS_MAMR_9COL 0x80904114
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606
607/*
608 * MAR setting for SDRAM
609 */
6d0f6bcf 610#define CONFIG_SYS_MAR 0x00000088
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611
612/*
613 * Internal Definitions
614 *
615 * Boot Flags
616 */
617#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
618#define BOOTFLAG_WARM 0x02 /* Software reboot */
619
620#endif /* __CONFIG_H */