[people/ms/u-boot.git] / include / configs / malta.h

/*
 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#ifndef _MALTA_CONFIG_H
#define _MALTA_CONFIG_H

/*
 * System configuration
 */
#define CONFIG_MALTA

#define CONFIG_MEMSIZE_IN_BYTES

#define CONFIG_PCI_GT64120
#define CONFIG_PCI_MSC01
#define CONFIG_PCNET
#define CONFIG_PCNET_79C973
#define PCNET_HAS_PROM

#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_MC146818
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0

/*
 * CPU Configuration
 */
#define CONFIG_SYS_MHZ			250	/* arbitrary value */
#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)

/*
 * Memory map
 */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE

#ifdef CONFIG_64BIT
# define CONFIG_SYS_SDRAM_BASE		0xffffffff80000000
#else
# define CONFIG_SYS_SDRAM_BASE		0x80000000
#endif
#define CONFIG_SYS_MEM_SIZE		(256 * 1024 * 1024)

#define CONFIG_SYS_INIT_SP_OFFSET	0x400000

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x01000000)
#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x00100000)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x00800000)

#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
#define CONFIG_SYS_BOOTM_LEN		(64 * 1024 * 1024)

#define CONFIG_SYS_MAXARGS		16

#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING

/*
 * Serial driver
 */
#define CONFIG_SYS_NS16550_PORT_MAPPED

/*
 * Flash configuration
 */
#ifdef CONFIG_64BIT
# define CONFIG_SYS_FLASH_BASE		0xffffffffbe000000
#else
# define CONFIG_SYS_FLASH_BASE		0xbe000000
#endif
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	128
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

/*
 * Environment
 */
#define CONFIG_ENV_SECT_SIZE		0x20000
#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR \
	(CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)

/*
 * IDE/ATA
 */
#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	2
#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_ISA_IO_BASE_ADDRESS
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01f0
#define CONFIG_SYS_ATA_DATA_OFFSET	0
#define CONFIG_SYS_ATA_REG_OFFSET	0

/*
 * Commands
 */

#define CONFIG_SYS_LONGHELP		/* verbose help, undef to save memory */

#endif /* _MALTA_CONFIG_H */
Commit	Line	Data
5a4dcfac GJ	1	/*
	2	* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
	3	*
0b17998e	4	* SPDX-License-Identifier: GPL-2.0
5a4dcfac GJ	5	*/
5a4dcfac GJ	6
7a9d109b PB	7	#ifndef _MALTA_CONFIG_H
7a9d109b PB	8	#define _MALTA_CONFIG_H
5a4dcfac	9
5a4dcfac GJ	10	/*
	11	* System configuration
	12	*/
7a9d109b	13	#define CONFIG_MALTA
5a4dcfac	14
ab41305d GJ	15	#define CONFIG_MEMSIZE_IN_BYTES
ab41305d GJ	16
feaa6066	17	#define CONFIG_PCI_GT64120
baf37f06	18	#define CONFIG_PCI_MSC01
f1957499	19	#define CONFIG_PCNET
e0878af8 PB	20	#define CONFIG_PCNET_79C973
e0878af8 PB	21	#define PCNET_HAS_PROM
feaa6066	22
3ced12a0 PB	23	#define CONFIG_MISC_INIT_R
	24	#define CONFIG_RTC_MC146818
	25	#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
	26
5a4dcfac GJ	27	/*
	28	* CPU Configuration
	29	*/
	30	#define CONFIG_SYS_MHZ 250 /* arbitrary value */
	31	#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
5a4dcfac	32
5a4dcfac GJ	33	/*
	34	* Memory map
	35	*/
10473d04	36	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
5a4dcfac	37
0f832b9c PB	38	#ifdef CONFIG_64BIT
	39	# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
	40	#else
	41	# define CONFIG_SYS_SDRAM_BASE 0x80000000
	42	#endif
5a4dcfac GJ	43	#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024)
	44
	45	#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
	46
0f832b9c PB	47	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000)
	48	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
	49	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x00800000)
5a4dcfac GJ	50
	51	#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
	52	#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
67d4752d	53	#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
5a4dcfac	54
5a4dcfac GJ	55	#define CONFIG_SYS_MAXARGS 16
	56
	57	#define CONFIG_AUTO_COMPLETE
	58	#define CONFIG_CMDLINE_EDITING
	59
	60	/*
	61	* Serial driver
	62	*/
2e7eb12e	63	#define CONFIG_SYS_NS16550_PORT_MAPPED
5a4dcfac	64
5a4dcfac GJ	65	/*
	66	* Flash configuration
	67	*/
0f832b9c PB	68	#ifdef CONFIG_64BIT
	69	# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000
	70	#else
	71	# define CONFIG_SYS_FLASH_BASE 0xbe000000
	72	#endif
52caee0f GJ	73	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	74	#define CONFIG_SYS_MAX_FLASH_SECT 128
	75	#define CONFIG_SYS_FLASH_CFI
	76	#define CONFIG_FLASH_CFI_DRIVER
	77	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
5a4dcfac	78
fba6f45c PB	79	/*
	80	* Environment
	81	*/
fba6f45c PB	82	#define CONFIG_ENV_SECT_SIZE 0x20000
	83	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	84	#define CONFIG_ENV_ADDR \
	85	(CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
	86
ba21a453 PB	87	/*
	88	* IDE/ATA
	89	*/
	90	#define CONFIG_SYS_IDE_MAXBUS 1
	91	#define CONFIG_SYS_IDE_MAXDEVICE 2
	92	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
	93	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0
	94	#define CONFIG_SYS_ATA_DATA_OFFSET 0
	95	#define CONFIG_SYS_ATA_REG_OFFSET 0
	96
5a4dcfac GJ	97	/*
	98	* Commands
	99	*/
feaa6066	100
5a4dcfac GJ	101	#define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */
5a4dcfac GJ	102
7a9d109b	103	#endif /* _MALTA_CONFIG_H */