[people/ms/u-boot.git] / include / configs / mcc200.h

/*
 * (C) Copyright 2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
#define CONFIG_MCC200		1	/* ... on MCC200 board			*/

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz		*/

#define CONFIG_MISC_INIT_R

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH 	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot	     		*/

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs 			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value 	*/
#endif

/*
 * Serial console configuration
 *
 *  To select console on the one of 8 external UARTs,
 * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
 * or as 5, 6, 7, or 8 for the second Quad UART.
 * COM11, COM12, COM13, COM14 are located on the second Quad UART.
 *
 *  CONFIG_PSC_CONSOLE must be undefined in this case.
 */
#if !defined(CONFIG_PRS200)
/* MCC200 configuration: */
#ifdef CONFIG_CONSOLE_COM12
#define CONFIG_QUART_CONSOLE	6	/* console is on UARTF of QUART2	*/
#else
#define CONFIG_QUART_CONSOLE	8	/* console is on UARTH of QUART2	*/
#endif
#else
/* PRS200 configuration: */
#undef CONFIG_QUART_CONSOLE
#endif /* CONFIG_PRS200 */
/*
 *  To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
 * and undefine CONFIG_QUART_CONSOLE.
 */
#if !defined(CONFIG_PRS200)
/* MCC200 configuration: */
#undef CONFIG_PSC_CONSOLE
#else
/* PRS200 configuration: */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1		*/
#endif
#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE)
#error "Select only one console device!"
#endif
#define CONFIG_BAUDRATE		115200
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CONFIG_MII		1

#define CONFIG_DOS_PARTITION

/* USB */
#define CONFIG_USB_OHCI
#define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE

/*
 * Supported commands
 */
#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				ADD_USB_CMD	| \
				CFG_CMD_BEDBUG	| \
				CFG_CMD_FAT	| \
				CFG_CMD_I2C)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define XMK_STR(x)	#x
#define MK_STR(x)	XMK_STR(x)

#ifdef CONFIG_PRS200
# define CFG__BOARDNAME "prs200"
#else
# define CFG__BOARDNAME "mcc200"
#endif

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=" CFG__BOARDNAME "\0"					\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addcons=etenv bootargs ${bootargs} "				\
		"console=${console},${baudrate}\0"			\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addcons;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};"				\
		"run nfsargs addip addcons;bootm\0"			\
	"console=ttyS0\0"						\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0"		\
	"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0"	\
	"text_base=" MK_STR(TEXT_BASE) "\0"				\
	"update=protect off ${text_base} +${filesize};"			\
		"era ${text_base} +${filesize};"			\
		"cp.b 200000 ${text_base} ${filesize}\0"		\
	"unlock=yes\0"							\
	""
#undef MK_STR
#undef XMK_STR

#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
#define CFG_PROMPT_HUSH_PS2	"> "

/*
 * IPB Bus clocking configuration.
 */
#define CFG_IPBSPEED_133   		/* define for 133MHz speed */

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */

#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * Flash configuration (8,16 or 32 MB)
 * TEXT base always at 0xFFF00000
 * ENV_ADDR always at  0xFFF40000
 * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
 *               0xFE000000 for 32 MB
 *               0xFF000000 for 16 MB
 *               0xFF800000 for  8 MB
 */
#define CFG_FLASH_BASE		0xfc000000
#define CFG_FLASH_SIZE		0x04000000

#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/

#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CFG_FLASH_PROTECTION	1	/* hardware flash protection		*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/

#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/

#define CFG_ENV_SECT_SIZE	0x40000 	/* size of one complete sector	*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */

#if TEXT_BASE == CFG_FLASH_BASE
#define CFG_LOWBOOT	1
#endif

/*
 * Memory map
 */
#define CFG_MBAR		0xf0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		1

/*
 * GPIO configuration
 */
/* 0x10000004 = 32MB SDRAM */
/* 0x90000004 = 64MB SDRAM */
#define CFG_GPS_PORT_CONFIG	0x00000004

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

/*
 * Various low-level settings
 */
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG		0x0004fb00
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
#define CFG_CS2_START		0x80000000
#define CFG_CS2_SIZE		0x00001000
#define CFG_CS2_CFG		0x1d300

/* Second Quad UART @0x80010000 */
#define CFG_CS1_START		0x80010000
#define CFG_CS1_SIZE		0x00001000
#define CFG_CS1_CFG		0x1d300

/*
 *  Select one of quarts as a default
 * console. If undefined - PSC console
 * wil be default
 */
#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

#define CFG_RESET_ADDRESS	0xff000000

/*
 * QUART Expanders support
 */
#if defined(CONFIG_QUART_CONSOLE)
/*
 * We'll use NS16550 chip routines,
 */
#define CFG_NS16550		1
#define CFG_NS16550_SERIAL	1
#define CONFIG_CONS_INDEX	1
/*
 *  To achieve necessary offset on SC16C554
 * A0-A2 (register select) pins with NS16550
 * functions (in struct NS16550), REG_SIZE
 * should be 4, because A0-A2 pins are connected
 * to DA2-DA4 address bus lines.
 */
#define CFG_NS16550_REG_SIZE	4
/*
 * LocalPlus Bus already inited in cpu_init_f(),
 * so can work with QUART's chip selects.
 * One of four SC16C554 UARTs is selected with
 * A3-A4 (DA5-DA6) lines.
 */
#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
#define CFG_NS16550_COM1	(CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
#define CFG_NS16550_COM1	(CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
#elif
#error "Wrong QUART expander number."
#endif

/*
 * SC16C554 chip's external crystal oscillator frequency
 * is 7.3728 MHz
 */
#define CFG_NS16550_CLK		7372800
#endif /* CONFIG_QUART_CONSOLE */
/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00005000

#endif /* __CONFIG_H */
Commit	Line	Data
86ea5f93 WD	1	/*
	2	* (C) Copyright 2006
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
	32	#define CONFIG_MPC5200
	33	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	34	#define CONFIG_MCC200 1 /* ... on MCC200 board */
	35
	36	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
	37
	38	#define CONFIG_MISC_INIT_R
	39
	40	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	41	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	42
	43	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	44	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	45	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	46	#endif
	47
	48	/*
	49	* Serial console configuration
87791f3b WD	50	*
	51	* To select console on the one of 8 external UARTs,
	52	* define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
	53	* or as 5, 6, 7, or 8 for the second Quad UART.
463764c8	54	* COM11, COM12, COM13, COM14 are located on the second Quad UART.
87791f3b WD	55	*
	56	* CONFIG_PSC_CONSOLE must be undefined in this case.
	57	*/
ed1cf845 WD	58	#if !defined(CONFIG_PRS200)
ed1cf845 WD	59	/* MCC200 configuration: */
463764c8 WD	60	#ifdef CONFIG_CONSOLE_COM12
	61	#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */
	62	#else
	63	#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */
	64	#endif
ed1cf845 WD	65	#else
	66	/* PRS200 configuration: */
	67	#undef CONFIG_QUART_CONSOLE
	68	#endif /* CONFIG_PRS200 */
87791f3b WD	69	/*
	70	* To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
	71	* and undefine CONFIG_QUART_CONSOLE.
86ea5f93	72	*/
ed1cf845 WD	73	#if !defined(CONFIG_PRS200)
	74	/* MCC200 configuration: */
	75	#undef CONFIG_PSC_CONSOLE
	76	#else
	77	/* PRS200 configuration: */
	78	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	79	#endif
87791f3b WD	80	#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE)
	81	#error "Select only one console device!"
	82	#endif
86ea5f93 WD	83	#define CONFIG_BAUDRATE 115200
	84	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	85
86ea5f93	86	#define CONFIG_MII 1
86ea5f93	87
86ea5f93 WD	88	#define CONFIG_DOS_PARTITION
	89
	90	/* USB */
86ea5f93 WD	91	#define CONFIG_USB_OHCI
	92	#define ADD_USB_CMD CFG_CMD_USB \| CFG_CMD_FAT
	93	#define CONFIG_USB_STORAGE
86ea5f93 WD	94
	95	/*
	96	* Supported commands
	97	*/
	98	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
86ea5f93 WD	99	ADD_USB_CMD \| \
86ea5f93 WD	100	CFG_CMD_BEDBUG \| \
86ea5f93	101	CFG_CMD_FAT \| \
5725f94a	102	CFG_CMD_I2C)
86ea5f93 WD	103
	104	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	105	#include <cmd_confdefs.h>
	106
	107	/*
	108	* Autobooting
	109	*/
	110	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	111
	112	#define CONFIG_PREBOOT "echo;" \
	113	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	114	"echo"
	115
	116	#undef CONFIG_BOOTARGS
	117
ed1cf845 WD	118	#define XMK_STR(x) #x
	119	#define MK_STR(x) XMK_STR(x)
	120
	121	#ifdef CONFIG_PRS200
	122	# define CFG__BOARDNAME "prs200"
	123	#else
	124	# define CFG__BOARDNAME "mcc200"
	125	#endif
	126
	127	#define CONFIG_EXTRA_ENV_SETTINGS \
86ea5f93	128	"netdev=eth0\0" \
ed1cf845	129	"hostname=" CFG__BOARDNAME "\0" \
86ea5f93 WD	130	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	131	"nfsroot=${serverip}:${rootpath}\0" \
	132	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	133	"addip=setenv bootargs ${bootargs} " \
	134	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	135	":${hostname}:${netdev}:off panic=1\0" \
ed1cf845 WD	136	"addcons=etenv bootargs ${bootargs} " \
	137	"console=${console},${baudrate}\0" \
	138	"flash_nfs=run nfsargs addip addcons;" \
86ea5f93	139	"bootm ${kernel_addr}\0" \
ed1cf845	140	"flash_self=run ramargs addip addcons;" \
86ea5f93	141	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
ed1cf845 WD	142	"net_nfs=tftp 200000 ${bootfile};" \
	143	"run nfsargs addip addcons;bootm\0" \
	144	"console=ttyS0\0" \
82f2e33a	145	"rootpath=/opt/eldk/ppc_6xx\0" \
ed1cf845 WD	146	"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \
	147	"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \
	148	"text_base=" MK_STR(TEXT_BASE) "\0" \
	149	"update=protect off ${text_base} +${filesize};" \
	150	"era ${text_base} +${filesize};" \
	151	"cp.b 200000 ${text_base} ${filesize}\0" \
58ad4978	152	"unlock=yes\0" \
86ea5f93	153	""
ed1cf845 WD	154	#undef MK_STR
ed1cf845 WD	155	#undef XMK_STR
86ea5f93 WD	156
	157	#define CONFIG_BOOTCOMMAND "run flash_self"
	158
82f2e33a WD	159	#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
	160	#define CFG_PROMPT_HUSH_PS2 "> "
	161
86ea5f93 WD	162	/*
	163	* IPB Bus clocking configuration.
	164	*/
82f2e33a	165	#define CFG_IPBSPEED_133 /* define for 133MHz speed */
86ea5f93	166
86ea5f93 WD	167	/*
	168	* I2C configuration
	169	*/
	170	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
5725f94a	171	#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
86ea5f93 WD	172
	173	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	174	#define CFG_I2C_SLAVE 0x7F
	175
86ea5f93 WD	176	/*
	177	* Flash configuration (8,16 or 32 MB)
	178	* TEXT base always at 0xFFF00000
	179	* ENV_ADDR always at 0xFFF40000
58ad4978 SR	180	* FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
58ad4978 SR	181	* 0xFE000000 for 32 MB
86ea5f93 WD	182	* 0xFF000000 for 16 MB
	183	* 0xFF800000 for 8 MB
	184	*/
58ad4978 SR	185	#define CFG_FLASH_BASE 0xfc000000
58ad4978 SR	186	#define CFG_FLASH_SIZE 0x04000000
86ea5f93	187
58ad4978 SR	188	#define CFG_FLASH_CFI /* The flash is CFI compatible */
58ad4978 SR	189	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
86ea5f93	190
58ad4978	191	#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
86ea5f93	192
58ad4978 SR	193	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
58ad4978 SR	194	#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
86ea5f93	195
58ad4978 SR	196	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
58ad4978 SR	197	#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
86ea5f93	198
58ad4978 SR	199	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
58ad4978 SR	200	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
86ea5f93	201
58ad4978 SR	202	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	203	#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
	204
	205	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
	206
	207	#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
	208	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
	209	#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
	210
	211	/* Address and size of Redundant Environment Sector */
	212	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
	213	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	214
	215	#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
86ea5f93	216
f149d864 WD	217	#if TEXT_BASE == CFG_FLASH_BASE
	218	#define CFG_LOWBOOT 1
	219	#endif
	220
86ea5f93 WD	221	/*
	222	* Memory map
	223	*/
	224	#define CFG_MBAR 0xf0000000
	225	#define CFG_SDRAM_BASE 0x00000000
	226	#define CFG_DEFAULT_MBAR 0x80000000
	227
	228	/* Use SRAM until RAM will be available */
	229	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	230	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
	231
	232
	233	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	234	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	235	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	236
	237	#define CFG_MONITOR_BASE TEXT_BASE
	238	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	239	# define CFG_RAMBOOT 1
	240	#endif
	241
	242	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
58ad4978	243	#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
86ea5f93 WD	244	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	245
	246	/*
	247	* Ethernet configuration
	248	*/
	249	#define CONFIG_MPC5xxx_FEC 1
	250	/*
	251	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	252	*/
	253	/* #define CONFIG_FEC_10MBIT 1 */
58ad4978	254	#define CONFIG_PHY_ADDR 1
86ea5f93 WD	255
	256	/*
	257	* GPIO configuration
	258	*/
bfc81252 WD	259	/* 0x10000004 = 32MB SDRAM */
bfc81252 WD	260	/* 0x90000004 = 64MB SDRAM */
5725f94a	261	#define CFG_GPS_PORT_CONFIG 0x00000004
86ea5f93 WD	262
	263	/*
	264	* Miscellaneous configurable options
	265	*/
	266	#define CFG_LONGHELP /* undef to save memory */
	267	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	268	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	269	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	270	#else
	271	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	272	#endif
	273	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	274	#define CFG_MAXARGS 16 /* max number of command args */
	275	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	276
	277	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	278	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	279
	280	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	281
	282	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	283
	284	/*
	285	* Various low-level settings
	286	*/
86ea5f93 WD	287	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
86ea5f93 WD	288	#define CFG_HID0_FINAL HID0_ICE
86ea5f93	289
86ea5f93 WD	290	#define CFG_BOOTCS_START CFG_FLASH_BASE
	291	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	292	#define CFG_BOOTCS_CFG 0x0004fb00
	293	#define CFG_CS0_START CFG_FLASH_BASE
	294	#define CFG_CS0_SIZE CFG_FLASH_SIZE
86ea5f93	295
05d8dce9 WD	296	/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
	297	#define CFG_CS2_START 0x80000000
	298	#define CFG_CS2_SIZE 0x00001000
b81a4630	299	#define CFG_CS2_CFG 0x1d300
05d8dce9	300
a874c8c6 WD	301	/* Second Quad UART @0x80010000 */
	302	#define CFG_CS1_START 0x80010000
	303	#define CFG_CS1_SIZE 0x00001000
	304	#define CFG_CS1_CFG 0x1d300
	305
87791f3b WD	306	/*
	307	* Select one of quarts as a default
	308	* console. If undefined - PSC console
	309	* wil be default
	310	*/
86ea5f93 WD	311	#define CFG_CS_BURST 0x00000000
	312	#define CFG_CS_DEADCYCLE 0x33333333
	313
	314	#define CFG_RESET_ADDRESS 0xff000000
	315
87791f3b WD	316	/*
	317	* QUART Expanders support
	318	*/
	319	#if defined(CONFIG_QUART_CONSOLE)
	320	/*
	321	* We'll use NS16550 chip routines,
	322	*/
	323	#define CFG_NS16550 1
	324	#define CFG_NS16550_SERIAL 1
	325	#define CONFIG_CONS_INDEX 1
	326	/*
	327	* To achieve necessary offset on SC16C554
	328	* A0-A2 (register select) pins with NS16550
	329	* functions (in struct NS16550), REG_SIZE
	330	* should be 4, because A0-A2 pins are connected
	331	* to DA2-DA4 address bus lines.
	332	*/
	333	#define CFG_NS16550_REG_SIZE 4
	334	/*
	335	* LocalPlus Bus already inited in cpu_init_f(),
	336	* so can work with QUART's chip selects.
	337	* One of four SC16C554 UARTs is selected with
	338	* A3-A4 (DA5-DA6) lines.
	339	*/
ed1cf845	340	#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
87791f3b WD	341	#define CFG_NS16550_COM1 (CFG_CS2_START \| (CONFIG_QUART_CONSOLE - 1)<<5)
	342	#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
	343	#define CFG_NS16550_COM1 (CFG_CS1_START \| (CONFIG_QUART_CONSOLE - 5)<<5)
	344	#elif
	345	#error "Wrong QUART expander number."
	346	#endif
	347
	348	/*
	349	* SC16C554 chip's external crystal oscillator frequency
	350	* is 7.3728 MHz
	351	*/
	352	#define CFG_NS16550_CLK 7372800
	353	#endif /* CONFIG_QUART_CONSOLE */
86ea5f93 WD	354	/*-----------------------------------------------------------------------
	355	* USB stuff
	356	*-----------------------------------------------------------------------
	357	*/
	358	#define CONFIG_USB_CLOCK 0x0001BBBB
	359	#define CONFIG_USB_CONFIG 0x00005000
	360
86ea5f93	361	#endif /* __CONFIG_H */