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86ea5f93 | 1 | /* |
a99715b8 | 2 | * (C) Copyright 2006-2008 |
86ea5f93 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /* | |
28 | * High Level Configuration Options | |
29 | * (easy to change) | |
30 | */ | |
31 | ||
32 | #define CONFIG_MPC5200 | |
33 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
34 | #define CONFIG_MCC200 1 /* ... on MCC200 board */ | |
35 | ||
2ae18241 WD |
36 | /* |
37 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
38 | * 0xFC000000 boot low (standard configuration) | |
39 | * 0xFFF00000 boot high | |
40 | * 0x00100000 boot from RAM (for testing only) | |
41 | */ | |
42 | #ifndef CONFIG_SYS_TEXT_BASE | |
43 | #define CONFIG_SYS_TEXT_BASE 0xFC000000 | |
44 | #endif | |
45 | ||
6d0f6bcf | 46 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ |
86ea5f93 WD |
47 | |
48 | #define CONFIG_MISC_INIT_R | |
49 | ||
360b4103 WD |
50 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
51 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
86ea5f93 | 52 | |
31d82672 BB |
53 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
54 | ||
86ea5f93 WD |
55 | /* |
56 | * Serial console configuration | |
87791f3b WD |
57 | * |
58 | * To select console on the one of 8 external UARTs, | |
59 | * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART, | |
60 | * or as 5, 6, 7, or 8 for the second Quad UART. | |
463764c8 | 61 | * COM11, COM12, COM13, COM14 are located on the second Quad UART. |
87791f3b WD |
62 | * |
63 | * CONFIG_PSC_CONSOLE must be undefined in this case. | |
64 | */ | |
ed1cf845 WD |
65 | #if !defined(CONFIG_PRS200) |
66 | /* MCC200 configuration: */ | |
463764c8 WD |
67 | #ifdef CONFIG_CONSOLE_COM12 |
68 | #define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */ | |
69 | #else | |
70 | #define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */ | |
71 | #endif | |
ed1cf845 WD |
72 | #else |
73 | /* PRS200 configuration: */ | |
74 | #undef CONFIG_QUART_CONSOLE | |
75 | #endif /* CONFIG_PRS200 */ | |
87791f3b WD |
76 | /* |
77 | * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1 | |
78 | * and undefine CONFIG_QUART_CONSOLE. | |
86ea5f93 | 79 | */ |
ed1cf845 WD |
80 | #if !defined(CONFIG_PRS200) |
81 | /* MCC200 configuration: */ | |
0fd30252 WD |
82 | #define CONFIG_SERIAL_MULTI 1 |
83 | #define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */ | |
84 | #define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */ | |
ed1cf845 WD |
85 | #else |
86 | /* PRS200 configuration: */ | |
87 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
88 | #endif | |
0fd30252 WD |
89 | #if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \ |
90 | !defined(CONFIG_SERIAL_MULTI) | |
87791f3b WD |
91 | #error "Select only one console device!" |
92 | #endif | |
86ea5f93 | 93 | #define CONFIG_BAUDRATE 115200 |
6d0f6bcf | 94 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
86ea5f93 | 95 | |
86ea5f93 | 96 | #define CONFIG_MII 1 |
86ea5f93 | 97 | |
86ea5f93 WD |
98 | #define CONFIG_DOS_PARTITION |
99 | ||
100 | /* USB */ | |
86ea5f93 | 101 | #define CONFIG_USB_OHCI |
86ea5f93 | 102 | #define CONFIG_USB_STORAGE |
cdb97a66 AS |
103 | /* automatic software updates (see board/mcc200/auto_update.c) */ |
104 | #define CONFIG_AUTO_UPDATE 1 | |
86ea5f93 | 105 | |
5dc11a51 | 106 | |
7f5c0157 JL |
107 | /* |
108 | * BOOTP options | |
109 | */ | |
110 | #define CONFIG_BOOTP_BOOTFILESIZE | |
111 | #define CONFIG_BOOTP_BOOTPATH | |
112 | #define CONFIG_BOOTP_GATEWAY | |
113 | #define CONFIG_BOOTP_HOSTNAME | |
114 | ||
115 | ||
86ea5f93 | 116 | /* |
5dc11a51 | 117 | * Command line configuration. |
86ea5f93 | 118 | */ |
5dc11a51 JL |
119 | #include <config_cmd_default.h> |
120 | ||
121 | #define CONFIG_CMD_BEDBUG | |
122 | #define CONFIG_CMD_FAT | |
123 | #define CONFIG_CMD_I2C | |
124 | #define CONFIG_CMD_USB | |
86ea5f93 | 125 | |
a4d2636f WD |
126 | #undef CONFIG_CMD_NET |
127 | ||
86ea5f93 WD |
128 | |
129 | /* | |
130 | * Autobooting | |
131 | */ | |
a4d2636f | 132 | #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ |
86ea5f93 WD |
133 | |
134 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 135 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
86ea5f93 WD |
136 | "echo" |
137 | ||
138 | #undef CONFIG_BOOTARGS | |
139 | ||
3b0ff842 WD |
140 | #define XMK_STR(x) #x |
141 | #define MK_STR(x) XMK_STR(x) | |
ed1cf845 WD |
142 | |
143 | #ifdef CONFIG_PRS200 | |
6d0f6bcf JCPV |
144 | # define CONFIG_SYS__BOARDNAME "prs200" |
145 | # define CONFIG_SYS__LINUX_CONSOLE "ttyS0" | |
ed1cf845 | 146 | #else |
6d0f6bcf JCPV |
147 | # define CONFIG_SYS__BOARDNAME "mcc200" |
148 | # define CONFIG_SYS__LINUX_CONSOLE "ttyEU5" | |
ed1cf845 WD |
149 | #endif |
150 | ||
a4d2636f WD |
151 | /* Network */ |
152 | #define CONFIG_ETHADDR 00:17:17:ff:00:00 | |
153 | #define CONFIG_IPADDR 10.76.9.29 | |
154 | #define CONFIG_SERVERIP 10.76.9.1 | |
155 | ||
156 | #include <version.h> /* For U-Boot version */ | |
157 | ||
ed1cf845 | 158 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
a4d2636f | 159 | "ubootver=" U_BOOT_VERSION "\0" \ |
86ea5f93 | 160 | "netdev=eth0\0" \ |
6d0f6bcf | 161 | "hostname=" CONFIG_SYS__BOARDNAME "\0" \ |
86ea5f93 WD |
162 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
163 | "nfsroot=${serverip}:${rootpath}\0" \ | |
a4d2636f WD |
164 | "ramargs=setenv bootargs root=/dev/mtdblock2 " \ |
165 | "rootfstype=cramfs\0" \ | |
86ea5f93 WD |
166 | "addip=setenv bootargs ${bootargs} " \ |
167 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
168 | ":${hostname}:${netdev}:off panic=1\0" \ | |
113f64e0 | 169 | "addcons=setenv bootargs ${bootargs} " \ |
a99715b8 DZ |
170 | "console=${console},${baudrate} " \ |
171 | "ubootver=${ubootver} board=${board}\0" \ | |
ed1cf845 | 172 | "flash_nfs=run nfsargs addip addcons;" \ |
86ea5f93 | 173 | "bootm ${kernel_addr}\0" \ |
ed1cf845 | 174 | "flash_self=run ramargs addip addcons;" \ |
86ea5f93 | 175 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
ed1cf845 WD |
176 | "net_nfs=tftp 200000 ${bootfile};" \ |
177 | "run nfsargs addip addcons;bootm\0" \ | |
6d0f6bcf | 178 | "console=" CONFIG_SYS__LINUX_CONSOLE "\0" \ |
82f2e33a | 179 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
6d0f6bcf JCPV |
180 | "bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0" \ |
181 | "load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0" \ | |
14d0a02a | 182 | "text_base=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ |
a4d2636f | 183 | "kernel_addr=0xFC0C0000\0" \ |
ed1cf845 WD |
184 | "update=protect off ${text_base} +${filesize};" \ |
185 | "era ${text_base} +${filesize};" \ | |
186 | "cp.b 200000 ${text_base} ${filesize}\0" \ | |
58ad4978 | 187 | "unlock=yes\0" \ |
86ea5f93 | 188 | "" |
ed1cf845 WD |
189 | #undef MK_STR |
190 | #undef XMK_STR | |
86ea5f93 WD |
191 | |
192 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
193 | ||
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
195 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
82f2e33a | 196 | |
86ea5f93 WD |
197 | /* |
198 | * IPB Bus clocking configuration. | |
199 | */ | |
6d0f6bcf | 200 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
86ea5f93 | 201 | |
86ea5f93 WD |
202 | /* |
203 | * I2C configuration | |
204 | */ | |
205 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 206 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
86ea5f93 | 207 | |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
209 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
86ea5f93 | 210 | |
86ea5f93 WD |
211 | /* |
212 | * Flash configuration (8,16 or 32 MB) | |
213 | * TEXT base always at 0xFFF00000 | |
214 | * ENV_ADDR always at 0xFFF40000 | |
58ad4978 | 215 | * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!) |
360b4103 WD |
216 | * 0xFE000000 for 32 MB |
217 | * 0xFF000000 for 16 MB | |
218 | * 0xFF800000 for 8 MB | |
86ea5f93 | 219 | */ |
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 |
221 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 | |
86ea5f93 | 222 | |
6d0f6bcf | 223 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 224 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
86ea5f93 | 225 | |
6d0f6bcf | 226 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
86ea5f93 | 227 | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
229 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
86ea5f93 | 230 | |
6d0f6bcf JCPV |
231 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
232 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ | |
86ea5f93 | 233 | |
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
235 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
86ea5f93 | 236 | |
6d0f6bcf JCPV |
237 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
238 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
58ad4978 | 239 | |
5a1aceb0 | 240 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
58ad4978 | 241 | |
0e8d1586 | 242 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ |
6d0f6bcf | 243 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 | 244 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
58ad4978 SR |
245 | |
246 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
247 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
248 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
58ad4978 SR |
249 | |
250 | #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ | |
86ea5f93 | 251 | |
14d0a02a | 252 | #if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE |
6d0f6bcf | 253 | #define CONFIG_SYS_LOWBOOT 1 |
f149d864 WD |
254 | #endif |
255 | ||
86ea5f93 WD |
256 | /* |
257 | * Memory map | |
258 | */ | |
6d0f6bcf JCPV |
259 | #define CONFIG_SYS_MBAR 0xf0000000 |
260 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
261 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
86ea5f93 WD |
262 | |
263 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
265 | #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ | |
86ea5f93 WD |
266 | |
267 | ||
6d0f6bcf JCPV |
268 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
269 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
270 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
86ea5f93 | 271 | |
14d0a02a | 272 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
273 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
274 | # define CONFIG_SYS_RAMBOOT 1 | |
86ea5f93 WD |
275 | #endif |
276 | ||
6d0f6bcf JCPV |
277 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
278 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ | |
279 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
86ea5f93 WD |
280 | |
281 | /* | |
282 | * Ethernet configuration | |
283 | */ | |
86321fc1 BW |
284 | /* #define CONFIG_MPC5xxx_FEC 1 */ |
285 | /* #define CONFIG_MPC5xxx_FEC_MII100 */ | |
86ea5f93 | 286 | /* |
86321fc1 | 287 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
86ea5f93 | 288 | */ |
86321fc1 | 289 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
58ad4978 | 290 | #define CONFIG_PHY_ADDR 1 |
86ea5f93 | 291 | |
e8143e72 WD |
292 | /* |
293 | * LCD Splash Screen | |
294 | */ | |
360b4103 | 295 | #if !defined(CONFIG_PRS200) |
e8143e72 | 296 | #define CONFIG_LCD 1 |
638dd145 | 297 | #define CONFIG_PROGRESSBAR 1 |
360b4103 WD |
298 | #endif |
299 | ||
e8143e72 WD |
300 | #if defined(CONFIG_LCD) |
301 | #define CONFIG_SPLASH_SCREEN 1 | |
6d0f6bcf | 302 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
360b4103 | 303 | #define LCD_BPP LCD_MONOCHROME |
e8143e72 WD |
304 | #endif |
305 | ||
86ea5f93 WD |
306 | /* |
307 | * GPIO configuration | |
308 | */ | |
bfc81252 WD |
309 | /* 0x10000004 = 32MB SDRAM */ |
310 | /* 0x90000004 = 64MB SDRAM */ | |
e8143e72 WD |
311 | #if defined(CONFIG_LCD) |
312 | /* set PSC2 in UART mode */ | |
6d0f6bcf | 313 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x00000044 |
e8143e72 | 314 | #else |
6d0f6bcf | 315 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x00000004 |
e8143e72 | 316 | #endif |
86ea5f93 WD |
317 | |
318 | /* | |
319 | * Miscellaneous configurable options | |
320 | */ | |
6d0f6bcf JCPV |
321 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
322 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
5dc11a51 | 323 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 324 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
86ea5f93 | 325 | #else |
6d0f6bcf | 326 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
86ea5f93 | 327 | #endif |
6d0f6bcf JCPV |
328 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
329 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
330 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
86ea5f93 | 331 | |
6d0f6bcf JCPV |
332 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
333 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
86ea5f93 | 334 | |
6d0f6bcf | 335 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
86ea5f93 | 336 | |
6d0f6bcf | 337 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
86ea5f93 | 338 | |
6d0f6bcf | 339 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
5dc11a51 | 340 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 341 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
5dc11a51 JL |
342 | #endif |
343 | ||
86ea5f93 WD |
344 | /* |
345 | * Various low-level settings | |
346 | */ | |
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
348 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
86ea5f93 | 349 | |
6d0f6bcf JCPV |
350 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
351 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
352 | #define CONFIG_SYS_BOOTCS_CFG 0x0004fb00 | |
353 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
354 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
86ea5f93 | 355 | |
05d8dce9 | 356 | /* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ |
6d0f6bcf JCPV |
357 | #define CONFIG_SYS_CS2_START 0x80000000 |
358 | #define CONFIG_SYS_CS2_SIZE 0x00001000 | |
359 | #define CONFIG_SYS_CS2_CFG 0x1d300 | |
05d8dce9 | 360 | |
a874c8c6 | 361 | /* Second Quad UART @0x80010000 */ |
6d0f6bcf JCPV |
362 | #define CONFIG_SYS_CS1_START 0x80010000 |
363 | #define CONFIG_SYS_CS1_SIZE 0x00001000 | |
364 | #define CONFIG_SYS_CS1_CFG 0x1d300 | |
a874c8c6 | 365 | |
a4d2636f WD |
366 | /* Leica - build revision resistors */ |
367 | /* | |
6d0f6bcf JCPV |
368 | #define CONFIG_SYS_CS3_START 0x80020000 |
369 | #define CONFIG_SYS_CS3_SIZE 0x00000004 | |
370 | #define CONFIG_SYS_CS3_CFG 0x1d300 | |
a4d2636f WD |
371 | */ |
372 | ||
87791f3b WD |
373 | /* |
374 | * Select one of quarts as a default | |
375 | * console. If undefined - PSC console | |
376 | * wil be default | |
377 | */ | |
6d0f6bcf JCPV |
378 | #define CONFIG_SYS_CS_BURST 0x00000000 |
379 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
86ea5f93 | 380 | |
6d0f6bcf | 381 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
86ea5f93 | 382 | |
87791f3b WD |
383 | /* |
384 | * QUART Expanders support | |
385 | */ | |
386 | #if defined(CONFIG_QUART_CONSOLE) | |
387 | /* | |
388 | * We'll use NS16550 chip routines, | |
389 | */ | |
6d0f6bcf JCPV |
390 | #define CONFIG_SYS_NS16550 1 |
391 | #define CONFIG_SYS_NS16550_SERIAL 1 | |
87791f3b WD |
392 | #define CONFIG_CONS_INDEX 1 |
393 | /* | |
394 | * To achieve necessary offset on SC16C554 | |
395 | * A0-A2 (register select) pins with NS16550 | |
396 | * functions (in struct NS16550), REG_SIZE | |
397 | * should be 4, because A0-A2 pins are connected | |
398 | * to DA2-DA4 address bus lines. | |
399 | */ | |
6d0f6bcf | 400 | #define CONFIG_SYS_NS16550_REG_SIZE 4 |
87791f3b WD |
401 | /* |
402 | * LocalPlus Bus already inited in cpu_init_f(), | |
403 | * so can work with QUART's chip selects. | |
404 | * One of four SC16C554 UARTs is selected with | |
405 | * A3-A4 (DA5-DA6) lines. | |
406 | */ | |
ed1cf845 | 407 | #if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200) |
6d0f6bcf | 408 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) |
87791f3b | 409 | #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) |
6d0f6bcf | 410 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) |
efd988eb | 411 | #else |
87791f3b WD |
412 | #error "Wrong QUART expander number." |
413 | #endif | |
414 | ||
415 | /* | |
416 | * SC16C554 chip's external crystal oscillator frequency | |
417 | * is 7.3728 MHz | |
418 | */ | |
6d0f6bcf | 419 | #define CONFIG_SYS_NS16550_CLK 7372800 |
87791f3b | 420 | #endif /* CONFIG_QUART_CONSOLE */ |
86ea5f93 WD |
421 | /*----------------------------------------------------------------------- |
422 | * USB stuff | |
423 | *----------------------------------------------------------------------- | |
424 | */ | |
425 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
426 | #define CONFIG_USB_CONFIG 0x00005000 | |
427 | ||
a4d2636f WD |
428 | #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ |
429 | #define CONFIG_AUTOBOOT_STOP_STR "432" | |
430 | #define CONFIG_SILENT_CONSOLE 1 | |
431 | ||
86ea5f93 | 432 | #endif /* __CONFIG_H */ |