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86ea5f93 WD |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /* | |
28 | * High Level Configuration Options | |
29 | * (easy to change) | |
30 | */ | |
31 | ||
32 | #define CONFIG_MPC5200 | |
33 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
34 | #define CONFIG_MCC200 1 /* ... on MCC200 board */ | |
35 | ||
36 | #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ | |
37 | ||
38 | #define CONFIG_MISC_INIT_R | |
39 | ||
360b4103 WD |
40 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
41 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
86ea5f93 | 42 | |
86ea5f93 WD |
43 | /* |
44 | * Serial console configuration | |
87791f3b WD |
45 | * |
46 | * To select console on the one of 8 external UARTs, | |
47 | * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART, | |
48 | * or as 5, 6, 7, or 8 for the second Quad UART. | |
463764c8 | 49 | * COM11, COM12, COM13, COM14 are located on the second Quad UART. |
87791f3b WD |
50 | * |
51 | * CONFIG_PSC_CONSOLE must be undefined in this case. | |
52 | */ | |
ed1cf845 WD |
53 | #if !defined(CONFIG_PRS200) |
54 | /* MCC200 configuration: */ | |
463764c8 WD |
55 | #ifdef CONFIG_CONSOLE_COM12 |
56 | #define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */ | |
57 | #else | |
58 | #define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */ | |
59 | #endif | |
ed1cf845 WD |
60 | #else |
61 | /* PRS200 configuration: */ | |
62 | #undef CONFIG_QUART_CONSOLE | |
63 | #endif /* CONFIG_PRS200 */ | |
87791f3b WD |
64 | /* |
65 | * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1 | |
66 | * and undefine CONFIG_QUART_CONSOLE. | |
86ea5f93 | 67 | */ |
ed1cf845 WD |
68 | #if !defined(CONFIG_PRS200) |
69 | /* MCC200 configuration: */ | |
0fd30252 WD |
70 | #define CONFIG_SERIAL_MULTI 1 |
71 | #define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */ | |
72 | #define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */ | |
ed1cf845 WD |
73 | #else |
74 | /* PRS200 configuration: */ | |
75 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
76 | #endif | |
0fd30252 WD |
77 | #if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \ |
78 | !defined(CONFIG_SERIAL_MULTI) | |
87791f3b WD |
79 | #error "Select only one console device!" |
80 | #endif | |
86ea5f93 WD |
81 | #define CONFIG_BAUDRATE 115200 |
82 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
83 | ||
86ea5f93 | 84 | #define CONFIG_MII 1 |
86ea5f93 | 85 | |
86ea5f93 WD |
86 | #define CONFIG_DOS_PARTITION |
87 | ||
88 | /* USB */ | |
86ea5f93 | 89 | #define CONFIG_USB_OHCI |
86ea5f93 | 90 | #define CONFIG_USB_STORAGE |
cdb97a66 AS |
91 | /* automatic software updates (see board/mcc200/auto_update.c) */ |
92 | #define CONFIG_AUTO_UPDATE 1 | |
86ea5f93 | 93 | |
5dc11a51 | 94 | |
7f5c0157 JL |
95 | /* |
96 | * BOOTP options | |
97 | */ | |
98 | #define CONFIG_BOOTP_BOOTFILESIZE | |
99 | #define CONFIG_BOOTP_BOOTPATH | |
100 | #define CONFIG_BOOTP_GATEWAY | |
101 | #define CONFIG_BOOTP_HOSTNAME | |
102 | ||
103 | ||
86ea5f93 | 104 | /* |
5dc11a51 | 105 | * Command line configuration. |
86ea5f93 | 106 | */ |
5dc11a51 JL |
107 | #include <config_cmd_default.h> |
108 | ||
109 | #define CONFIG_CMD_BEDBUG | |
110 | #define CONFIG_CMD_FAT | |
111 | #define CONFIG_CMD_I2C | |
112 | #define CONFIG_CMD_USB | |
86ea5f93 | 113 | |
86ea5f93 WD |
114 | |
115 | /* | |
116 | * Autobooting | |
117 | */ | |
118 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
119 | ||
120 | #define CONFIG_PREBOOT "echo;" \ | |
121 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
122 | "echo" | |
123 | ||
124 | #undef CONFIG_BOOTARGS | |
125 | ||
3b0ff842 WD |
126 | #define XMK_STR(x) #x |
127 | #define MK_STR(x) XMK_STR(x) | |
ed1cf845 WD |
128 | |
129 | #ifdef CONFIG_PRS200 | |
3b0ff842 WD |
130 | # define CFG__BOARDNAME "prs200" |
131 | # define CFG__LINUX_CONSOLE "ttyS0" | |
ed1cf845 | 132 | #else |
3b0ff842 WD |
133 | # define CFG__BOARDNAME "mcc200" |
134 | # define CFG__LINUX_CONSOLE "ttyEU7" | |
ed1cf845 WD |
135 | #endif |
136 | ||
137 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
86ea5f93 | 138 | "netdev=eth0\0" \ |
ed1cf845 | 139 | "hostname=" CFG__BOARDNAME "\0" \ |
86ea5f93 WD |
140 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
141 | "nfsroot=${serverip}:${rootpath}\0" \ | |
142 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
143 | "addip=setenv bootargs ${bootargs} " \ | |
144 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
145 | ":${hostname}:${netdev}:off panic=1\0" \ | |
113f64e0 | 146 | "addcons=setenv bootargs ${bootargs} " \ |
ed1cf845 WD |
147 | "console=${console},${baudrate}\0" \ |
148 | "flash_nfs=run nfsargs addip addcons;" \ | |
86ea5f93 | 149 | "bootm ${kernel_addr}\0" \ |
ed1cf845 | 150 | "flash_self=run ramargs addip addcons;" \ |
86ea5f93 | 151 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
ed1cf845 WD |
152 | "net_nfs=tftp 200000 ${bootfile};" \ |
153 | "run nfsargs addip addcons;bootm\0" \ | |
21a9cc02 | 154 | "console=" CFG__LINUX_CONSOLE "\0" \ |
82f2e33a | 155 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
ed1cf845 WD |
156 | "bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \ |
157 | "load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \ | |
158 | "text_base=" MK_STR(TEXT_BASE) "\0" \ | |
159 | "update=protect off ${text_base} +${filesize};" \ | |
160 | "era ${text_base} +${filesize};" \ | |
161 | "cp.b 200000 ${text_base} ${filesize}\0" \ | |
58ad4978 | 162 | "unlock=yes\0" \ |
86ea5f93 | 163 | "" |
ed1cf845 WD |
164 | #undef MK_STR |
165 | #undef XMK_STR | |
86ea5f93 WD |
166 | |
167 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
168 | ||
82f2e33a WD |
169 | #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ |
170 | #define CFG_PROMPT_HUSH_PS2 "> " | |
171 | ||
86ea5f93 WD |
172 | /* |
173 | * IPB Bus clocking configuration. | |
174 | */ | |
c99512d6 | 175 | #define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
86ea5f93 | 176 | |
86ea5f93 WD |
177 | /* |
178 | * I2C configuration | |
179 | */ | |
180 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
cdb97a66 | 181 | #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
86ea5f93 WD |
182 | |
183 | #define CFG_I2C_SPEED 100000 /* 100 kHz */ | |
184 | #define CFG_I2C_SLAVE 0x7F | |
185 | ||
86ea5f93 WD |
186 | /* |
187 | * Flash configuration (8,16 or 32 MB) | |
188 | * TEXT base always at 0xFFF00000 | |
189 | * ENV_ADDR always at 0xFFF40000 | |
58ad4978 | 190 | * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!) |
360b4103 WD |
191 | * 0xFE000000 for 32 MB |
192 | * 0xFF000000 for 16 MB | |
193 | * 0xFF800000 for 8 MB | |
86ea5f93 | 194 | */ |
58ad4978 SR |
195 | #define CFG_FLASH_BASE 0xfc000000 |
196 | #define CFG_FLASH_SIZE 0x04000000 | |
86ea5f93 | 197 | |
58ad4978 SR |
198 | #define CFG_FLASH_CFI /* The flash is CFI compatible */ |
199 | #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
86ea5f93 | 200 | |
58ad4978 | 201 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
86ea5f93 | 202 | |
58ad4978 SR |
203 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
204 | #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
86ea5f93 | 205 | |
58ad4978 SR |
206 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
207 | #define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ | |
86ea5f93 | 208 | |
58ad4978 SR |
209 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
210 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
86ea5f93 | 211 | |
58ad4978 SR |
212 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
213 | #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
214 | ||
360b4103 | 215 | #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
58ad4978 | 216 | |
360b4103 | 217 | #define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ |
58ad4978 SR |
218 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
219 | #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
220 | ||
221 | /* Address and size of Redundant Environment Sector */ | |
222 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) | |
223 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
224 | ||
225 | #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ | |
86ea5f93 | 226 | |
f149d864 WD |
227 | #if TEXT_BASE == CFG_FLASH_BASE |
228 | #define CFG_LOWBOOT 1 | |
229 | #endif | |
230 | ||
86ea5f93 WD |
231 | /* |
232 | * Memory map | |
233 | */ | |
234 | #define CFG_MBAR 0xf0000000 | |
235 | #define CFG_SDRAM_BASE 0x00000000 | |
236 | #define CFG_DEFAULT_MBAR 0x80000000 | |
237 | ||
238 | /* Use SRAM until RAM will be available */ | |
239 | #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM | |
240 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ | |
241 | ||
242 | ||
243 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
244 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
245 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
246 | ||
360b4103 | 247 | #define CFG_MONITOR_BASE TEXT_BASE |
86ea5f93 WD |
248 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
249 | # define CFG_RAMBOOT 1 | |
250 | #endif | |
251 | ||
252 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
58ad4978 | 253 | #define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ |
86ea5f93 WD |
254 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
255 | ||
256 | /* | |
257 | * Ethernet configuration | |
258 | */ | |
259 | #define CONFIG_MPC5xxx_FEC 1 | |
260 | /* | |
261 | * Define CONFIG_FEC_10MBIT to force FEC at 10Mb | |
262 | */ | |
263 | /* #define CONFIG_FEC_10MBIT 1 */ | |
58ad4978 | 264 | #define CONFIG_PHY_ADDR 1 |
86ea5f93 | 265 | |
e8143e72 WD |
266 | /* |
267 | * LCD Splash Screen | |
268 | */ | |
360b4103 | 269 | #if !defined(CONFIG_PRS200) |
e8143e72 | 270 | #define CONFIG_LCD 1 |
638dd145 | 271 | #define CONFIG_PROGRESSBAR 1 |
360b4103 WD |
272 | #endif |
273 | ||
e8143e72 WD |
274 | #if defined(CONFIG_LCD) |
275 | #define CONFIG_SPLASH_SCREEN 1 | |
276 | #define CFG_CONSOLE_IS_IN_ENV 1 | |
360b4103 | 277 | #define LCD_BPP LCD_MONOCHROME |
e8143e72 WD |
278 | #endif |
279 | ||
86ea5f93 WD |
280 | /* |
281 | * GPIO configuration | |
282 | */ | |
bfc81252 WD |
283 | /* 0x10000004 = 32MB SDRAM */ |
284 | /* 0x90000004 = 64MB SDRAM */ | |
e8143e72 WD |
285 | #if defined(CONFIG_LCD) |
286 | /* set PSC2 in UART mode */ | |
287 | #define CFG_GPS_PORT_CONFIG 0x00000044 | |
288 | #else | |
5725f94a | 289 | #define CFG_GPS_PORT_CONFIG 0x00000004 |
e8143e72 | 290 | #endif |
86ea5f93 WD |
291 | |
292 | /* | |
293 | * Miscellaneous configurable options | |
294 | */ | |
360b4103 WD |
295 | #define CFG_LONGHELP /* undef to save memory */ |
296 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
5dc11a51 | 297 | #if defined(CONFIG_CMD_KGDB) |
360b4103 | 298 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
86ea5f93 | 299 | #else |
360b4103 | 300 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
86ea5f93 | 301 | #endif |
360b4103 | 302 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
86ea5f93 WD |
303 | #define CFG_MAXARGS 16 /* max number of command args */ |
304 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
305 | ||
360b4103 | 306 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
86ea5f93 WD |
307 | #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
308 | ||
309 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
310 | ||
311 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
312 | ||
5dc11a51 JL |
313 | #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
314 | #if defined(CONFIG_CMD_KGDB) | |
315 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
316 | #endif | |
317 | ||
86ea5f93 WD |
318 | /* |
319 | * Various low-level settings | |
320 | */ | |
86ea5f93 WD |
321 | #define CFG_HID0_INIT HID0_ICE | HID0_ICFI |
322 | #define CFG_HID0_FINAL HID0_ICE | |
86ea5f93 | 323 | |
86ea5f93 WD |
324 | #define CFG_BOOTCS_START CFG_FLASH_BASE |
325 | #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE | |
326 | #define CFG_BOOTCS_CFG 0x0004fb00 | |
327 | #define CFG_CS0_START CFG_FLASH_BASE | |
328 | #define CFG_CS0_SIZE CFG_FLASH_SIZE | |
86ea5f93 | 329 | |
05d8dce9 WD |
330 | /* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ |
331 | #define CFG_CS2_START 0x80000000 | |
332 | #define CFG_CS2_SIZE 0x00001000 | |
b81a4630 | 333 | #define CFG_CS2_CFG 0x1d300 |
05d8dce9 | 334 | |
a874c8c6 WD |
335 | /* Second Quad UART @0x80010000 */ |
336 | #define CFG_CS1_START 0x80010000 | |
337 | #define CFG_CS1_SIZE 0x00001000 | |
338 | #define CFG_CS1_CFG 0x1d300 | |
339 | ||
87791f3b WD |
340 | /* |
341 | * Select one of quarts as a default | |
342 | * console. If undefined - PSC console | |
343 | * wil be default | |
344 | */ | |
86ea5f93 WD |
345 | #define CFG_CS_BURST 0x00000000 |
346 | #define CFG_CS_DEADCYCLE 0x33333333 | |
347 | ||
348 | #define CFG_RESET_ADDRESS 0xff000000 | |
349 | ||
87791f3b WD |
350 | /* |
351 | * QUART Expanders support | |
352 | */ | |
353 | #if defined(CONFIG_QUART_CONSOLE) | |
354 | /* | |
355 | * We'll use NS16550 chip routines, | |
356 | */ | |
357 | #define CFG_NS16550 1 | |
358 | #define CFG_NS16550_SERIAL 1 | |
359 | #define CONFIG_CONS_INDEX 1 | |
360 | /* | |
361 | * To achieve necessary offset on SC16C554 | |
362 | * A0-A2 (register select) pins with NS16550 | |
363 | * functions (in struct NS16550), REG_SIZE | |
364 | * should be 4, because A0-A2 pins are connected | |
365 | * to DA2-DA4 address bus lines. | |
366 | */ | |
367 | #define CFG_NS16550_REG_SIZE 4 | |
368 | /* | |
369 | * LocalPlus Bus already inited in cpu_init_f(), | |
370 | * so can work with QUART's chip selects. | |
371 | * One of four SC16C554 UARTs is selected with | |
372 | * A3-A4 (DA5-DA6) lines. | |
373 | */ | |
ed1cf845 | 374 | #if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200) |
87791f3b WD |
375 | #define CFG_NS16550_COM1 (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) |
376 | #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) | |
377 | #define CFG_NS16550_COM1 (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) | |
378 | #elif | |
379 | #error "Wrong QUART expander number." | |
380 | #endif | |
381 | ||
382 | /* | |
383 | * SC16C554 chip's external crystal oscillator frequency | |
384 | * is 7.3728 MHz | |
385 | */ | |
386 | #define CFG_NS16550_CLK 7372800 | |
387 | #endif /* CONFIG_QUART_CONSOLE */ | |
86ea5f93 WD |
388 | /*----------------------------------------------------------------------- |
389 | * USB stuff | |
390 | *----------------------------------------------------------------------- | |
391 | */ | |
392 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
393 | #define CONFIG_USB_CONFIG 0x00005000 | |
394 | ||
86ea5f93 | 395 | #endif /* __CONFIG_H */ |