[people/ms/u-boot.git] / include / configs / mcc200.h

/*
 * (C) Copyright 2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
#define CONFIG_MCC200		1	/* ... on MCC200 board			*/

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz		*/

#define CONFIG_MISC_INIT_R

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH 	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot	     		*/

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs 			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value 	*/
#endif

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1			*/
#define CONFIG_BAUDRATE		115200
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#undef CONFIG_PCI_SCAN_SHOW

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_NET_MULTI	1
#define CONFIG_MII		1
#define CONFIG_EEPRO100		1
#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#undef  CONFIG_NS8382X

#define ADD_PCI_CMD 		CFG_CMD_PCI

/* Partitions */
#define CONFIG_DOS_PARTITION

/* USB */
#if 1
#define CONFIG_USB_OHCI
#define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
#else
#define ADD_USB_CMD             0
#endif

#define ADD_DOC_CMD             CFG_CMD_DOC

/*
 * Supported commands
 */
#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				ADD_DOC_CMD	| \
				ADD_PCI_CMD	| \
				ADD_USB_CMD	| \
				CFG_CMD_BEDBUG	| \
				CFG_CMD_DATE	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_EEPROM	| \
				CFG_CMD_FAT	| \
				CFG_CMD_I2C	| \
				CFG_CMD_NFS	| \
				CFG_CMD_SNTP	)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=mcc200\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/mcc200/uImage\0"				\
	"baudrate=115200\0"						\
	"load=tftp 100000 /tftpboot/mcc200/u-boot.bin\0"		\
	"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;"	\
		"cp.b 100000 fff00000 40000;"			        \
		"setenv filesize;saveenv\0"				\
	"upd=run load;run update\0"					\
	"serverip=192.168.1.1\0"					\
	"ipaddr=192.168.133.144\0"					\
	"netmask=255.255.0.0\0"						\
	"unlock=yes\0"							\
	"ethaddr=00:02:44:7d:73:3b\0"					\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CFG_I2C_EEPROM_ADDR		0x58
#define CFG_I2C_EEPROM_ADDR_LEN		1
#define CFG_EEPROM_PAGE_WRITE_BITS	4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10

/*
 * RTC configuration
 */
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR		0x51

/*
 * Disk-On-Chip configuration
 */
#define CFG_DOC_SHORT_TIMEOUT
#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/

#define CFG_DOC_SUPPORT_2000
#define CFG_DOC_SUPPORT_MILLENNIUM
#define CFG_DOC_BASE		0xE0000000
#define CFG_DOC_SIZE		0x00100000

/*
 * Flash configuration (8,16 or 32 MB)
 * TEXT base always at 0xFFF00000
 * ENV_ADDR always at  0xFFF40000
 * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
 *               0xFE000000 for 32 MB
 *               0xFF000000 for 16 MB
 *               0xFF800000 for  8 MB
 */
#define CFG_FLASH_BASE		0xfc000000
#define CFG_FLASH_SIZE		0x04000000

#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/

#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CFG_FLASH_PROTECTION	1	/* hardware flash protection		*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/

#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/

#define CFG_ENV_SECT_SIZE	0x40000 	/* size of one complete sector	*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */

/*
 * Memory map
 */
#define CFG_MBAR		0xf0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		1

/*
 * GPIO configuration
 */
//###CHD: MSB = 1 -> 64MB: funktioniert nicht: ERRATA - BUG?
//###CHD: 0x10000004 = 32MB SDRAM
//###CHD: 0x90000004 = 64MB SDRAM
#define CFG_GPS_PORT_CONFIG	0x10000004

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

/*
 * Various low-level settings
 */
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG		0x0004fb00
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE
#define CFG_CS1_START		CFG_DOC_BASE
#define CFG_CS1_SIZE		CFG_DOC_SIZE
#define CFG_CS1_CFG		0x00047800

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

#define CFG_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00005000

#endif /* __CONFIG_H */
Commit	Line	Data
86ea5f93 WD	1	/*
	2	* (C) Copyright 2006
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
	32	#define CONFIG_MPC5200
	33	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	34	#define CONFIG_MCC200 1 /* ... on MCC200 board */
	35
	36	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
	37
	38	#define CONFIG_MISC_INIT_R
	39
	40	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	41	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	42
	43	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	44	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	45	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	46	#endif
	47
	48	/*
	49	* Serial console configuration
	50	*/
	51	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	52	#define CONFIG_BAUDRATE 115200
	53	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	54
86ea5f93 WD	55	/*
	56	* PCI Mapping:
	57	* 0x40000000 - 0x4fffffff - PCI Memory
	58	* 0x50000000 - 0x50ffffff - PCI IO Space
	59	*/
86ea5f93 WD	60	#define CONFIG_PCI 1
	61	#define CONFIG_PCI_PNP 1
	62	#define CONFIG_PCI_SCAN_SHOW 1
	63	#undef CONFIG_PCI_SCAN_SHOW
	64
	65	#define CONFIG_PCI_MEM_BUS 0x40000000
	66	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	67	#define CONFIG_PCI_MEM_SIZE 0x10000000
	68
	69	#define CONFIG_PCI_IO_BUS 0x50000000
	70	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	71	#define CONFIG_PCI_IO_SIZE 0x01000000
	72
	73	#define CONFIG_NET_MULTI 1
	74	#define CONFIG_MII 1
	75	#define CONFIG_EEPRO100 1
	76	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
	77	#undef CONFIG_NS8382X
	78
	79	#define ADD_PCI_CMD CFG_CMD_PCI
	80
86ea5f93 WD	81	/* Partitions */
	82	#define CONFIG_DOS_PARTITION
	83
	84	/* USB */
	85	#if 1
	86	#define CONFIG_USB_OHCI
	87	#define ADD_USB_CMD CFG_CMD_USB \| CFG_CMD_FAT
	88	#define CONFIG_USB_STORAGE
	89	#else
	90	#define ADD_USB_CMD 0
	91	#endif
	92
86ea5f93	93	#define ADD_DOC_CMD CFG_CMD_DOC
86ea5f93 WD	94
	95	/*
	96	* Supported commands
	97	*/
	98	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	99	ADD_DOC_CMD \| \
	100	ADD_PCI_CMD \| \
	101	ADD_USB_CMD \| \
	102	CFG_CMD_BEDBUG \| \
	103	CFG_CMD_DATE \| \
	104	CFG_CMD_DHCP \| \
	105	CFG_CMD_EEPROM \| \
	106	CFG_CMD_FAT \| \
	107	CFG_CMD_I2C \| \
86ea5f93 WD	108	CFG_CMD_NFS \| \
	109	CFG_CMD_SNTP )
	110
	111	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	112	#include <cmd_confdefs.h>
	113
	114	/*
	115	* Autobooting
	116	*/
	117	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	118
	119	#define CONFIG_PREBOOT "echo;" \
	120	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	121	"echo"
	122
	123	#undef CONFIG_BOOTARGS
	124
	125	#define CONFIG_EXTRA_ENV_SETTINGS \
	126	"netdev=eth0\0" \
58ad4978	127	"hostname=mcc200\0" \
86ea5f93 WD	128	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	129	"nfsroot=${serverip}:${rootpath}\0" \
	130	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	131	"addip=setenv bootargs ${bootargs} " \
	132	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	133	":${hostname}:${netdev}:off panic=1\0" \
	134	"flash_nfs=run nfsargs addip;" \
	135	"bootm ${kernel_addr}\0" \
	136	"flash_self=run ramargs addip;" \
	137	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	138	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
58ad4978 SR	139	"rootpath=/opt/eldk/ppc_82xx\0" \
58ad4978 SR	140	"bootfile=/tftpboot/mcc200/uImage\0" \
86ea5f93	141	"baudrate=115200\0" \
58ad4978 SR	142	"load=tftp 100000 /tftpboot/mcc200/u-boot.bin\0" \
	143	"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
	144	"cp.b 100000 fff00000 40000;" \
	145	"setenv filesize;saveenv\0" \
	146	"upd=run load;run update\0" \
	147	"serverip=192.168.1.1\0" \
	148	"ipaddr=192.168.133.144\0" \
	149	"netmask=255.255.0.0\0" \
	150	"unlock=yes\0" \
	151	"ethaddr=00:02:44:7d:73:3b\0" \
86ea5f93 WD	152	""
	153
	154	#define CONFIG_BOOTCOMMAND "run flash_self"
	155
86ea5f93 WD	156	/*
	157	* IPB Bus clocking configuration.
	158	*/
	159	#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
86ea5f93	160
86ea5f93 WD	161	/*
	162	* I2C configuration
	163	*/
	164	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	165	#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	166
	167	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	168	#define CFG_I2C_SLAVE 0x7F
	169
	170	/*
	171	* EEPROM configuration
	172	*/
	173	#define CFG_I2C_EEPROM_ADDR 0x58
	174	#define CFG_I2C_EEPROM_ADDR_LEN 1
	175	#define CFG_EEPROM_PAGE_WRITE_BITS 4
	176	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
	177
	178	/*
	179	* RTC configuration
	180	*/
	181	#define CONFIG_RTC_PCF8563
	182	#define CFG_I2C_RTC_ADDR 0x51
	183
86ea5f93 WD	184	/*
	185	* Disk-On-Chip configuration
	186	*/
86ea5f93 WD	187	#define CFG_DOC_SHORT_TIMEOUT
	188	#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
	189
	190	#define CFG_DOC_SUPPORT_2000
	191	#define CFG_DOC_SUPPORT_MILLENNIUM
	192	#define CFG_DOC_BASE 0xE0000000
	193	#define CFG_DOC_SIZE 0x00100000
	194
86ea5f93 WD	195	/*
	196	* Flash configuration (8,16 or 32 MB)
	197	* TEXT base always at 0xFFF00000
	198	* ENV_ADDR always at 0xFFF40000
58ad4978 SR	199	* FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
58ad4978 SR	200	* 0xFE000000 for 32 MB
86ea5f93 WD	201	* 0xFF000000 for 16 MB
	202	* 0xFF800000 for 8 MB
	203	*/
58ad4978 SR	204	#define CFG_FLASH_BASE 0xfc000000
58ad4978 SR	205	#define CFG_FLASH_SIZE 0x04000000
86ea5f93	206
58ad4978 SR	207	#define CFG_FLASH_CFI /* The flash is CFI compatible */
58ad4978 SR	208	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
86ea5f93	209
58ad4978	210	#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
86ea5f93	211
58ad4978 SR	212	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
58ad4978 SR	213	#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
86ea5f93	214
58ad4978 SR	215	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
58ad4978 SR	216	#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
86ea5f93	217
58ad4978 SR	218	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
58ad4978 SR	219	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
86ea5f93	220
58ad4978 SR	221	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	222	#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
	223
	224	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
	225
	226	#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
	227	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
	228	#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
	229
	230	/* Address and size of Redundant Environment Sector */
	231	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
	232	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	233
	234	#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
86ea5f93 WD	235
	236	/*
	237	* Memory map
	238	*/
	239	#define CFG_MBAR 0xf0000000
	240	#define CFG_SDRAM_BASE 0x00000000
	241	#define CFG_DEFAULT_MBAR 0x80000000
	242
	243	/* Use SRAM until RAM will be available */
	244	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	245	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
	246
	247
	248	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	249	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	250	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	251
	252	#define CFG_MONITOR_BASE TEXT_BASE
	253	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	254	# define CFG_RAMBOOT 1
	255	#endif
	256
	257	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
58ad4978	258	#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
86ea5f93 WD	259	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	260
	261	/*
	262	* Ethernet configuration
	263	*/
	264	#define CONFIG_MPC5xxx_FEC 1
	265	/*
	266	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	267	*/
	268	/* #define CONFIG_FEC_10MBIT 1 */
58ad4978	269	#define CONFIG_PHY_ADDR 1
86ea5f93 WD	270
	271	/*
	272	* GPIO configuration
	273	*/
	274	//###CHD: MSB = 1 -> 64MB: funktioniert nicht: ERRATA - BUG?
	275	//###CHD: 0x10000004 = 32MB SDRAM
	276	//###CHD: 0x90000004 = 64MB SDRAM
	277	#define CFG_GPS_PORT_CONFIG 0x10000004
	278
	279	/*
	280	* Miscellaneous configurable options
	281	*/
	282	#define CFG_LONGHELP /* undef to save memory */
	283	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	284	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	285	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	286	#else
	287	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	288	#endif
	289	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	290	#define CFG_MAXARGS 16 /* max number of command args */
	291	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	292
	293	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	294	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	295
	296	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	297
	298	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	299
	300	/*
	301	* Various low-level settings
	302	*/
86ea5f93 WD	303	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
86ea5f93 WD	304	#define CFG_HID0_FINAL HID0_ICE
86ea5f93	305
86ea5f93 WD	306	#define CFG_BOOTCS_START CFG_FLASH_BASE
	307	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	308	#define CFG_BOOTCS_CFG 0x0004fb00
	309	#define CFG_CS0_START CFG_FLASH_BASE
	310	#define CFG_CS0_SIZE CFG_FLASH_SIZE
	311	#define CFG_CS1_START CFG_DOC_BASE
	312	#define CFG_CS1_SIZE CFG_DOC_SIZE
	313	#define CFG_CS1_CFG 0x00047800
86ea5f93 WD	314
	315	#define CFG_CS_BURST 0x00000000
	316	#define CFG_CS_DEADCYCLE 0x33333333
	317
	318	#define CFG_RESET_ADDRESS 0xff000000
	319
	320	/*-----------------------------------------------------------------------
	321	* USB stuff
	322	*-----------------------------------------------------------------------
	323	*/
	324	#define CONFIG_USB_CLOCK 0x0001BBBB
	325	#define CONFIG_USB_CONFIG 0x00005000
	326
86ea5f93	327	#endif /* __CONFIG_H */