[people/ms/u-boot.git] / include / configs / mcx.h

/*
 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
 *
 * Based on omap3_evm_config.h
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP			/* in a TI OMAP core */
#define CONFIG_OMAP34XX			/* which is a 34XX */
#define CONFIG_OMAP3_MCX		/* working with mcx */
#define CONFIG_OMAP_GPIO

#define MACH_TYPE_MCX			3656
#define CONFIG_MACH_TYPE	MACH_TYPE_MCX
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_SYS_CACHELINE_SIZE	64

#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

#define CONFIG_OF_LIBFDT
#define CONFIG_FIT

/*
 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
 * and older u-boot.bin with the new U-Boot SPL.
 */
#define CONFIG_SYS_TEXT_BASE		0x80008000

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
/*
 * DDR related
 */
#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION

/* EHCI */
#define CONFIG_USB_STORAGE
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_USB_ULPI
#define CONFIG_USB_ULPI_VIEWPORT_OMAP
/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	154
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO	152
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/

#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_USB
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_GPIO

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_DRIVER_OMAP34XX_I2C

/* RTC */
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR		0x68

#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access */
							/* nand at CS0 */

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
							/* NAND devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */

/* Environment information */
#define CONFIG_BOOTDELAY	10

#define CONFIG_BOOTFILE		"uImage"

#define xstr(s)	str(s)
#define str(s)	#s

/* Setup MTD for NAND on the SOM */
#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO),"	\
				"1m(u-boot),256k(env1),"		\
				"256k(env2),6m(kernel),6m(k_recovery),"	\
				"8m(fs_recovery),-(common_data)"

#define CONFIG_HOSTNAME mcx
#define CONFIG_EXTRA_ENV_SETTINGS \
	"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0"	\
	"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0"	\
	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
	"addfb=setenv bootargs ${bootargs} vram=6M "			\
		"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0"	\
	"addip_sta=setenv bootargs ${bootargs} "			\
		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
		"${netmask}:${hostname}:eth0:off\0"			\
	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
		"else run addip_sta;fi\0"				\
	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
	"addtty=setenv bootargs ${bootargs} "				\
		"console=${consoledev},${baudrate}\0"			\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"baudrate=115200\0"						\
	"consoledev=ttyO2\0"						\
	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
	"loadaddr=0x82000000\0"						\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"load_k=tftp ${loadaddr} ${bootfile}\0"				\
	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0"			\
	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
	"mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0"				\
	"mmcargs=root=/dev/mmcblk0p2 rw "				\
		"rootfstype=ext3 rootwait\0"				\
	"mmcboot=echo Booting from mmc ...; "				\
		"run mmcargs; "						\
		"run addip addtty addmtd addfb addeth addmisc;"		\
		"run loaduimage; "					\
		"bootm ${loadaddr}\0"					\
	"net_nfs=run load_k; "						\
		"run nfsargs; "						\
		"run addip addtty addmtd addfb addeth addmisc;"		\
		"bootm ${loadaddr}\0"					\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0"			\
	"uboot_addr=0x80000\0"						\
	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
	"updatemlo=nandecc hw;nand erase 0 20000;"			\
		"nand write ${loadaddr} 0 20000\0"			\
	"upd=if run load;then echo Updating u-boot;if run update;"	\
		"then echo U-Boot updated;"				\
			"else echo Error updating u-boot !;"		\
			"echo Board without bootloader !!;"		\
		"fi;"							\
		"else echo U-Boot not downloaded..exiting;fi\0"		\
	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0"		\
	"bootscript=echo Running bootscript from mmc ...; "		\
		"source ${loadaddr}\0"					\
	"nandargs=setenv bootargs ubi.mtd=7 "				\
		"root=ubi0:rootfs rootfstype=ubifs\0"			\
	"nandboot=echo Booting from nand ...; "				\
		"run nandargs; "					\
		"ubi part nand0,4;"					\
		"ubi readvol ${loadaddr} kernel;"			\
		"run addip addtty addmtd addfb addeth addmisc;"		\
		"bootm ${loadaddr}\0"					\
	"swupdate_args=setenv bootargs ubi.mtd=6 root=ubi0:fs_recovery "\
		"rootfstype=ubifs quiet loglevel=1 "			\
			"consoleblank=0 ${swupdate_misc}\0"		\
	"swupdate=echo Running Sw-Update...;"				\
		"if printenv mtdparts;then echo Starting SwUpdate...; "	\
		"else mtdparts default;fi; "				\
		"ubi part nand0,5;"					\
		"ubi readvol 0x82000000 kernel_recovery;"		\
		"run swupdate_args; "					\
		"setenv bootargs ${bootargs} "				\
			"${mtdparts} "					\
			"vram=6M omapfb.vram=1:2M,2:2M,3:2M "		\
			"omapdss.def_disp=lcd;"				\
		"bootm ${loadaddr}\0"

#define CONFIG_BOOTCOMMAND \
	"run nandboot"

#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING

/*
 * Miscellaneous configurable options
 */
#define V_PROMPT			"mcx # "

#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT		V_PROMPT
#define CONFIG_SYS_CBSIZE		1024/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M

#define CONFIG_NAND_OMAP_GPMC
#define GPMC_NAND_ECC_LP_x16_LAYOUT
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */

/* Redundant Environment */
#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
						2 * CONFIG_SYS_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
					CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_SOFTECC

#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

/* move malloc and bss high to prevent clashing with the main image */
#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"

/* NAND boot config */
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
					 48, 49, 50, 51, 52, 53, 54, 55,\
					 56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE		256
#define CONFIG_SYS_NAND_ECCBYTES	3

#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000

/*
 * ethernet support
 *
 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#endif

#endif /* __CONFIG_H */
Commit	Line	Data
4ab779cb IY	1	/*
	2	* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
	3	*
	4	* Based on omap3_evm_config.h
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc.
	19	*/
	20
	21	#ifndef __CONFIG_H
	22	#define __CONFIG_H
	23
	24	/*
	25	* High Level Configuration Options
	26	*/
	27	#define CONFIG_OMAP /* in a TI OMAP core */
	28	#define CONFIG_OMAP34XX /* which is a 34XX */
	29	#define CONFIG_OMAP3_MCX /* working with mcx */
308252ad	30	#define CONFIG_OMAP_GPIO
4ab779cb IY	31
	32	#define MACH_TYPE_MCX 3656
	33	#define CONFIG_MACH_TYPE MACH_TYPE_MCX
3ae6abb6	34	#define CONFIG_BOARD_LATE_INIT
4ab779cb IY	35
	36	#define CONFIG_SYS_CACHELINE_SIZE 64
	37
	38	#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
	39
	40	#include <asm/arch/cpu.h> /* get chip and board defs */
	41	#include <asm/arch/omap3.h>
	42
	43	#define CONFIG_OF_LIBFDT
	44	#define CONFIG_FIT
	45
	46	/*
	47	* Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
	48	* and older u-boot.bin with the new U-Boot SPL.
	49	*/
	50	#define CONFIG_SYS_TEXT_BASE 0x80008000
	51
	52	/*
	53	* Display CPU and Board information
	54	*/
	55	#define CONFIG_DISPLAY_CPUINFO
	56	#define CONFIG_DISPLAY_BOARDINFO
	57
	58	/* Clock Defines */
	59	#define V_OSCK 26000000 /* Clock output from T2 */
	60	#define V_SCLK (V_OSCK >> 1)
	61
	62	#define CONFIG_MISC_INIT_R
	63
	64	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	65	#define CONFIG_SETUP_MEMORY_TAGS
	66	#define CONFIG_INITRD_TAG
	67	#define CONFIG_REVISION_TAG
	68
	69	/*
	70	* Size of malloc() pool
	71	*/
	72	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
	73	#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
	74	/*
	75	* DDR related
	76	*/
	77	#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
	78
	79	/*
	80	* Hardware drivers
	81	*/
	82
	83	/*
	84	* NS16550 Configuration
	85	*/
	86	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	87
	88	#define CONFIG_SYS_NS16550
	89	#define CONFIG_SYS_NS16550_SERIAL
	90	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	91	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	92
	93	/*
	94	* select serial console configuration
	95	*/
	96	#define CONFIG_CONS_INDEX 3
	97	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	98	#define CONFIG_SERIAL3 3 /* UART3 */
99
100	/* allow to overwrite serial and ethaddr */
101	#define CONFIG_ENV_OVERWRITE
102	#define CONFIG_BAUDRATE 115200
103	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
104	115200}
105	#define CONFIG_MMC
106	#define CONFIG_OMAP_HSMMC
107	#define CONFIG_GENERIC_MMC
108	#define CONFIG_DOS_PARTITION
109
110	/* EHCI */
111	#define CONFIG_USB_STORAGE
112	#define CONFIG_OMAP3_GPIO_5
113	#define CONFIG_USB_EHCI
114	#define CONFIG_USB_EHCI_OMAP
115	#define CONFIG_USB_ULPI
116	#define CONFIG_USB_ULPI_VIEWPORT_OMAP
117	/#define CONFIG_EHCI_DCACHE/ /* leave it disabled for now */
118	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154
119	#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152
120	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
121
122	/* commands to include */
123	#include <config_cmd_default.h>
124
125	#define CONFIG_CMD_EXT2 /* EXT2 Support */
126	#define CONFIG_CMD_FAT /* FAT support */
127	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
128
129	#define CONFIG_CMD_DATE
130	#define CONFIG_CMD_I2C /* I2C serial bus support */
131	#define CONFIG_CMD_MMC /* MMC support */
132	#define CONFIG_CMD_FAT /* FAT support */
133	#define CONFIG_CMD_USB
134	#define CONFIG_CMD_NAND /* NAND support */
135	#define CONFIG_CMD_DHCP
136	#define CONFIG_CMD_PING
137	#define CONFIG_CMD_CACHE
138	#define CONFIG_CMD_UBI
139	#define CONFIG_CMD_UBIFS
140	#define CONFIG_RBTREE
141	#define CONFIG_LZO
142	#define CONFIG_MTD_PARTITIONS
143	#define CONFIG_MTD_DEVICE
144	#define CONFIG_CMD_MTDPARTS
3ae6abb6	145	#define CONFIG_CMD_GPIO
4ab779cb IY	146
	147	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	148	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	149	#undef CONFIG_CMD_IMI /* iminfo */
	150	#undef CONFIG_CMD_IMLS /* List all found images */
	151
	152	#define CONFIG_SYS_NO_FLASH
	153	#define CONFIG_HARD_I2C
	154	#define CONFIG_SYS_I2C_SPEED 100000
	155	#define CONFIG_SYS_I2C_SLAVE 1
	156	#define CONFIG_SYS_I2C_BUS 0
	157	#define CONFIG_DRIVER_OMAP34XX_I2C
	158
	159	/* RTC */
	160	#define CONFIG_RTC_DS1337
	161	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	162
	163	#define CONFIG_CMD_NET
	164	#define CONFIG_CMD_MII
	165	#define CONFIG_CMD_NFS
	166	/*
	167	* Board NAND Info.
	168	*/
	169	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	170	/* to access nand */
	171	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	172	/* to access */
	173	/* nand at CS0 */
	174
	175	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	176	/* NAND devices */
4ab779cb IY	177	#define CONFIG_JFFS2_NAND
	178	/* nand device jffs2 lives on */
	179	#define CONFIG_JFFS2_DEV "nand0"
	180	/* start of jffs2 partition */
	181	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	182	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
	183
	184	/* Environment information */
	185	#define CONFIG_BOOTDELAY 10
	186
	187	#define CONFIG_BOOTFILE "uImage"
	188
f89a8b6a SB	189	#define xstr(s) str(s)
	190	#define str(s) #s
	191
	192	/* Setup MTD for NAND on the SOM */
	193	#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
	194	#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
	195	"1m(u-boot),256k(env1)," \
	196	"256k(env2),6m(kernel),6m(k_recovery)," \
	197	"8m(fs_recovery),-(common_data)"
	198
	199	#define CONFIG_HOSTNAME mcx
4ab779cb	200	#define CONFIG_EXTRA_ENV_SETTINGS \
f89a8b6a SB	201	"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \
	202	"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \
	203	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
	204	"addfb=setenv bootargs ${bootargs} vram=6M " \
	205	"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \
	206	"addip_sta=setenv bootargs ${bootargs} " \
	207	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	208	"${netmask}:${hostname}:eth0:off\0" \
	209	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
	210	"addip=if test -n ${ipdyn};then run addip_dyn;" \
	211	"else run addip_sta;fi\0" \
	212	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
	213	"addtty=setenv bootargs ${bootargs} " \
	214	"console=${consoledev},${baudrate}\0" \
	215	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	216	"baudrate=115200\0" \
	217	"consoledev=ttyO2\0" \
	218	"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
	219	"loadaddr=0x82000000\0" \
	220	"load=tftp ${loadaddr} ${u-boot}\0" \
	221	"load_k=tftp ${loadaddr} ${bootfile}\0" \
	222	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	223	"loadmlo=tftp ${loadaddr} ${mlo}\0" \
	224	"mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0" \
	225	"mmcargs=root=/dev/mmcblk0p2 rw " \
	226	"rootfstype=ext3 rootwait\0" \
	227	"mmcboot=echo Booting from mmc ...; " \
	228	"run mmcargs; " \
	229	"run addip addtty addmtd addfb addeth addmisc;" \
	230	"run loaduimage; " \
	231	"bootm ${loadaddr}\0" \
	232	"net_nfs=run load_k; " \
	233	"run nfsargs; " \
	234	"run addip addtty addmtd addfb addeth addmisc;" \
	235	"bootm ${loadaddr}\0" \
	236	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	237	"nfsroot=${serverip}:${rootpath}\0" \
	238	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0" \
	239	"uboot_addr=0x80000\0" \
	240	"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
	241	"nand write ${loadaddr} ${uboot_addr} 80000\0" \
	242	"updatemlo=nandecc hw;nand erase 0 20000;" \
	243	"nand write ${loadaddr} 0 20000\0" \
	244	"upd=if run load;then echo Updating u-boot;if run update;" \
	245	"then echo U-Boot updated;" \
	246	"else echo Error updating u-boot !;" \
	247	"echo Board without bootloader !!;" \
	248	"fi;" \
	249	"else echo U-Boot not downloaded..exiting;fi\0" \
	250	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	251	"bootscript=echo Running bootscript from mmc ...; " \
	252	"source ${loadaddr}\0" \
	253	"nandargs=setenv bootargs ubi.mtd=7 " \
	254	"root=ubi0:rootfs rootfstype=ubifs\0" \
	255	"nandboot=echo Booting from nand ...; " \
	256	"run nandargs; " \
	257	"ubi part nand0,4;" \
	258	"ubi readvol ${loadaddr} kernel;" \
	259	"run addip addtty addmtd addfb addeth addmisc;" \
	260	"bootm ${loadaddr}\0" \
	261	"swupdate_args=setenv bootargs ubi.mtd=6 root=ubi0:fs_recovery "\
	262	"rootfstype=ubifs quiet loglevel=1 " \
	263	"consoleblank=0 ${swupdate_misc}\0" \
	264	"swupdate=echo Running Sw-Update...;" \
265	"if printenv mtdparts;then echo Starting SwUpdate...; " \
266	"else mtdparts default;fi; " \
267	"ubi part nand0,5;" \
268	"ubi readvol 0x82000000 kernel_recovery;" \
269	"run swupdate_args; " \
270	"setenv bootargs ${bootargs} " \
271	"${mtdparts} " \
272	"vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
273	"omapdss.def_disp=lcd;" \
274	"bootm ${loadaddr}\0"
4ab779cb IY	275
4ab779cb IY	276	#define CONFIG_BOOTCOMMAND \
f89a8b6a	277	"run nandboot"
4ab779cb IY	278
4ab779cb IY	279	#define CONFIG_AUTO_COMPLETE
48a4ee50 DZ	280	#define CONFIG_CMDLINE_EDITING
48a4ee50 DZ	281
4ab779cb IY	282	/*
	283	* Miscellaneous configurable options
	284	*/
	285	#define V_PROMPT "mcx # "
	286
	287	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	288	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
4ab779cb	289	#define CONFIG_SYS_PROMPT V_PROMPT
992a27d5	290	#define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
4ab779cb IY	291	/* Print Buffer Size */
	292	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	293	sizeof(CONFIG_SYS_PROMPT) + 16)
	294	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	295	/* args */
	296	/* Boot Argument Buffer Size */
	297	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	298	/* memtest works on */
	299	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	300	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	301	0x01F00000) /* 31MB */
	302
	303	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	304	/* address */
	305
	306	/*
	307	* AM3517 has 12 GP timers, they can be driven by the system clock
	308	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	309	* This rate is divided by a local divisor.
	310	*/
	311	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	312	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	313	#define CONFIG_SYS_HZ 1000
	314
4ab779cb IY	315	/*
	316	* Physical Memory Map
	317	*/
	318	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	319	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	320	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
	321	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	322
	323	/*
	324	* FLASH and environment organization
	325	*/
	326
	327	/* ** PISMO SUPPORT * */
	328
	329	/* Configure the PISMO */
	330	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	331
	332	#define CONFIG_NAND_OMAP_GPMC
	333	#define GPMC_NAND_ECC_LP_x16_LAYOUT
	334	#define CONFIG_ENV_IS_IN_NAND
f89a8b6a	335	#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
4ab779cb	336
f89a8b6a	337	/* Redundant Environment */
4ab779cb IY	338	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	339	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	340	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
f89a8b6a SB	341	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
	342	2 * CONFIG_SYS_ENV_SECT_SIZE)
	343	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
4ab779cb IY	344
	345	/* Flash banks JFFS2 should use */
	346	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	347	CONFIG_SYS_MAX_NAND_DEVICE)
	348	#define CONFIG_SYS_JFFS2_MEM_NAND
	349	/* use flash_info[2] */
	350	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
	351	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	352
	353	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	354	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	355	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	356	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	357	CONFIG_SYS_INIT_RAM_SIZE - \
	358	GENERATED_GBL_DATA_SIZE)
	359
	360	/* Defines for SPL */
	361	#define CONFIG_SPL
	362	#define CONFIG_SPL_NAND_SIMPLE
	363	#define CONFIG_SPL_NAND_SOFTECC
	364
	365	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	366	#define CONFIG_SPL_LIBDISK_SUPPORT
	367	#define CONFIG_SPL_I2C_SUPPORT
	368	#define CONFIG_SPL_MMC_SUPPORT
	369	#define CONFIG_SPL_FAT_SUPPORT
	370	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	371	#define CONFIG_SPL_SERIAL_SUPPORT
	372	#define CONFIG_SPL_POWER_SUPPORT
	373	#define CONFIG_SPL_NAND_SUPPORT
	374	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	375
	376	#define CONFIG_SPL_TEXT_BASE 0x40200000 /CONFIG_SYS_SRAM_START/
e0820ccc	377	#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
4ab779cb IY	378	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
	379
	380	/* move malloc and bss high to prevent clashing with the main image */
	381	#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
	382	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	383	#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
	384	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	385
	386	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	387	#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
	388	#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
	389
	390	/* NAND boot config */
	391	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	392	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	393	#define CONFIG_SYS_NAND_OOBSIZE 64
	394	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	395	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	396	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	397	#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
	398	48, 49, 50, 51, 52, 53, 54, 55,\
	399	56, 57, 58, 59, 60, 61, 62, 63}
	400	#define CONFIG_SYS_NAND_ECCSIZE 256
	401	#define CONFIG_SYS_NAND_ECCBYTES 3
	402
4ab779cb IY	403	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	404
	405	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	406
	407	/*
	408	* ethernet support
	409	*
	410	*/
	411	#if defined(CONFIG_CMD_NET)
	412	#define CONFIG_DRIVER_TI_EMAC
	413	#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	414	#define CONFIG_MII
	415	#define CONFIG_BOOTP_DEFAULT
	416	#define CONFIG_BOOTP_DNS
	417	#define CONFIG_BOOTP_DNS2
	418	#define CONFIG_BOOTP_SEND_HOSTNAME
	419	#define CONFIG_NET_RETRY_COUNT 10
	420	#endif
	421
	422	#endif /* __CONFIG_H */