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8b7d1f0a SR |
1 | /* |
2 | * (C) Copyright 2003-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | ||
25 | /************************************************************************* | |
26 | * (c) 2005 esd gmbh Hannover | |
27 | * | |
28 | * | |
29 | * from IceCube.h file | |
30 | * by Reinhard Arlt reinhard.arlt@esd-electronics.com | |
31 | * | |
32 | *************************************************************************/ | |
33 | ||
34 | #ifndef __CONFIG_H | |
35 | #define __CONFIG_H | |
36 | ||
37 | /* | |
38 | * High Level Configuration Options | |
39 | * (easy to change) | |
40 | */ | |
41 | ||
42 | #define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ | |
43 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
44 | #define CONFIG_ICECUBE 1 /* ... on IceCube board */ | |
45 | #define CONFIG_MECP5200 1 /* ... on MECP5200 board */ | |
46 | #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ | |
47 | ||
48 | #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ | |
49 | ||
50 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
51 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
52 | ||
8b7d1f0a SR |
53 | /* |
54 | * Serial console configuration | |
55 | */ | |
56 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
57 | #if 0 /* test-only */ | |
58 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
59 | #else | |
60 | #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ | |
61 | #endif | |
62 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
63 | ||
64 | ||
65 | #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ | |
66 | ||
67 | #define CONFIG_MII | |
68 | #if 0 /* test-only !!! */ | |
69 | #define CONFIG_NET_MULTI 1 | |
70 | #define CONFIG_EEPRO100 1 | |
71 | #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ | |
72 | #define CONFIG_NS8382X 1 | |
73 | #endif | |
74 | ||
75 | #else /* MPC5100 */ | |
76 | ||
77 | #endif | |
78 | ||
79 | /* Partitions */ | |
80 | #define CONFIG_MAC_PARTITION | |
81 | #define CONFIG_DOS_PARTITION | |
82 | ||
83 | /* USB */ | |
84 | #if 0 | |
85 | #define CONFIG_USB_OHCI | |
8b7d1f0a | 86 | #define CONFIG_USB_STORAGE |
8b7d1f0a SR |
87 | #endif |
88 | ||
d794cfef | 89 | |
7f5c0157 JL |
90 | /* |
91 | * BOOTP options | |
92 | */ | |
93 | #define CONFIG_BOOTP_BOOTFILESIZE | |
94 | #define CONFIG_BOOTP_BOOTPATH | |
95 | #define CONFIG_BOOTP_GATEWAY | |
96 | #define CONFIG_BOOTP_HOSTNAME | |
97 | ||
98 | ||
8b7d1f0a | 99 | /* |
d794cfef | 100 | * Command line configuration. |
8b7d1f0a | 101 | */ |
d794cfef JL |
102 | #include <config_cmd_default.h> |
103 | ||
104 | #define CONFIG_CMD_EEPROM | |
105 | #define CONFIG_CMD_FAT | |
106 | #define CONFIG_CMD_EXT2 | |
107 | #define CONFIG_CMD_I2C | |
108 | #define CONFIG_CMD_IDE | |
109 | #define CONFIG_CMD_BSP | |
110 | #define CONFIG_CMD_ELF | |
111 | ||
8b7d1f0a SR |
112 | |
113 | #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ | |
74357114 | 114 | # define CFG_LOWBOOT 1 |
8b7d1f0a SR |
115 | # define CFG_LOWBOOT16 1 |
116 | #endif | |
117 | #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ | |
74357114 | 118 | # define CFG_LOWBOOT 1 |
8b7d1f0a SR |
119 | # define CFG_LOWBOOT08 1 |
120 | #endif | |
121 | ||
122 | /* | |
123 | * Autobooting | |
124 | */ | |
125 | #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ | |
126 | ||
127 | #define CONFIG_PREBOOT "echo;" \ | |
128 | "echo Welcome to CBX-CPU5200 (mecp5200);" \ | |
129 | "echo" | |
130 | ||
131 | #undef CONFIG_BOOTARGS | |
132 | ||
133 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
134 | "netdev=eth0\0" \ | |
74357114 WD |
135 | "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ |
136 | "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ | |
137 | "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \ | |
138 | "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \ | |
139 | "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \ | |
140 | "loadaddr=01000000\0" \ | |
141 | "serverip=192.168.2.99\0" \ | |
142 | "gatewayip=10.0.0.79\0" \ | |
143 | "user=mu\0" \ | |
144 | "target=mecp5200.esd\0" \ | |
145 | "script=mecp5200.bat\0" \ | |
146 | "image=/tftpboot/vxWorks_mecp5200\0" \ | |
147 | "ipaddr=10.0.13.196\0" \ | |
148 | "netmask=255.255.0.0\0" \ | |
8b7d1f0a SR |
149 | "" |
150 | ||
151 | #define CONFIG_BOOTCOMMAND "run flash_vxworks0" | |
152 | ||
153 | #if defined(CONFIG_MPC5200) | |
154 | /* | |
155 | * IPB Bus clocking configuration. | |
156 | */ | |
53677ef1 | 157 | #undef CFG_IPBSPEED_133 /* define for 133MHz speed */ |
8b7d1f0a SR |
158 | #endif |
159 | /* | |
160 | * I2C configuration | |
161 | */ | |
162 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
163 | #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ | |
164 | ||
165 | #define CFG_I2C_SPEED 86000 /* 100 kHz */ | |
166 | #define CFG_I2C_SLAVE 0x7F | |
167 | ||
168 | /* | |
169 | * EEPROM configuration | |
170 | */ | |
171 | #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ | |
172 | #define CFG_I2C_EEPROM_ADDR_LEN 2 | |
173 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 | |
174 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
74357114 | 175 | #define CFG_I2C_MULTI_EEPROMS 1 |
8b7d1f0a SR |
176 | /* |
177 | * Flash configuration | |
178 | */ | |
179 | #define CFG_FLASH_BASE 0xFFC00000 | |
74357114 | 180 | #define CFG_FLASH_SIZE 0x00400000 |
8b7d1f0a SR |
181 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x003E0000) |
182 | #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
183 | #define CFG_MAX_FLASH_SECT 512 | |
184 | ||
185 | #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ | |
186 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
187 | ||
188 | /* | |
189 | * Environment settings | |
190 | */ | |
191 | #if 1 /* test-only */ | |
192 | #define CFG_ENV_IS_IN_FLASH 1 | |
193 | #define CFG_ENV_SIZE 0x10000 | |
194 | #define CFG_ENV_SECT_SIZE 0x10000 | |
195 | #define CONFIG_ENV_OVERWRITE 1 | |
196 | #else | |
197 | #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ | |
198 | #define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ | |
199 | #define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/ | |
200 | /* total size of a CAT24WC32 is 8192 bytes */ | |
201 | #define CONFIG_ENV_OVERWRITE 1 | |
202 | #endif | |
203 | ||
74357114 WD |
204 | #define CFG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */ |
205 | #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ | |
206 | #define CFG_FLASH_PROTECTION 1 /* use hardware protection */ | |
8b7d1f0a SR |
207 | #if 0 |
208 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
209 | #endif | |
74357114 | 210 | #define CFG_FLASH_INCREMENT 0x00400000 /* size of flash bank */ |
8b7d1f0a | 211 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
74357114 | 212 | #define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */ |
8b7d1f0a SR |
213 | |
214 | ||
215 | /* | |
216 | * Memory map | |
217 | */ | |
218 | #define CFG_MBAR 0xF0000000 | |
219 | #define CFG_SDRAM_BASE 0x00000000 | |
220 | #define CFG_DEFAULT_MBAR 0x80000000 | |
221 | ||
222 | /* Use SRAM until RAM will be available */ | |
223 | #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM | |
224 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ | |
225 | ||
226 | ||
227 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
228 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
229 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
230 | ||
231 | #define CFG_MONITOR_BASE TEXT_BASE | |
232 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
233 | # define CFG_RAMBOOT 1 | |
234 | #endif | |
235 | ||
236 | #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ | |
237 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
238 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
239 | ||
240 | /* | |
241 | * Ethernet configuration | |
242 | */ | |
243 | #define CONFIG_MPC5xxx_FEC 1 | |
244 | /* | |
245 | * Define CONFIG_FEC_10MBIT to force FEC at 10Mb | |
246 | */ | |
247 | /* #define CONFIG_FEC_10MBIT 1 */ | |
248 | #define CONFIG_PHY_ADDR 0x00 | |
249 | #define CONFIG_UDP_CHECKSUM 1 | |
250 | ||
251 | ||
252 | /* | |
253 | * GPIO configuration | |
254 | */ | |
255 | #define CFG_GPS_PORT_CONFIG 0x01052444 | |
256 | ||
257 | /* | |
258 | * Miscellaneous configurable options | |
259 | */ | |
260 | #define CFG_LONGHELP /* undef to save memory */ | |
261 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
d794cfef | 262 | #if defined(CONFIG_CMD_KGDB) |
8b7d1f0a SR |
263 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
264 | #else | |
265 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
266 | #endif | |
267 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
268 | #define CFG_MAXARGS 16 /* max number of command args */ | |
269 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
270 | ||
271 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ | |
272 | #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
273 | ||
274 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
275 | ||
74357114 | 276 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
8b7d1f0a SR |
277 | |
278 | #define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ | |
279 | ||
d794cfef JL |
280 | #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
281 | #if defined(CONFIG_CMD_KGDB) | |
282 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
283 | #endif | |
284 | ||
8b7d1f0a SR |
285 | /* |
286 | * Various low-level settings | |
287 | */ | |
288 | #if defined(CONFIG_MPC5200) | |
289 | #define CFG_HID0_INIT HID0_ICE | HID0_ICFI | |
290 | #define CFG_HID0_FINAL HID0_ICE | |
291 | #else | |
292 | #define CFG_HID0_INIT 0 | |
293 | #define CFG_HID0_FINAL 0 | |
294 | #endif | |
295 | ||
296 | #define CFG_BOOTCS_START CFG_FLASH_BASE | |
297 | #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE | |
298 | #define CFG_BOOTCS_CFG 0x00085d00 | |
299 | ||
300 | #define CFG_CS0_START CFG_FLASH_BASE | |
301 | #define CFG_CS0_SIZE CFG_FLASH_SIZE | |
302 | ||
303 | #define CFG_CS1_START 0xfd000000 | |
304 | #define CFG_CS1_SIZE 0x00010000 | |
305 | #define CFG_CS1_CFG 0x10101410 | |
306 | ||
307 | #define CFG_CS_BURST 0x00000000 | |
308 | #define CFG_CS_DEADCYCLE 0x33333333 | |
309 | ||
310 | #define CFG_RESET_ADDRESS 0xff000000 | |
311 | ||
312 | /*----------------------------------------------------------------------- | |
313 | * USB stuff | |
314 | *----------------------------------------------------------------------- | |
315 | */ | |
316 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
317 | #define CONFIG_USB_CONFIG 0x00001000 | |
318 | ||
319 | /*----------------------------------------------------------------------- | |
320 | * IDE/ATA stuff Supports IDE harddisk | |
321 | *----------------------------------------------------------------------- | |
322 | */ | |
323 | ||
324 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
325 | ||
326 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
327 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
328 | ||
329 | #define CONFIG_IDE_RESET /* reset for ide supported */ | |
330 | #define CONFIG_IDE_PREINIT | |
331 | ||
332 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
333 | #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
334 | ||
335 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
336 | ||
337 | #define CFG_ATA_BASE_ADDR MPC5XXX_ATA | |
338 | ||
339 | /* Offset for data I/O */ | |
340 | #define CFG_ATA_DATA_OFFSET (0x0060) | |
341 | ||
342 | /* Offset for normal register accesses */ | |
343 | #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) | |
344 | ||
345 | /* Offset for alternate registers */ | |
346 | #define CFG_ATA_ALT_OFFSET (0x005C) | |
347 | ||
74357114 WD |
348 | /* Interval between registers */ |
349 | #define CFG_ATA_STRIDE 4 | |
8b7d1f0a SR |
350 | |
351 | #endif /* __CONFIG_H */ |