[people/ms/u-boot.git] / include / configs / mgsuvd.h

/*
 * (C) Copyright 2007
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC866		1	/* This is a MPC866 CPU		*/
#define CONFIG_MGSUVD		1	/* ...on a mgsuvd board	*/

/* Do boardspecific init */
#define CONFIG_BOARD_EARLY_INIT_R       1

#define CONFIG_8xx_GCLK_FREQ		66000000

#define CONFIG_SYS_SMC_UCODE_PATCH	1	/* Relocate SMC1 */
#define CONFIG_SYS_SMC_DPMEM_OFFSET	0x1fc0
#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/

#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/

#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_SYS_CPM_BOOTCOUNT_ADDR	0x1eb0	/* In case of SMC relocation, the
					 * default value is not working */

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS						\
	"netdev=eth0\0"								\
	"addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=${serverip}:${rootpath}\0"				\
	"ramargs=setenv bootargs root=/dev/ram rw\0"				\
	"addip=setenv bootargs ${bootargs} "					\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"		\
		":${hostname}:${netdev}:off panic=1\0"				\
	"flash_nfs=run nfsargs addip;"						\
		"bootm ${kernel_addr}\0"					\
	"flash_self=run ramargs addip;"						\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"			\
	"net_nfs=tftp ${kernel_addr} ${bootfile}; "				\
		"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;"	\
		"bootm ${kernel_addr} - ${fdt_addr}\0"				\
	"rootpath=/opt/eldk/ppc_8xx\0"						\
	"bootfile=/tftpboot/mgsuvd/uImage\0"					\
	"fdt_addr=400000\0"							\
	"kernel_addr=200000\0"							\
	"fdt_file=/tftpboot/mgsuvd/mgsuvd.dtb\0"				\
	"load=tftp 200000 ${u-boot}\0"						\
	"update=protect off f0000000 +${filesize};"				\
		"erase f0000000 +${filesize};"					\
		"cp.b 200000 f0000000 ${filesize};"				\
		"protect on f0000000 +${filesize}\0"				\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE

#undef CONFIG_RTC_MPC8xx		/* MPC866 does not support RTC	*/

#define	CONFIG_TIMESTAMP		/* but print image timestmps	*/

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
#ifdef	CONFIG_SYS_HUSH_PARSER
#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_HUSH_INIT_VAR	1
#endif

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xf0000000
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_FLASH_SIZE		32
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */


#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
#define CONFIG_ENV_SIZE		0x08000 /* Total Size of Environment Sector	*/
#define CONFIG_ENV_SECT_SIZE	0x40000 /* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#define CONFIG_SYS_SYPCR	0xffffff89

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_SIUMCR	0x00610480

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	0x01800000
#define CONFIG_SYS_SCCR	0x01800000

#define CONFIG_SYS_DER 0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xf0000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing: Default value of OR0 after reset
 */
#define CONFIG_SYS_OR0_PRELIM	0xfe000954
#define CONFIG_SYS_BR0_PRELIM	0xf0000401

/*
 * BR1 and OR1 (SDRAM)
 *
 */
#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_MAX_SIZE		(64 << 20)	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

#define CONFIG_SYS_OR1_PRELIM	0xfc000800
#define CONFIG_SYS_BR1_PRELIM	(0x000000C0 | 0x01)

#define CONFIG_SYS_MPTPR	0x0200
/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
   1 Write loop Cycle (not used), 1 Timer Loop Cycle */
#define CONFIG_SYS_MBMR	0x10964111
#define CONFIG_SYS_MAR		0x00000088

/*
 * 4096	Rows from SDRAM example configuration
 * 1000	factor s -> ms
 * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
 * 4	Number of refresh cycles per period
 * 64	Refresh cycle in ms per number of rows
 */
#define CONFIG_SYS_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))

/* GPIO/PIGGY on CS3 initialization values
*/
#define CONFIG_SYS_PIGGY_BASE	(0x30000000)
#define CONFIG_SYS_OR3_PRELIM	(0xfe000d24)
#define CONFIG_SYS_BR3_PRELIM	(0x30000401)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#define CONFIG_SCC3_ENET
#define CONFIG_ETHPRIME		"SCC ETHERNET"
#define CONFIG_HAS_ETH0

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,866@0"
#define OF_SOC			"soc@fff00000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc/cpm/serial@a80"

/* enable I2C and select the hardware/software driver */
#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define	CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
#define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define I2C_SOFT_DECLARATIONS

/*
 * Software (bit-bang) I2C driver configuration
 */
#define I2C_BASE_DIR	(CONFIG_SYS_PIGGY_BASE + 0x04)
#define I2C_BASE_PORT	(CONFIG_SYS_PIGGY_BASE + 0x09)

#define SDA_BIT		0x40
#define SCL_BIT		0x80
#define SDA_CONF	0x1000
#define SCL_CONF	0x2000

#define I2C_ACTIVE	do {} while (0)
#define I2C_TRISTATE	do {} while (0)
#define I2C_READ	i2c_soft_read_pin ()
#define I2C_SDA(bit)	if(bit) { \
				*(unsigned short *)(I2C_BASE_DIR) &=  ~SDA_CONF; \
				} \
			else    { \
				*(unsigned char *)(I2C_BASE_PORT) &= ~SDA_BIT; \
				*(unsigned short *)(I2C_BASE_DIR) |= SDA_CONF; \
				}
#define I2C_SCL(bit)	if(bit) { \
				*(unsigned short *)(I2C_BASE_DIR) &=  ~SCL_CONF; \
				} \
			else    { \
				*(unsigned char *)(I2C_BASE_PORT) &= ~SCL_BIT; \
				*(unsigned short *)(I2C_BASE_DIR) |= SCL_CONF; \
				}
#define I2C_DELAY	udelay(50)	/* 1/4 I2C clock duration */

#define CONFIG_I2C_MULTI_BUS	1
#define CONFIG_I2C_CMD_TREE	1
#define CONFIG_SYS_MAX_I2C_BUS		2
#define CONFIG_SYS_I2C_INIT_BOARD	1
#define CONFIG_I2C_MUX		1

/* EEprom support */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_I2C_MULTI_EEPROMS	1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10

/* Support the IVM EEprom */
#define	CONFIG_SYS_IVM_EEPROM_ADR	0x50
#define CONFIG_SYS_IVM_EEPROM_MAX_LEN	0x400
#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN	0x100

/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
#define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
#define CONFIG_DTT_SENSORS	{0, 2, 4, 6}	/* Sensor addresses		*/
#define CONFIG_SYS_DTT_MAX_TEMP	70
#define CONFIG_SYS_DTT_LOW_TEMP	-30
#define CONFIG_SYS_DTT_HYSTERESIS	3
#define CONFIG_SYS_DTT_BUS_NUM		(CONFIG_SYS_MAX_I2C_BUS)

#endif	/* __CONFIG_H */
Commit	Line	Data
381e4e63 HS	1	/*
	2	* (C) Copyright 2007
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
	37	#define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
	38
82afabfe HS	39	/* Do boardspecific init */
	40	#define CONFIG_BOARD_EARLY_INIT_R 1
	41
381e4e63 HS	42	#define CONFIG_8xx_GCLK_FREQ 66000000
381e4e63 HS	43
6d0f6bcf JCPV	44	#define CONFIG_SYS_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
6d0f6bcf JCPV	45	#define CONFIG_SYS_SMC_DPMEM_OFFSET 0x1fc0
381e4e63 HS	46	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	47
	48	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
	49
	50	#define CONFIG_BOOTCOUNT_LIMIT
6d0f6bcf	51	#define CONFIG_SYS_CPM_BOOTCOUNT_ADDR 0x1eb0 /* In case of SMC relocation, the
f7e51b27	52	* default value is not working */
381e4e63 HS	53
	54	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	55
	56	#define CONFIG_BOARD_TYPES 1 /* support board types */
	57
	58	#define CONFIG_PREBOOT "echo;" \
32bf3d14	59	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
381e4e63 HS	60	"echo"
	61
	62	#undef CONFIG_BOOTARGS
	63
c61e033d DZ	64	#define CONFIG_EXTRA_ENV_SETTINGS \
c61e033d DZ	65	"netdev=eth0\0" \
f308572e	66	"addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
c61e033d DZ	67	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	68	"nfsroot=${serverip}:${rootpath}\0" \
	69	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	70	"addip=setenv bootargs ${bootargs} " \
	71	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	72	":${hostname}:${netdev}:off panic=1\0" \
	73	"flash_nfs=run nfsargs addip;" \
	74	"bootm ${kernel_addr}\0" \
	75	"flash_self=run ramargs addip;" \
	76	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	77	"net_nfs=tftp ${kernel_addr} ${bootfile}; " \
	78	"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \
	79	"bootm ${kernel_addr} - ${fdt_addr}\0" \
	80	"rootpath=/opt/eldk/ppc_8xx\0" \
	81	"bootfile=/tftpboot/mgsuvd/uImage\0" \
	82	"fdt_addr=400000\0" \
	83	"kernel_addr=200000\0" \
	84	"fdt_file=/tftpboot/mgsuvd/mgsuvd.dtb\0" \
	85	"load=tftp 200000 ${u-boot}\0" \
	86	"update=protect off f0000000 +${filesize};" \
	87	"erase f0000000 +${filesize};" \
	88	"cp.b 200000 f0000000 ${filesize};" \
	89	"protect on f0000000 +${filesize}\0" \
381e4e63 HS	90	""
	91	#define CONFIG_BOOTCOMMAND "run flash_self"
	92
	93	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	94	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
381e4e63 HS	95
	96	#undef CONFIG_WATCHDOG /* watchdog disabled */
	97
	98	/*
	99	* BOOTP options
	100	*/
	101	#define CONFIG_BOOTP_SUBNETMASK
	102	#define CONFIG_BOOTP_GATEWAY
	103	#define CONFIG_BOOTP_HOSTNAME
	104	#define CONFIG_BOOTP_BOOTPATH
	105	#define CONFIG_BOOTP_BOOTFILESIZE
	106
	107	#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
	108
	109	#define CONFIG_TIMESTAMP /* but print image timestmps */
	110
	111	/*
	112	* Command line configuration.
	113	*/
	114	#include <config_cmd_default.h>
	115
	116	#define CONFIG_CMD_ASKENV
	117	#define CONFIG_CMD_DHCP
e5e4edd9	118	#define CONFIG_CMD_DTT
f2202450	119	#define CONFIG_CMD_EEPROM
9661bf9d	120	#define CONFIG_CMD_I2C
381e4e63 HS	121	#define CONFIG_CMD_NFS
	122	#define CONFIG_CMD_PING
	123
	124	/*
	125	* Miscellaneous configurable options
	126	*/
6d0f6bcf JCPV	127	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	128	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
381e4e63 HS	129
381e4e63 HS	130	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
6d0f6bcf JCPV	131	#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
	132	#ifdef CONFIG_SYS_HUSH_PARSER
	133	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
8f64da7f	134	#define CONFIG_HUSH_INIT_VAR 1
381e4e63 HS	135	#endif
	136
	137	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	138	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
381e4e63	139	#else
6d0f6bcf	140	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
381e4e63	141	#endif
6d0f6bcf JCPV	142	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	143	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	144	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
381e4e63	145
6d0f6bcf JCPV	146	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	147	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
381e4e63	148
6d0f6bcf	149	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
381e4e63	150
6d0f6bcf	151	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
381e4e63	152
6d0f6bcf	153	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
381e4e63 HS	154
	155	/*
	156	* Low Level Configuration Settings
	157	* (address mappings, register initial values, etc.)
	158	* You should know what you are doing if you make changes here.
	159	*/
	160	/*-----------------------------------------------------------------------
	161	* Internal Memory Mapped Register
	162	*/
6d0f6bcf	163	#define CONFIG_SYS_IMMR 0xFFF00000
381e4e63 HS	164
	165	/*-----------------------------------------------------------------------
	166	* Definitions for initial stack pointer and data area (in DPRAM)
	167	*/
6d0f6bcf JCPV	168	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
	169	#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	170	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	171	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	172	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
381e4e63 HS	173
	174	/*-----------------------------------------------------------------------
	175	* Start addresses for the final memory configuration
	176	* (Set up by the startup code)
6d0f6bcf	177	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
381e4e63	178	*/
6d0f6bcf JCPV	179	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	180	#define CONFIG_SYS_FLASH_BASE 0xf0000000
	181	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	182	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	183	#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
381e4e63 HS	184
	185	/*
	186	* For booting Linux, the board info and command line data
	187	* have to be in the first 8 MB of memory, since this is
	188	* the maximum mapped by the Linux kernel during initialization.
	189	*/
6d0f6bcf	190	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
381e4e63 HS	191
	192	/*-----------------------------------------------------------------------
	193	* FLASH organization
	194	*/
6d0f6bcf JCPV	195	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	196	#define CONFIG_SYS_FLASH_SIZE 32
	197	#define CONFIG_SYS_FLASH_CFI
00b1883a	198	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf	199	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
381e4e63 HS	200
381e4e63 HS	201
6d0f6bcf JCPV	202	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	203	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
381e4e63	204
5a1aceb0	205	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	206	#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
	207	#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
	208	#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
381e4e63 HS	209
381e4e63 HS	210	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	211	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	212	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
381e4e63	213
6d0f6bcf	214	#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
381e4e63 HS	215
	216	/*-----------------------------------------------------------------------
	217	* Cache Configuration
	218	*/
6d0f6bcf	219	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
381e4e63	220	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	221	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
381e4e63 HS	222	#endif
	223
	224	/*-----------------------------------------------------------------------
	225	* SYPCR - System Protection Control 11-9
	226	* SYPCR can only be written once after reset!
	227	*-----------------------------------------------------------------------
	228	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	229	*/
6d0f6bcf	230	#define CONFIG_SYS_SYPCR 0xffffff89
381e4e63 HS	231
	232	/*-----------------------------------------------------------------------
	233	* SIUMCR - SIU Module Configuration 11-6
	234	*-----------------------------------------------------------------------
	235	*/
6d0f6bcf	236	#define CONFIG_SYS_SIUMCR 0x00610480
381e4e63 HS	237
	238	/*-----------------------------------------------------------------------
	239	* TBSCR - Time Base Status and Control 11-26
	240	*-----------------------------------------------------------------------
	241	* Clear Reference Interrupt Status, Timebase freezing enabled
	242	*/
6d0f6bcf	243	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
381e4e63 HS	244
	245	/*-----------------------------------------------------------------------
	246	* PISCR - Periodic Interrupt Status and Control 11-31
	247	*-----------------------------------------------------------------------
	248	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	249	*/
6d0f6bcf	250	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
381e4e63 HS	251
	252	/*-----------------------------------------------------------------------
	253	* SCCR - System Clock and reset Control Register 15-27
	254	*-----------------------------------------------------------------------
	255	* Set clock output, timebase and RTC source and divider,
	256	* power management and some other internal clocks
	257	*/
	258	#define SCCR_MASK 0x01800000
6d0f6bcf	259	#define CONFIG_SYS_SCCR 0x01800000
381e4e63	260
6d0f6bcf	261	#define CONFIG_SYS_DER 0
381e4e63 HS	262
	263	/*
	264	* Init Memory Controller:
	265	*
	266	* BR0/1 and OR0/1 (FLASH)
	267	*/
	268
	269	#define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
	270
	271	/* used to re-map FLASH both when starting from SRAM or FLASH:
	272	* restrict access enough to keep SRAM working (if any)
	273	* but not too much to meddle with FLASH accesses
	274	*/
6d0f6bcf JCPV	275	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	276	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
381e4e63 HS	277
	278	/*
	279	* FLASH timing: Default value of OR0 after reset
	280	*/
6d0f6bcf JCPV	281	#define CONFIG_SYS_OR0_PRELIM 0xfe000954
6d0f6bcf JCPV	282	#define CONFIG_SYS_BR0_PRELIM 0xf0000401
381e4e63 HS	283
	284	/*
	285	* BR1 and OR1 (SDRAM)
	286	*
	287	*/
	288	#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
	289	#define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
	290
	291	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	292	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
381e4e63	293
6d0f6bcf JCPV	294	#define CONFIG_SYS_OR1_PRELIM 0xfc000800
6d0f6bcf JCPV	295	#define CONFIG_SYS_BR1_PRELIM (0x000000C0 \| 0x01)
381e4e63	296
6d0f6bcf	297	#define CONFIG_SYS_MPTPR 0x0200
381e4e63 HS	298	/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
381e4e63 HS	299	1 Write loop Cycle (not used), 1 Timer Loop Cycle */
6d0f6bcf JCPV	300	#define CONFIG_SYS_MBMR 0x10964111
6d0f6bcf JCPV	301	#define CONFIG_SYS_MAR 0x00000088
381e4e63 HS	302
	303	/*
	304	* 4096 Rows from SDRAM example configuration
	305	* 1000 factor s -> ms
	306	* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
	307	* 4 Number of refresh cycles per period
	308	* 64 Refresh cycle in ms per number of rows
	309	*/
6d0f6bcf	310	#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
82afabfe HS	311
	312	/* GPIO/PIGGY on CS3 initialization values
	313	*/
6d0f6bcf JCPV	314	#define CONFIG_SYS_PIGGY_BASE (0x30000000)
	315	#define CONFIG_SYS_OR3_PRELIM (0xfe000d24)
	316	#define CONFIG_SYS_BR3_PRELIM (0x30000401)
381e4e63 HS	317
	318	/*
	319	* Internal Definitions
	320	*
	321	* Boot Flags
	322	*/
	323	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	324	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	325
	326	#define CONFIG_SCC3_ENET
	327	#define CONFIG_ETHPRIME "SCC ETHERNET"
	328	#define CONFIG_HAS_ETH0
	329
	330	/* pass open firmware flat tree */
	331	#define CONFIG_OF_LIBFDT 1
	332	#define CONFIG_OF_BOARD_SETUP 1
	333
	334	#define OF_CPU "PowerPC,866@0"
82afabfe	335	#define OF_SOC "soc@fff00000"
381e4e63 HS	336	#define OF_TBCLK (bd->bi_busfreq / 4)
	337	#define OF_STDOUT_PATH "/soc/cpm/serial@a80"
	338
9661bf9d HS	339	/* enable I2C and select the hardware/software driver */
	340	#undef CONFIG_HARD_I2C /* I2C with hardware support */
	341	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
6d0f6bcf JCPV	342	#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
6d0f6bcf JCPV	343	#define CONFIG_SYS_I2C_SLAVE 0x7F
9661bf9d HS	344	#define I2C_SOFT_DECLARATIONS
	345
	346	/*
	347	* Software (bit-bang) I2C driver configuration
	348	*/
6d0f6bcf JCPV	349	#define I2C_BASE_DIR (CONFIG_SYS_PIGGY_BASE + 0x04)
6d0f6bcf JCPV	350	#define I2C_BASE_PORT (CONFIG_SYS_PIGGY_BASE + 0x09)
9661bf9d HS	351
	352	#define SDA_BIT 0x40
	353	#define SCL_BIT 0x80
	354	#define SDA_CONF 0x1000
	355	#define SCL_CONF 0x2000
	356
	357	#define I2C_ACTIVE do {} while (0)
	358	#define I2C_TRISTATE do {} while (0)
	359	#define I2C_READ i2c_soft_read_pin ()
	360	#define I2C_SDA(bit) if(bit) { \
	361	(unsigned short )(I2C_BASE_DIR) &= ~SDA_CONF; \
	362	} \
	363	else { \
	364	(unsigned char )(I2C_BASE_PORT) &= ~SDA_BIT; \
	365	(unsigned short )(I2C_BASE_DIR) \|= SDA_CONF; \
	366	}
	367	#define I2C_SCL(bit) if(bit) { \
	368	(unsigned short )(I2C_BASE_DIR) &= ~SCL_CONF; \
	369	} \
	370	else { \
	371	(unsigned char )(I2C_BASE_PORT) &= ~SCL_BIT; \
	372	(unsigned short )(I2C_BASE_DIR) \|= SCL_CONF; \
	373	}
	374	#define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
	375
	376	#define CONFIG_I2C_MULTI_BUS 1
	377	#define CONFIG_I2C_CMD_TREE 1
6d0f6bcf JCPV	378	#define CONFIG_SYS_MAX_I2C_BUS 2
6d0f6bcf JCPV	379	#define CONFIG_SYS_I2C_INIT_BOARD 1
67b23a32	380	#define CONFIG_I2C_MUX 1
9661bf9d	381
f2202450	382	/* EEprom support */
6d0f6bcf JCPV	383	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	384	#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
	385	#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
	386	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	387	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
9661bf9d	388
8f64da7f	389	/* Support the IVM EEprom */
6d0f6bcf JCPV	390	#define CONFIG_SYS_IVM_EEPROM_ADR 0x50
	391	#define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400
	392	#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100
8f64da7f	393
e5e4edd9 HS	394	/* I2C SYSMON (LM75, AD7414 is almost compatible) */
	395	#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
	396	#define CONFIG_DTT_SENSORS {0, 2, 4, 6} /* Sensor addresses */
6d0f6bcf JCPV	397	#define CONFIG_SYS_DTT_MAX_TEMP 70
	398	#define CONFIG_SYS_DTT_LOW_TEMP -30
	399	#define CONFIG_SYS_DTT_HYSTERESIS 3
	400	#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
e5e4edd9	401
381e4e63	402	#endif /* __CONFIG_H */