[people/ms/u-boot.git] / include / configs / microblaze-generic.h

/*
 * (C) Copyright 2007-2010 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/xilinx/microblaze-generic/xparameters.h"

/* MicroBlaze CPU */
#define	MICROBLAZE_V5		1

/* linear and spi flash memory */
#ifdef XILINX_FLASH_START
#define	FLASH
#undef	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#ifdef XILINX_SPI_FLASH_BASEADDR
#undef	FLASH
#define	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#undef	FLASH
#undef	SPIFLASH
#define	RAMENV	/* hold environment in RAM */
#endif
#endif

/* uart */
# define CONFIG_BAUDRATE	115200
/* The following table includes the supported baudrates */
# define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

/* setting reset address */
/*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/

/* gpio */
#ifdef XILINX_GPIO_BASEADDR
# define CONFIG_XILINX_GPIO
# define CONFIG_SYS_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
#endif

/* interrupt controller */
#ifdef XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_ADDR		XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
#endif

/* timer */
#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
#  define CONFIG_SYS_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
#  define CONFIG_SYS_TIMER_0_IRQ	XILINX_TIMER_IRQ
#endif

/* watchdog */
#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
# define CONFIG_WATCHDOG_BASEADDR	XILINX_WATCHDOG_BASEADDR
# define CONFIG_WATCHDOG_IRQ		XILINX_WATCHDOG_IRQ
# ifndef CONFIG_SPL_BUILD
#  define CONFIG_HW_WATCHDOG
#  define CONFIG_XILINX_TB_WATCHDOG
# endif
#endif

#if !defined(CONFIG_OF_CONTROL) || \
	(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL))
/* ddr sdram - main memory */
# define CONFIG_SYS_SDRAM_BASE	XILINX_RAM_START
# define CONFIG_SYS_SDRAM_SIZE	XILINX_RAM_SIZE
#endif

#define CONFIG_SYS_MALLOC_LEN	0xC0000

/* Stack location before relocation */
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_TEXT_BASE - \
					 CONFIG_SYS_MALLOC_F_LEN)

/*
 * CFI flash memory layout - Example
 * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
 * CONFIG_SYS_FLASH_SIZE = 0x0080_0000;	  8MB
 *
 * SECT_SIZE = 0x20000;			128kB is one sector
 * CONFIG_ENV_SIZE = SECT_SIZE;		128kB environment store
 *
 * 0x2200_0000	CONFIG_SYS_FLASH_BASE
 *					FREE		256kB
 * 0x2204_0000	CONFIG_ENV_ADDR
 *					ENV_AREA	128kB
 * 0x2206_0000
 *					FREE
 * 0x2280_0000	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
 *
 */

#ifdef FLASH
# define CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
# define CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
# define CONFIG_SYS_FLASH_CFI		1
# define CONFIG_FLASH_CFI_DRIVER	1
/* ?empty sector */
# define CONFIG_SYS_FLASH_EMPTY_INFO	1
/* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_BANKS	1
/* max number of sectors on one chip */
# define CONFIG_SYS_MAX_FLASH_SECT	512
/* hardware flash protection */
# define CONFIG_SYS_FLASH_PROTECTION
/* use buffered writes (20x faster) */
# define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
# ifdef	RAMENV
#  define CONFIG_ENV_IS_NOWHERE	1
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* FLASH && !RAMENV */
#  define CONFIG_ENV_IS_IN_FLASH	1
/* 128K(one sector) for env */
#  define CONFIG_ENV_SECT_SIZE	0x20000
#  define CONFIG_ENV_ADDR \
			(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
#  define CONFIG_ENV_SIZE	0x20000
# endif /* FLASH && !RAMBOOT */
#else /* !FLASH */

#ifdef SPIFLASH
# define CONFIG_SYS_NO_FLASH		1
# define CONFIG_SYS_SPI_BASE		XILINX_SPI_FLASH_BASEADDR
# define CONFIG_SPI			1
# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
# define CONFIG_SF_DEFAULT_SPEED	XILINX_SPI_FLASH_MAX_FREQ
# define CONFIG_SF_DEFAULT_CS		XILINX_SPI_FLASH_CS

# ifdef	RAMENV
#  define CONFIG_ENV_IS_NOWHERE	1
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* SPIFLASH && !RAMENV */
#  define CONFIG_ENV_IS_IN_SPI_FLASH	1
#  define CONFIG_ENV_SPI_MODE		SPI_MODE_3
#  define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#  define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
/* 128K(two sectors) for env */
#  define CONFIG_ENV_SECT_SIZE	0x10000
#  define CONFIG_ENV_SIZE	(2 * CONFIG_ENV_SECT_SIZE)
/* Warning: adjust the offset in respect of other flash content and size */
#  define CONFIG_ENV_OFFSET	(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
# endif /* SPIFLASH && !RAMBOOT */
#else /* !SPIFLASH */

/* ENV in RAM */
# define CONFIG_SYS_NO_FLASH	1
# define CONFIG_ENV_IS_NOWHERE	1
# define CONFIG_ENV_SIZE	0x1000
# define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
#endif /* !SPIFLASH */
#endif /* !FLASH */

#if defined(XILINX_USE_ICACHE)
# define CONFIG_ICACHE
#else
# undef CONFIG_ICACHE
#endif

#if defined(XILINX_USE_DCACHE)
# define CONFIG_DCACHE
#else
# undef CONFIG_DCACHE
#endif

#ifndef XILINX_DCACHE_BYTE_SIZE
#define XILINX_DCACHE_BYTE_SIZE	32768
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MFSL

#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
# define CONFIG_CMD_CACHE
#else
# undef CONFIG_CMD_CACHE
#endif

#if defined(FLASH)
# define CONFIG_CMD_JFFS2
# define CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVES
# endif

#else
#if defined(SPIFLASH)
# define CONFIG_CMD_SF

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVES
# endif
#else
# undef CONFIG_CMD_JFFS2
# undef CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS
#endif
#endif

#if defined(CONFIG_CMD_JFFS2)
# define CONFIG_MTD_PARTITIONS
#endif

#if defined(CONFIG_CMD_UBIFS)
# define CONFIG_CMD_UBI
# define CONFIG_LZO
#endif

#if defined(CONFIG_CMD_UBI)
# define CONFIG_MTD_PARTITIONS
# define CONFIG_RBTREE
#endif

#if defined(CONFIG_MTD_PARTITIONS)
/* MTD partitions */
#define CONFIG_CMD_MTDPARTS	/* mtdparts command line support */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=flash-0"

/* default mtd partition table */
#define MTDPARTS_DEFAULT	"mtdparts=flash-0:256k(u-boot),"\
				"256k(env),3m(kernel),1m(romfs),"\
				"1m(cramfs),-(jffs2)"
#endif

/* size of console buffer */
#define	CONFIG_SYS_CBSIZE	512
 /* print buffer size */
#define	CONFIG_SYS_PBSIZE \
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define	CONFIG_SYS_MAXARGS	15
#define	CONFIG_SYS_LONGHELP
/* default load address */
#define	CONFIG_SYS_LOAD_ADDR	XILINX_RAM_START

#define	CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
#define	CONFIG_BOOTARGS		"root=romfs"
#define	CONFIG_HOSTNAME		XILINX_BOARD_NAME
#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
#define	CONFIG_IPADDR		192.168.0.3
#define	CONFIG_SERVERIP		192.168.0.5
#define	CONFIG_GATEWAYIP	192.168.0.1

/* architecture dependent code */
#define	CONFIG_SYS_USR_EXCEP	/* user exception */

#define	CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot;echo"

#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" \
					"nor0=flash-0\0"\
					"mtdparts=mtdparts=flash-0:"\
					"256k(u-boot),256k(env),3m(kernel),"\
					"1m(romfs),1m(cramfs),-(jffs2)\0"\
					"nc=setenv stdout nc;"\
					"setenv stdin nc\0" \
					"serial=setenv stdout serial;"\
					"setenv stdin serial\0"

#define CONFIG_CMDLINE_EDITING

#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER

/* Enable flat device tree support */
#define CONFIG_LMB		1
#define CONFIG_OF_LIBFDT	1

#if defined(CONFIG_XILINX_AXIEMAC)
# define CONFIG_MII		1
# define CONFIG_CMD_MII		1
# define CONFIG_PHY_GIGE	1
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
# define CONFIG_PHY_ATHEROS	1
# define CONFIG_PHY_BROADCOM	1
# define CONFIG_PHY_DAVICOM	1
# define CONFIG_PHY_LXT		1
# define CONFIG_PHY_MARVELL	1
# define CONFIG_PHY_MICREL	1
# define CONFIG_PHY_MICREL_KSZ9021
# define CONFIG_PHY_NATSEMI	1
# define CONFIG_PHY_REALTEK	1
# define CONFIG_PHY_VITESSE	1
#else
# undef CONFIG_MII
# undef CONFIG_CMD_MII
#endif

/* SPL part */
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SPL_LDSCRIPT	"arch/microblaze/cpu/u-boot-spl.lds"

#define CONFIG_SPL_RAM_DEVICE
#ifdef CONFIG_SYS_FLASH_BASE
# define CONFIG_SPL_NOR_SUPPORT
# define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
#endif

/* for booting directly linux */
#define CONFIG_SPL_OS_BOOT

#define CONFIG_SYS_OS_BASE		(CONFIG_SYS_FLASH_BASE + \
					 0x60000)
#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
					 0x40000)
#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
					 0x1000000)

/* SP location before relocation, must use scratch RAM */
/* BRAM start */
#define CONFIG_SYS_INIT_RAM_ADDR	0x0
/* BRAM size - will be generated */
#define CONFIG_SYS_INIT_RAM_SIZE	0x100000

# define CONFIG_SPL_STACK_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 CONFIG_SYS_MALLOC_F_LEN)

/* Just for sure that there is a space for stack */
#define CONFIG_SPL_STACK_SIZE		0x100

#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE

#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_INIT_RAM_SIZE - \
					 CONFIG_SYS_INIT_RAM_ADDR - \
					 CONFIG_SYS_MALLOC_F_LEN - \
					 CONFIG_SPL_STACK_SIZE)

#endif	/* __CONFIG_H */
Commit	Line	Data
76316a31	1	/*
4aecfb16	2	* (C) Copyright 2007-2010 Michal Simek
76316a31	3	*
cb1bc63b	4	* Michal SIMEK <monstr@monstr.eu>
76316a31	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
76316a31 MS	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
52a822ed	12	#include "../board/xilinx/microblaze-generic/xparameters.h"
76316a31	13
4aecfb16	14	/* MicroBlaze CPU */
1a50f164	15	#define MICROBLAZE_V5 1
76316a31	16
bcec8f49	17	/* linear and spi flash memory */
1fe7e8fa SL	18	#ifdef XILINX_FLASH_START
1fe7e8fa SL	19	#define FLASH
bcec8f49	20	#undef SPIFLASH
1fe7e8fa SL	21	#undef RAMENV /* hold environment in flash */
1fe7e8fa SL	22	#else
bcec8f49	23	#ifdef XILINX_SPI_FLASH_BASEADDR
1fe7e8fa	24	#undef FLASH
bcec8f49 SL	25	#define SPIFLASH
	26	#undef RAMENV /* hold environment in flash */
	27	#else
	28	#undef FLASH
	29	#undef SPIFLASH
1fe7e8fa SL	30	#define RAMENV /* hold environment in RAM */
1fe7e8fa SL	31	#endif
bcec8f49	32	#endif
1fe7e8fa	33
76316a31	34	/* uart */
67659e2e MS	35	# define CONFIG_BAUDRATE 115200
	36	/* The following table includes the supported baudrates */
	37	# define CONFIG_SYS_BAUDRATE_TABLE \
	38	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
	39
76316a31	40	/* setting reset address */
14d0a02a	41	/#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE/
76316a31 MS	42
76316a31 MS	43	/* gpio */
4c6a6f02	44	#ifdef XILINX_GPIO_BASEADDR
4e779ad2	45	# define CONFIG_XILINX_GPIO
4aecfb16	46	# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
4c6a6f02	47	#endif
76316a31 MS	48
76316a31 MS	49	/* interrupt controller */
4d49b280	50	#ifdef XILINX_INTC_BASEADDR
4aecfb16 MS	51	# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
4aecfb16 MS	52	# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
4d49b280	53	#endif
76316a31 MS	54
76316a31 MS	55	/* timer */
bcbb046b	56	#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
4aecfb16 MS	57	# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
4aecfb16 MS	58	# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
4d49b280	59	#endif
bcbb046b	60
0f21f98d MS	61	/* watchdog */
	62	#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
	63	# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
	64	# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
b5e9b9a9 MS	65	# ifndef CONFIG_SPL_BUILD
	66	# define CONFIG_HW_WATCHDOG
	67	# define CONFIG_XILINX_TB_WATCHDOG
	68	# endif
0f21f98d MS	69	#endif
0f21f98d MS	70
0f925822 MY	71	#if !defined(CONFIG_OF_CONTROL) \|\| \
0f925822 MY	72	(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL))
76316a31	73	/* ddr sdram - main memory */
e945f6dc MS	74	# define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
	75	# define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
	76	#endif
	77
	78	#define CONFIG_SYS_MALLOC_LEN 0xC0000
	79
	80	/* Stack location before relocation */
4fcd0b33 MS	81	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
4fcd0b33 MS	82	CONFIG_SYS_MALLOC_F_LEN)
76316a31	83
8f371b18 SL	84	/*
	85	* CFI flash memory layout - Example
	86	* CONFIG_SYS_FLASH_BASE = 0x2200_0000;
	87	* CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
	88	*
	89	* SECT_SIZE = 0x20000; 128kB is one sector
	90	* CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
	91	*
	92	* 0x2200_0000 CONFIG_SYS_FLASH_BASE
	93	* FREE 256kB
	94	* 0x2204_0000 CONFIG_ENV_ADDR
	95	* ENV_AREA 128kB
	96	* 0x2206_0000
	97	* FREE
	98	* 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
	99	*
	100	*/
	101
76316a31	102	#ifdef FLASH
4aecfb16 MS	103	# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
	104	# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
	105	# define CONFIG_SYS_FLASH_CFI 1
	106	# define CONFIG_FLASH_CFI_DRIVER 1
	107	/* ?empty sector */
	108	# define CONFIG_SYS_FLASH_EMPTY_INFO 1
	109	/* max number of memory banks */
	110	# define CONFIG_SYS_MAX_FLASH_BANKS 1
	111	/* max number of sectors on one chip */
	112	# define CONFIG_SYS_MAX_FLASH_SECT 512
	113	/* hardware flash protection */
	114	# define CONFIG_SYS_FLASH_PROTECTION
22ff7f4d MS	115	/* use buffered writes (20x faster) */
22ff7f4d MS	116	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
4aecfb16 MS	117	# ifdef RAMENV
	118	# define CONFIG_ENV_IS_NOWHERE 1
	119	# define CONFIG_ENV_SIZE 0x1000
	120	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	121
bcec8f49	122	# else /* FLASH && !RAMENV */
4aecfb16 MS	123	# define CONFIG_ENV_IS_IN_FLASH 1
	124	/* 128K(one sector) for env */
	125	# define CONFIG_ENV_SECT_SIZE 0x20000
	126	# define CONFIG_ENV_ADDR \
	127	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
	128	# define CONFIG_ENV_SIZE 0x20000
bcec8f49	129	# endif /* FLASH && !RAMBOOT */
76316a31	130	#else /* !FLASH */
bcec8f49 SL	131
	132	#ifdef SPIFLASH
	133	# define CONFIG_SYS_NO_FLASH 1
	134	# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
bcec8f49	135	# define CONFIG_SPI 1
bcec8f49 SL	136	# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	137	# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
	138	# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
	139
	140	# ifdef RAMENV
	141	# define CONFIG_ENV_IS_NOWHERE 1
	142	# define CONFIG_ENV_SIZE 0x1000
	143	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	144
	145	# else /* SPIFLASH && !RAMENV */
	146	# define CONFIG_ENV_IS_IN_SPI_FLASH 1
	147	# define CONFIG_ENV_SPI_MODE SPI_MODE_3
	148	# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	149	# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	150	/* 128K(two sectors) for env */
	151	# define CONFIG_ENV_SECT_SIZE 0x10000
	152	# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
	153	/* Warning: adjust the offset in respect of other flash content and size */
	154	# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
	155	# endif /* SPIFLASH && !RAMBOOT */
	156	#else /* !SPIFLASH */
	157
4aecfb16 MS	158	/* ENV in RAM */
	159	# define CONFIG_SYS_NO_FLASH 1
	160	# define CONFIG_ENV_IS_NOWHERE 1
	161	# define CONFIG_ENV_SIZE 0x1000
	162	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
bcec8f49	163	#endif /* !SPIFLASH */
76316a31 MS	164	#endif /* !FLASH */
76316a31 MS	165
e9b737de	166	#if defined(XILINX_USE_ICACHE)
4aecfb16	167	# define CONFIG_ICACHE
e9b737de	168	#else
4aecfb16	169	# undef CONFIG_ICACHE
e9b737de MS	170	#endif
	171
	172	#if defined(XILINX_USE_DCACHE)
4aecfb16	173	# define CONFIG_DCACHE
e9b737de	174	#else
4aecfb16	175	# undef CONFIG_DCACHE
e9b737de MS	176	#endif
e9b737de MS	177
5811830f MS	178	#ifndef XILINX_DCACHE_BYTE_SIZE
	179	#define XILINX_DCACHE_BYTE_SIZE 32768
	180	#endif
	181
079a136c JL	182	/*
	183	* BOOTP options
	184	*/
	185	#define CONFIG_BOOTP_BOOTFILESIZE
	186	#define CONFIG_BOOTP_BOOTPATH
	187	#define CONFIG_BOOTP_GATEWAY
	188	#define CONFIG_BOOTP_HOSTNAME
76316a31	189
5dc11a51 JL	190	/*
	191	* Command line configuration.
	192	*/
5dc11a51	193	#define CONFIG_CMD_ASKENV
5dc11a51	194	#define CONFIG_CMD_IRQ
5dc11a51	195	#define CONFIG_CMD_MFSL
4d49b280	196
e9b737de	197	#if defined(CONFIG_DCACHE) \|\| defined(CONFIG_ICACHE)
4aecfb16	198	# define CONFIG_CMD_CACHE
e9b737de	199	#else
4aecfb16	200	# undef CONFIG_CMD_CACHE
e9b737de MS	201	#endif
e9b737de MS	202
5dc11a51	203	#if defined(FLASH)
4aecfb16	204	# define CONFIG_CMD_JFFS2
7cfb13a7 SL	205	# define CONFIG_CMD_UBI
7cfb13a7 SL	206	# undef CONFIG_CMD_UBIFS
4aecfb16	207
bcec8f49	208	# if !defined(RAMENV)
bcec8f49 SL	209	# define CONFIG_CMD_SAVES
	210	# endif
	211
	212	#else
	213	#if defined(SPIFLASH)
	214	# define CONFIG_CMD_SF
	215
4aecfb16	216	# if !defined(RAMENV)
4aecfb16 MS	217	# define CONFIG_CMD_SAVES
4aecfb16 MS	218	# endif
853643d8	219	#else
4aecfb16	220	# undef CONFIG_CMD_JFFS2
2cce2d32 SL	221	# undef CONFIG_CMD_UBI
2cce2d32 SL	222	# undef CONFIG_CMD_UBIFS
5dc11a51	223	#endif
bcec8f49	224	#endif
76316a31	225
5dc11a51	226	#if defined(CONFIG_CMD_JFFS2)
7cfb13a7 SL	227	# define CONFIG_MTD_PARTITIONS
	228	#endif
	229
	230	#if defined(CONFIG_CMD_UBIFS)
	231	# define CONFIG_CMD_UBI
	232	# define CONFIG_LZO
	233	#endif
	234
	235	#if defined(CONFIG_CMD_UBI)
	236	# define CONFIG_MTD_PARTITIONS
	237	# define CONFIG_RBTREE
	238	#endif
	239
	240	#if defined(CONFIG_MTD_PARTITIONS)
	241	/* MTD partitions */
68d7d651	242	#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
942556a9 SR	243	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	244	#define CONFIG_FLASH_CFI_MTD
c82a541d	245	#define MTDIDS_DEFAULT "nor0=flash-0"
144876a3 MS	246
144876a3 MS	247	/* default mtd partition table */
c82a541d	248	#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
144876a3 MS	249	"256k(env),3m(kernel),1m(romfs),"\
	250	"1m(cramfs),-(jffs2)"
	251	#endif
	252
4aecfb16 MS	253	/* size of console buffer */
	254	#define CONFIG_SYS_CBSIZE 512
	255	/* print buffer size */
	256	#define CONFIG_SYS_PBSIZE \
	257	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	258	/* max number of command args */
	259	#define CONFIG_SYS_MAXARGS 15
6d0f6bcf	260	#define CONFIG_SYS_LONGHELP
4aecfb16 MS	261	/* default load address */
4aecfb16 MS	262	#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
76316a31	263
330e5545	264	#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
76316a31	265	#define CONFIG_BOOTARGS "root=romfs"
330e5545	266	#define CONFIG_HOSTNAME XILINX_BOARD_NAME
853643d8	267	#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
76316a31	268	#define CONFIG_IPADDR 192.168.0.3
853643d8 MS	269	#define CONFIG_SERVERIP 192.168.0.5
853643d8 MS	270	#define CONFIG_GATEWAYIP 192.168.0.1
76316a31 MS	271
76316a31 MS	272	/* architecture dependent code */
6d0f6bcf	273	#define CONFIG_SYS_USR_EXCEP /* user exception */
76316a31	274
0900bee9	275	#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
144876a3	276
4aecfb16	277	#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
c82a541d SL	278	"nor0=flash-0\0"\
c82a541d SL	279	"mtdparts=mtdparts=flash-0:"\
144876a3	280	"256k(u-boot),256k(env),3m(kernel),"\
78376452 MS	281	"1m(romfs),1m(cramfs),-(jffs2)\0"\
	282	"nc=setenv stdout nc;"\
	283	"setenv stdin nc\0" \
	284	"serial=setenv stdout serial;"\
	285	"setenv stdin serial\0"
144876a3	286
188dc16b	287	#define CONFIG_CMDLINE_EDITING
188dc16b	288
78376452 MS	289	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
78376452 MS	290
0900bee9 MS	291	/* Use the HUSH parser */
0900bee9 MS	292	#define CONFIG_SYS_HUSH_PARSER
0900bee9	293
37e892d9 MS	294	/* Enable flat device tree support */
37e892d9 MS	295	#define CONFIG_LMB 1
37e892d9 MS	296	#define CONFIG_OF_LIBFDT 1
37e892d9 MS	297
4632b1ea	298	#if defined(CONFIG_XILINX_AXIEMAC)
f5e5e1ff SL	299	# define CONFIG_MII 1
	300	# define CONFIG_CMD_MII 1
	301	# define CONFIG_PHY_GIGE 1
	302	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
f5e5e1ff SL	303	# define CONFIG_PHY_ATHEROS 1
	304	# define CONFIG_PHY_BROADCOM 1
	305	# define CONFIG_PHY_DAVICOM 1
	306	# define CONFIG_PHY_LXT 1
	307	# define CONFIG_PHY_MARVELL 1
	308	# define CONFIG_PHY_MICREL 1
2014a3de	309	# define CONFIG_PHY_MICREL_KSZ9021
f5e5e1ff SL	310	# define CONFIG_PHY_NATSEMI 1
	311	# define CONFIG_PHY_REALTEK 1
	312	# define CONFIG_PHY_VITESSE 1
	313	#else
	314	# undef CONFIG_MII
	315	# undef CONFIG_CMD_MII
f5e5e1ff SL	316	#endif
f5e5e1ff SL	317
9d242745	318	/* SPL part */
9d242745 MS	319	#define CONFIG_CMD_SPL
	320	#define CONFIG_SPL_FRAMEWORK
	321	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	322	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	323	#define CONFIG_SPL_SERIAL_SUPPORT
	324	#define CONFIG_SPL_BOARD_INIT
	325
	326	#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
	327
	328	#define CONFIG_SPL_RAM_DEVICE
4dd09742 MS	329	#ifdef CONFIG_SYS_FLASH_BASE
	330	# define CONFIG_SPL_NOR_SUPPORT
	331	# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
	332	#endif
9d242745 MS	333
	334	/* for booting directly linux */
	335	#define CONFIG_SPL_OS_BOOT
	336
	337	#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
	338	0x60000)
	339	#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
	340	0x40000)
	341	#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
	342	0x1000000)
	343
	344	/* SP location before relocation, must use scratch RAM */
	345	/* BRAM start */
	346	#define CONFIG_SYS_INIT_RAM_ADDR 0x0
	347	/* BRAM size - will be generated */
ca7d2266	348	#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
9d242745	349
ca7d2266 MS	350	# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	351	CONFIG_SYS_INIT_RAM_SIZE - \
	352	CONFIG_SYS_MALLOC_F_LEN)
9d242745 MS	353
	354	/* Just for sure that there is a space for stack */
	355	#define CONFIG_SPL_STACK_SIZE 0x100
	356
9d242745 MS	357	#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
	358
	359	#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
	360	CONFIG_SYS_INIT_RAM_ADDR - \
ca7d2266	361	CONFIG_SYS_MALLOC_F_LEN - \
9d242745 MS	362	CONFIG_SPL_STACK_SIZE)
9d242745 MS	363
76316a31	364	#endif /* __CONFIG_H */