[people/ms/u-boot.git] / include / configs / ml401.h

/*
 * (C) Copyright 2007-2008 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/xilinx/ml401/xparameters.h"

#define	CONFIG_MICROBLAZE	1	/* MicroBlaze CPU */
#define	MICROBLAZE_V5		1
#define	CONFIG_ML401		1	/* ML401 Board */

/* uart */
#ifdef XILINX_UARTLITE_BASEADDR
#define	CONFIG_XILINX_UARTLITE
#define	CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
#define	CONFIG_BAUDRATE		XILINX_UARTLITE_BAUDRATE
#define	CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
#else
#ifdef XILINX_UART16550_BASEADDR
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	4
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550_COM1	XILINX_UART16550_BASEADDR
#define CONFIG_SYS_NS16550_CLK		XILINX_UART16550_CLOCK_HZ
#define	CONFIG_BAUDRATE		115200
#define	CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 115200 }
#endif
#endif

/* setting reset address */
/*#define	CONFIG_SYS_RESET_ADDRESS	TEXT_BASE*/

/* ethernet */
#ifdef XILINX_EMAC_BASEADDR
#define CONFIG_XILINX_EMAC	1
#define CONFIG_SYS_ENET
#else
#ifdef XILINX_EMACLITE_BASEADDR
#define CONFIG_XILINX_EMACLITE	1
#define CONFIG_SYS_ENET
#endif
#endif
#undef ET_DEBUG

/* gpio */
#ifdef XILINX_GPIO_BASEADDR
#define	CONFIG_SYS_GPIO_0		1
#define	CONFIG_SYS_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
#endif

/* interrupt controller */
#ifdef XILINX_INTC_BASEADDR
#define	CONFIG_SYS_INTC_0		1
#define	CONFIG_SYS_INTC_0_ADDR		XILINX_INTC_BASEADDR
#define	CONFIG_SYS_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
#endif

/* timer */
#ifdef XILINX_TIMER_BASEADDR
#if (XILINX_TIMER_IRQ != -1)
#define	CONFIG_SYS_TIMER_0		1
#define	CONFIG_SYS_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
#define	CONFIG_SYS_TIMER_0_IRQ		XILINX_TIMER_IRQ
#define	FREQUENCE		XILINX_CLOCK_FREQ
#define	CONFIG_SYS_TIMER_0_PRELOAD	( FREQUENCE/1000 )
#endif
#else
#ifdef XILINX_CLOCK_FREQ
#define	CONFIG_XILINX_CLOCK_FREQ	XILINX_CLOCK_FREQ
#else
#error BAD CLOCK FREQ
#endif
#endif
/* FSL */
/* #define	CONFIG_SYS_FSL_2 */
/* #define	FSL_INTR_2	1 */

/*
 * memory layout - Example
 * TEXT_BASE = 0x1200_0000;
 * CONFIG_SYS_SRAM_BASE = 0x1000_0000;
 * CONFIG_SYS_SRAM_SIZE = 0x0400_0000;
 *
 * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
 * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
 * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
 *
 * 0x1000_0000	CONFIG_SYS_SDRAM_BASE
 *					FREE
 * 0x1200_0000	TEXT_BASE
 *		U-BOOT code
 * 0x1202_0000
 *					FREE
 *
 *					STACK
 * 0x13F7_F000	CONFIG_SYS_MALLOC_BASE
 *					MALLOC_AREA	256kB	Alloc
 * 0x11FB_F000	CONFIG_SYS_MONITOR_BASE
 *					MONITOR_CODE	256kB	Env
 * 0x13FF_F000	CONFIG_SYS_GBL_DATA_OFFSET
 *					GLOBAL_DATA	4kB	bd, gd
 * 0x1400_0000	CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
 */

/* ddr sdram - main memory */
#define	CONFIG_SYS_SDRAM_BASE		XILINX_RAM_START
#define	CONFIG_SYS_SDRAM_SIZE		XILINX_RAM_SIZE
#define	CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)

/* global pointer */
#define	CONFIG_SYS_GBL_DATA_SIZE	0x1000	/* size of global data */
/* start of global data */
#define	CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)

/* monitor code */
#define	SIZE			0x40000
#define	CONFIG_SYS_MONITOR_LEN		SIZE
#define	CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN)
#define	CONFIG_SYS_MONITOR_END		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define	CONFIG_SYS_MALLOC_LEN		SIZE
#define	CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)

/* stack */
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_MONITOR_BASE

/*#define	RAMENV */
#define	FLASH

#ifdef FLASH
	#define	CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
	#define	CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
	#define	CONFIG_SYS_FLASH_CFI		1
	#define	CONFIG_FLASH_CFI_DRIVER	1
	#define	CONFIG_SYS_FLASH_EMPTY_INFO	1	/* ?empty sector */
	#define	CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
	#define	CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
	#define	CONFIG_SYS_FLASH_PROTECTION		/* hardware flash protection */

	#ifdef	RAMENV
		#define	CONFIG_ENV_IS_NOWHERE	1
		#define	CONFIG_ENV_SIZE		0x1000
		#define	CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

	#else	/* !RAMENV */
		#define	CONFIG_ENV_IS_IN_FLASH	1
		#define	CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
		#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
		#define	CONFIG_ENV_SIZE		0x40000
	#endif /* !RAMBOOT */
#else /* !FLASH */
	/* ENV in RAM */
	#define	CONFIG_SYS_NO_FLASH		1
	#define	CONFIG_ENV_IS_NOWHERE	1
	#define	CONFIG_ENV_SIZE		0x1000
	#define	CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	#define	CONFIG_SYS_FLASH_PROTECTION		/* hardware flash protection */
#endif /* !FLASH */

/* system ace */
#ifdef XILINX_SYSACE_BASEADDR
	#define	CONFIG_SYSTEMACE
	/* #define DEBUG_SYSTEMACE */
	#define	SYSTEMACE_CONFIG_FPGA
	#define	CONFIG_SYS_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
	#define	CONFIG_SYS_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
	#define	CONFIG_DOS_PARTITION
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MFSL

#ifndef CONFIG_SYS_ENET
	#undef CONFIG_CMD_NET
#else
	#define CONFIG_CMD_PING
#endif

#if defined(CONFIG_SYSTEMACE)
	#define CONFIG_CMD_EXT2
	#define CONFIG_CMD_FAT
#endif

#if defined(FLASH)
	#define CONFIG_CMD_ECHO
	#define CONFIG_CMD_FLASH
	#define CONFIG_CMD_IMLS
	#define CONFIG_CMD_JFFS2

	#if !defined(RAMENV)
		#define CONFIG_CMD_ENV
		#define CONFIG_CMD_SAVES
	#endif
#else
	#undef CONFIG_CMD_FLASH
#endif

#if defined(CONFIG_CMD_JFFS2)
/* JFFS2 partitions */
#define CONFIG_JFFS2_CMDLINE	/* mtdparts command line support */
#define MTDIDS_DEFAULT		"nor0=ml401-0"

/* default mtd partition table */
#define MTDPARTS_DEFAULT	"mtdparts=ml401-0:256k(u-boot),"\
				"256k(env),3m(kernel),1m(romfs),"\
				"1m(cramfs),-(jffs2)"
#endif

/* Miscellaneous configurable options */
#define	CONFIG_SYS_PROMPT	"U-Boot-mONStR> "
#define	CONFIG_SYS_CBSIZE	512	/* size of console buffer */
#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
#define	CONFIG_SYS_MAXARGS	15	/* max number of command args */
#define	CONFIG_SYS_LONGHELP
#define	CONFIG_SYS_LOAD_ADDR	0x12000000 /* default load address */

#define	CONFIG_BOOTDELAY	30
#define	CONFIG_BOOTARGS		"root=romfs"
#define	CONFIG_HOSTNAME		"ml401"
#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
#define	CONFIG_IPADDR		192.168.0.3
#define	CONFIG_SERVERIP		192.168.0.5
#define	CONFIG_GATEWAYIP	192.168.0.1
#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD

/* architecture dependent code */
#define	CONFIG_SYS_USR_EXCEP	/* user exception */
#define CONFIG_SYS_HZ	1000

#define	CONFIG_PREBOOT		"echo U-BOOT for ML401;setenv preboot;echo"

#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" /* hardware flash protection */\
					"nor0=ml401-0\0"\
					"mtdparts=mtdparts=ml401-0:"\
					"256k(u-boot),256k(env),3m(kernel),"\
					"1m(romfs),1m(cramfs),-(jffs2)\0"

#define CONFIG_CMDLINE_EDITING
#define CONFIG_OF_LIBFDT	1

#endif	/* __CONFIG_H */
Commit	Line	Data
76316a31	1	/*
188dc16b	2	* (C) Copyright 2007-2008 Michal Simek
76316a31	3	*
cb1bc63b	4	* Michal SIMEK <monstr@monstr.eu>
76316a31 MS	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	#include "../board/xilinx/ml401/xparameters.h"
	29
	30	#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
1a50f164	31	#define MICROBLAZE_V5 1
76316a31 MS	32	#define CONFIG_ML401 1 /* ML401 Board */
	33
	34	/* uart */
af7ae1a4	35	#ifdef XILINX_UARTLITE_BASEADDR
853643d8	36	#define CONFIG_XILINX_UARTLITE
af7ae1a4 MS	37	#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
af7ae1a4 MS	38	#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
6d0f6bcf	39	#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
af7ae1a4 MS	40	#else
af7ae1a4 MS	41	#ifdef XILINX_UART16550_BASEADDR
6d0f6bcf JCPV	42	#define CONFIG_SYS_NS16550
	43	#define CONFIG_SYS_NS16550_SERIAL
	44	#define CONFIG_SYS_NS16550_REG_SIZE 4
af7ae1a4	45	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	46	#define CONFIG_SYS_NS16550_COM1 XILINX_UART16550_BASEADDR
6d0f6bcf JCPV	47	#define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
af7ae1a4	48	#define CONFIG_BAUDRATE 115200
6d0f6bcf	49	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 115200 }
af7ae1a4 MS	50	#endif
af7ae1a4 MS	51	#endif
76316a31 MS	52
76316a31 MS	53	/* setting reset address */
6d0f6bcf	54	/#define CONFIG_SYS_RESET_ADDRESS TEXT_BASE/
76316a31	55
17980495	56	/* ethernet */
e5845e21 MS	57	#ifdef XILINX_EMAC_BASEADDR
e5845e21 MS	58	#define CONFIG_XILINX_EMAC 1
6d0f6bcf	59	#define CONFIG_SYS_ENET
e5845e21 MS	60	#else
	61	#ifdef XILINX_EMACLITE_BASEADDR
	62	#define CONFIG_XILINX_EMACLITE 1
6d0f6bcf	63	#define CONFIG_SYS_ENET
e5845e21 MS	64	#endif
	65	#endif
	66	#undef ET_DEBUG
17980495	67
76316a31	68	/* gpio */
4c6a6f02	69	#ifdef XILINX_GPIO_BASEADDR
6d0f6bcf JCPV	70	#define CONFIG_SYS_GPIO_0 1
6d0f6bcf JCPV	71	#define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
4c6a6f02	72	#endif
76316a31 MS	73
76316a31 MS	74	/* interrupt controller */
4d49b280	75	#ifdef XILINX_INTC_BASEADDR
6d0f6bcf JCPV	76	#define CONFIG_SYS_INTC_0 1
	77	#define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
	78	#define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
4d49b280	79	#endif
76316a31 MS	80
76316a31 MS	81	/* timer */
4d49b280 MS	82	#ifdef XILINX_TIMER_BASEADDR
4d49b280 MS	83	#if (XILINX_TIMER_IRQ != -1)
6d0f6bcf JCPV	84	#define CONFIG_SYS_TIMER_0 1
	85	#define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
	86	#define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
17980495	87	#define FREQUENCE XILINX_CLOCK_FREQ
6d0f6bcf	88	#define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 )
4d49b280 MS	89	#endif
	90	#else
	91	#ifdef XILINX_CLOCK_FREQ
853643d8	92	#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
4d49b280 MS	93	#else
	94	#error BAD CLOCK FREQ
	95	#endif
	96	#endif
19bf1fba	97	/* FSL */
6d0f6bcf	98	/* #define CONFIG_SYS_FSL_2 */
188dc16b	99	/* #define FSL_INTR_2 1 */
19bf1fba	100
76316a31 MS	101	/*
	102	* memory layout - Example
	103	* TEXT_BASE = 0x1200_0000;
6d0f6bcf JCPV	104	* CONFIG_SYS_SRAM_BASE = 0x1000_0000;
6d0f6bcf JCPV	105	* CONFIG_SYS_SRAM_SIZE = 0x0400_0000;
76316a31	106	*
6d0f6bcf JCPV	107	* CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
	108	* CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
	109	* CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
76316a31	110	*
6d0f6bcf	111	* 0x1000_0000 CONFIG_SYS_SDRAM_BASE
76316a31 MS	112	* FREE
	113	* 0x1200_0000 TEXT_BASE
	114	* U-BOOT code
	115	* 0x1202_0000
	116	* FREE
	117	*
	118	* STACK
6d0f6bcf	119	* 0x13F7_F000 CONFIG_SYS_MALLOC_BASE
17980495	120	* MALLOC_AREA 256kB Alloc
6d0f6bcf	121	* 0x11FB_F000 CONFIG_SYS_MONITOR_BASE
17980495	122	* MONITOR_CODE 256kB Env
6d0f6bcf	123	* 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET
853643d8	124	* GLOBAL_DATA 4kB bd, gd
6d0f6bcf	125	* 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
76316a31 MS	126	*/
	127
	128	/* ddr sdram - main memory */
6d0f6bcf JCPV	129	#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
	130	#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
	131	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	132	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
76316a31 MS	133
76316a31 MS	134	/* global pointer */
6d0f6bcf	135	#define CONFIG_SYS_GBL_DATA_SIZE 0x1000 /* size of global data */
32556443	136	/* start of global data */
6d0f6bcf	137	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
76316a31 MS	138
	139	/* monitor code */
	140	#define SIZE 0x40000
6d0f6bcf JCPV	141	#define CONFIG_SYS_MONITOR_LEN SIZE
	142	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN)
	143	#define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	144	#define CONFIG_SYS_MALLOC_LEN SIZE
	145	#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
76316a31 MS	146
76316a31 MS	147	/* stack */
6d0f6bcf	148	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MONITOR_BASE
76316a31 MS	149
	150	/#define RAMENV /
	151	#define FLASH
	152
	153	#ifdef FLASH
6d0f6bcf JCPV	154	#define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
	155	#define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
	156	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	157	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	158	#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */
	159	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	160	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
	161	#define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */
76316a31 MS	162
76316a31 MS	163	#ifdef RAMENV
93f6d725	164	#define CONFIG_ENV_IS_NOWHERE 1
0e8d1586	165	#define CONFIG_ENV_SIZE 0x1000
6d0f6bcf	166	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
76316a31 MS	167
76316a31 MS	168	#else /* !RAMENV */
5a1aceb0	169	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	170	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
6d0f6bcf	171	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
0e8d1586	172	#define CONFIG_ENV_SIZE 0x40000
76316a31 MS	173	#endif /* !RAMBOOT */
	174	#else /* !FLASH */
	175	/* ENV in RAM */
6d0f6bcf	176	#define CONFIG_SYS_NO_FLASH 1
93f6d725	177	#define CONFIG_ENV_IS_NOWHERE 1
0e8d1586	178	#define CONFIG_ENV_SIZE 0x1000
6d0f6bcf JCPV	179	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
6d0f6bcf JCPV	180	#define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */
76316a31 MS	181	#endif /* !FLASH */
76316a31 MS	182
853643d8 MS	183	/* system ace */
	184	#ifdef XILINX_SYSACE_BASEADDR
	185	#define CONFIG_SYSTEMACE
	186	/* #define DEBUG_SYSTEMACE */
	187	#define SYSTEMACE_CONFIG_FPGA
6d0f6bcf JCPV	188	#define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
6d0f6bcf JCPV	189	#define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
853643d8 MS	190	#define CONFIG_DOS_PARTITION
	191	#endif
	192
079a136c JL	193	/*
	194	* BOOTP options
	195	*/
	196	#define CONFIG_BOOTP_BOOTFILESIZE
	197	#define CONFIG_BOOTP_BOOTPATH
	198	#define CONFIG_BOOTP_GATEWAY
	199	#define CONFIG_BOOTP_HOSTNAME
76316a31	200
5dc11a51 JL	201	/*
	202	* Command line configuration.
	203	*/
	204	#include <config_cmd_default.h>
	205
	206	#define CONFIG_CMD_ASKENV
5dc11a51	207	#define CONFIG_CMD_CACHE
5dc11a51	208	#define CONFIG_CMD_IRQ
5dc11a51	209	#define CONFIG_CMD_MFSL
4d49b280	210
6d0f6bcf	211	#ifndef CONFIG_SYS_ENET
4d49b280 MS	212	#undef CONFIG_CMD_NET
	213	#else
	214	#define CONFIG_CMD_PING
	215	#endif
853643d8 MS	216
	217	#if defined(CONFIG_SYSTEMACE)
	218	#define CONFIG_CMD_EXT2
	219	#define CONFIG_CMD_FAT
	220	#endif
5dc11a51 JL	221
	222	#if defined(FLASH)
	223	#define CONFIG_CMD_ECHO
	224	#define CONFIG_CMD_FLASH
	225	#define CONFIG_CMD_IMLS
	226	#define CONFIG_CMD_JFFS2
	227
	228	#if !defined(RAMENV)
	229	#define CONFIG_CMD_ENV
	230	#define CONFIG_CMD_SAVES
76316a31	231	#endif
853643d8 MS	232	#else
853643d8 MS	233	#undef CONFIG_CMD_FLASH
5dc11a51	234	#endif
76316a31	235
5dc11a51	236	#if defined(CONFIG_CMD_JFFS2)
144876a3 MS	237	/* JFFS2 partitions */
	238	#define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */
	239	#define MTDIDS_DEFAULT "nor0=ml401-0"
	240
	241	/* default mtd partition table */
	242	#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\
	243	"256k(env),3m(kernel),1m(romfs),"\
	244	"1m(cramfs),-(jffs2)"
	245	#endif
	246
76316a31	247	/* Miscellaneous configurable options */
6d0f6bcf JCPV	248	#define CONFIG_SYS_PROMPT "U-Boot-mONStR> "
	249	#define CONFIG_SYS_CBSIZE 512 /* size of console buffer */
	250	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
	251	#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
	252	#define CONFIG_SYS_LONGHELP
	253	#define CONFIG_SYS_LOAD_ADDR 0x12000000 /* default load address */
76316a31	254
144876a3	255	#define CONFIG_BOOTDELAY 30
76316a31 MS	256	#define CONFIG_BOOTARGS "root=romfs"
76316a31 MS	257	#define CONFIG_HOSTNAME "ml401"
853643d8	258	#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
76316a31	259	#define CONFIG_IPADDR 192.168.0.3
853643d8 MS	260	#define CONFIG_SERVERIP 192.168.0.5
853643d8 MS	261	#define CONFIG_GATEWAYIP 192.168.0.1
76316a31 MS	262	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
	263
	264	/* architecture dependent code */
6d0f6bcf JCPV	265	#define CONFIG_SYS_USR_EXCEP /* user exception */
6d0f6bcf JCPV	266	#define CONFIG_SYS_HZ 1000
76316a31	267
144876a3 MS	268	#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo"
	269
	270	#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
	271	"nor0=ml401-0\0"\
	272	"mtdparts=mtdparts=ml401-0:"\
	273	"256k(u-boot),256k(env),3m(kernel),"\
	274	"1m(romfs),1m(cramfs),-(jffs2)\0"
	275
188dc16b MS	276	#define CONFIG_CMDLINE_EDITING
	277	#define CONFIG_OF_LIBFDT 1
	278
76316a31	279	#endif /* __CONFIG_H */