[people/ms/u-boot.git] / include / configs / ml401.h

/*
 * (C) Copyright 2007 Czech Technical University.
 *
 * Michal SIMEK <monstr@seznam.cz>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/xilinx/ml401/xparameters.h"

#define	CONFIG_MICROBLAZE	1	/* MicroBlaze CPU */
#define	CONFIG_ML401		1	/* ML401 Board */

/* uart */
#define	CONFIG_SERIAL_BASE	CONFIG_XILINX_UARTLITE_0_BASEADDR
#define	CONFIG_BAUDRATE		CONFIG_XILINX_UARTLITE_0_BAUDRATE
#define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }

/* setting reset address */
#define	CFG_RESET_ADDRESS	TEXT_BASE

/* gpio */
#define	CFG_GPIO_0		1
#define	CFG_GPIO_0_ADDR		CONFIG_XILINX_GPIO_0_BASEADDR

/* interrupt controller */
#define	CFG_INTC_0		1
#define	CFG_INTC_0_ADDR		CONFIG_XILINX_INTC_0_BASEADDR
#define	CFG_INTC_0_NUM		CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS

/* timer */
#define	CFG_TIMER_0		1
#define	CFG_TIMER_0_ADDR	CONFIG_XILINX_TIMER_0_BASEADDR
#define	CFG_TIMER_0_IRQ		CONFIG_XILINX_TIMER_0_IRQ
#define	FREQUENCE		66666666
#define	CFG_TIMER_0_PRELOAD	( FREQUENCE/1000 )

/*
 * memory layout - Example
 * TEXT_BASE = 0x1200_0000;
 * CFG_SRAM_BASE = 0x1000_0000;
 * CFG_SRAM_SIZE = 0x0400_0000;
 *
 * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
 * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
 *
 * 0x1000_0000	CFG_SDRAM_BASE
 *					FREE
 * 0x1200_0000	TEXT_BASE
 *		U-BOOT code
 * 0x1202_0000
 *					FREE
 *
 *					STACK
 * 0x11FB_F000	CFG_MONITOR_BASE
 *					MONITOR_CODE
 * 0x13FF_F000	CFG_GBL_DATA_OFFSET
 * 					GLOBAL_DATA
 * 0x1400_0000	CFG_SDRAM_BASE + CFG_SDRAM_SIZE
 */

/* ddr sdram - main memory */
#define	CFG_SDRAM_BASE		CONFIG_XILINX_ERAM_START
#define	CFG_SDRAM_SIZE		CONFIG_XILINX_ERAM_SIZE
#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
#define	CFG_MEMTEST_END		(CFG_SDRAM_BASE + 0x1000)

/* global pointer */
#define	CFG_GBL_DATA_SIZE	0x1000	/* size of global data */
#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */

/* monitor code */
#define	SIZE			0x40000
#define	CFG_MONITOR_LEN		SIZE
#define	CFG_MONITOR_BASE	(CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
#define	CFG_MALLOC_LEN		SIZE

/* stack */
#define	CFG_INIT_SP_OFFSET	CFG_MONITOR_BASE

/*#define	RAMENV */
#define	FLASH

#ifdef FLASH
	#define	CFG_FLASH_BASE		CONFIG_XILINX_FLASH_START
	#define	CFG_FLASH_SIZE		CONFIG_XILINX_FLASH_SIZE
	#define	CFG_FLASH_CFI		1
	#define	CFG_FLASH_CFI_DRIVER	1
	#define	CFG_FLASH_EMPTY_INFO	1	/* ?empty sector */
	#define	CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
	#define	CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */

	#ifdef	RAMENV
		#define	CFG_ENV_IS_NOWHERE	1
		#define	CFG_ENV_SIZE		0x1000
		#define	CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SIZE)

	#else	/* !RAMENV */
		#define	CFG_ENV_IS_IN_FLASH	1
		#define	CFG_ENV_ADDR		0x40000
		#define	CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
		#define	CFG_ENV_SIZE		0x2000
	#endif /* !RAMBOOT */
#else /* !FLASH */
	/* ENV in RAM */
	#define	CFG_NO_FLASH		1
	#define	CFG_ENV_IS_NOWHERE	1
	#define	CFG_ENV_SIZE		0x1000
	#define	CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SIZE)
#endif /* !FLASH */

#ifdef	FLASH
	#ifdef	RAMENV
	#define	CONFIG_COMMANDS	(CONFIG__CMD_DFL |\
				CFG_CMD_MEMORY |\
				CFG_CMD_MISC |\
				CFG_CMD_AUTOSCRIPT |\
				CFG_CMD_IRQ |\
				CFG_CMD_ASKENV |\
				CFG_CMD_BDI |\
				CFG_CMD_RUN |\
				CFG_CMD_LOADS |\
				CFG_CMD_LOADB |\
				CFG_CMD_IMI |\
				CFG_CMD_NET |\
				CFG_CMD_CACHE |\
				CFG_CMD_IMLS |\
				CFG_CMD_FLASH |\
				CFG_CMD_PING \
				)
	#else	/* !RAMENV */
	#define	CONFIG_COMMANDS	(CONFIG__CMD_DFL |\
				CFG_CMD_MEMORY |\
				CFG_CMD_MISC |\
				CFG_CMD_AUTOSCRIPT |\
				CFG_CMD_IRQ |\
				CFG_CMD_ASKENV |\
				CFG_CMD_BDI |\
				CFG_CMD_RUN |\
				CFG_CMD_LOADS |\
				CFG_CMD_LOADB |\
				CFG_CMD_IMI |\
				CFG_CMD_NET |\
				CFG_CMD_CACHE |\
				CFG_CMD_IMLS |\
				CFG_CMD_FLASH |\
				CFG_CMD_PING |\
				CFG_CMD_ENV |\
				CFG_CMD_SAVES \
				)

	#endif

#else	/* !FLASH */
	#define	CONFIG_COMMANDS	(CONFIG__CMD_DFL |\
				CFG_CMD_MEMORY |\
				CFG_CMD_MISC |\
				CFG_CMD_AUTOSCRIPT |\
				CFG_CMD_IRQ |\
				CFG_CMD_ASKENV |\
				CFG_CMD_BDI |\
				CFG_CMD_RUN |\
				CFG_CMD_LOADS |\
				CFG_CMD_LOADB |\
				CFG_CMD_IMI |\
				CFG_CMD_NET |\
				CFG_CMD_CACHE |\
				CFG_CMD_PING \
				)
#endif	/* !FLASH */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/* Miscellaneous configurable options */
#define	CFG_PROMPT	"U-Boot-mONStR> "
#define	CFG_CBSIZE	512	/* size of console buffer */
#define	CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
#define	CFG_MAXARGS	15	/* max number of command args */
#define	CFG_LONGHELP
#define	CFG_LOAD_ADDR	0x12000000 /* default load address */

#define	CONFIG_BOOTDELAY 	30
#define	CONFIG_BOOTARGS		"root=romfs"
#define	CONFIG_HOSTNAME		"ml401"
#define	CONFIG_BOOTCOMMAND 	"base 0;tftp 11000000 image.img;bootm"
#define	CONFIG_IPADDR		192.168.0.3
#define	CONFIG_SERVERIP 	192.168.0.5
#define	CONFIG_GATEWAYIP 	192.168.0.1
#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD

/* architecture dependent code */
#define	CFG_USR_EXCEP	/* user exception */
#define CFG_HZ	1000

/* system ace */
/*#define CONFIG_SYSTEMACE
#define DEBUG_SYSTEMACE
#define CFG_SYSTEMACE_BASE 0xCF000000
#define CFG_SYSTEMACE_WIDTH	8
#define CONFIG_DOS_PARTITION
*/
#endif	/* __CONFIG_H */
Commit	Line	Data
76316a31 MS	1	/*
	2	* (C) Copyright 2007 Czech Technical University.
	3	*
	4	* Michal SIMEK <monstr@seznam.cz>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	#include "../board/xilinx/ml401/xparameters.h"
	29
	30	#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
	31	#define CONFIG_ML401 1 /* ML401 Board */
	32
	33	/* uart */
	34	#define CONFIG_SERIAL_BASE CONFIG_XILINX_UARTLITE_0_BASEADDR
	35	#define CONFIG_BAUDRATE CONFIG_XILINX_UARTLITE_0_BAUDRATE
	36	#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
	37
	38	/* setting reset address */
	39	#define CFG_RESET_ADDRESS TEXT_BASE
	40
	41	/* gpio */
	42	#define CFG_GPIO_0 1
	43	#define CFG_GPIO_0_ADDR CONFIG_XILINX_GPIO_0_BASEADDR
	44
	45	/* interrupt controller */
	46	#define CFG_INTC_0 1
	47	#define CFG_INTC_0_ADDR CONFIG_XILINX_INTC_0_BASEADDR
	48	#define CFG_INTC_0_NUM CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS
	49
	50	/* timer */
	51	#define CFG_TIMER_0 1
	52	#define CFG_TIMER_0_ADDR CONFIG_XILINX_TIMER_0_BASEADDR
	53	#define CFG_TIMER_0_IRQ CONFIG_XILINX_TIMER_0_IRQ
	54	#define FREQUENCE 66666666
	55	#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
	56
	57	/*
	58	* memory layout - Example
	59	* TEXT_BASE = 0x1200_0000;
	60	* CFG_SRAM_BASE = 0x1000_0000;
	61	* CFG_SRAM_SIZE = 0x0400_0000;
	62	*
	63	* CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
	64	* CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
65	*
66	* 0x1000_0000 CFG_SDRAM_BASE
67	* FREE
68	* 0x1200_0000 TEXT_BASE
69	* U-BOOT code
70	* 0x1202_0000
71	* FREE
72	*
73	* STACK
74	* 0x11FB_F000 CFG_MONITOR_BASE
75	* MONITOR_CODE
76	* 0x13FF_F000 CFG_GBL_DATA_OFFSET
77	* GLOBAL_DATA
78	* 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
79	*/
80
81	/* ddr sdram - main memory */
82	#define CFG_SDRAM_BASE CONFIG_XILINX_ERAM_START
83	#define CFG_SDRAM_SIZE CONFIG_XILINX_ERAM_SIZE
84	#define CFG_MEMTEST_START CFG_SDRAM_BASE
85	#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000)
86
87	/* global pointer */
88	#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
89	#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
90
91	/* monitor code */
92	#define SIZE 0x40000
93	#define CFG_MONITOR_LEN SIZE
94	#define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
95	#define CFG_MALLOC_LEN SIZE
96
97	/* stack */
98	#define CFG_INIT_SP_OFFSET CFG_MONITOR_BASE
99
100	/#define RAMENV /
101	#define FLASH
102
103	#ifdef FLASH
104	#define CFG_FLASH_BASE CONFIG_XILINX_FLASH_START
105	#define CFG_FLASH_SIZE CONFIG_XILINX_FLASH_SIZE
106	#define CFG_FLASH_CFI 1
107	#define CFG_FLASH_CFI_DRIVER 1
108	#define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */
109	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
110	#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
111
112	#ifdef RAMENV
113	#define CFG_ENV_IS_NOWHERE 1
114	#define CFG_ENV_SIZE 0x1000
115	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
116
117	#else /* !RAMENV */
118	#define CFG_ENV_IS_IN_FLASH 1
119	#define CFG_ENV_ADDR 0x40000
120	#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
121	#define CFG_ENV_SIZE 0x2000
122	#endif /* !RAMBOOT */
123	#else /* !FLASH */
124	/* ENV in RAM */
125	#define CFG_NO_FLASH 1
126	#define CFG_ENV_IS_NOWHERE 1
127	#define CFG_ENV_SIZE 0x1000
128	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
129	#endif /* !FLASH */
130
131	#ifdef FLASH
132	#ifdef RAMENV
133	#define CONFIG_COMMANDS (CONFIG__CMD_DFL \|\
134	CFG_CMD_MEMORY \|\
135	CFG_CMD_MISC \|\
136	CFG_CMD_AUTOSCRIPT \|\
137	CFG_CMD_IRQ \|\
138	CFG_CMD_ASKENV \|\
139	CFG_CMD_BDI \|\
140	CFG_CMD_RUN \|\
141	CFG_CMD_LOADS \|\
142	CFG_CMD_LOADB \|\
143	CFG_CMD_IMI \|\
144	CFG_CMD_NET \|\
145	CFG_CMD_CACHE \|\
146	CFG_CMD_IMLS \|\
147	CFG_CMD_FLASH \|\
148	CFG_CMD_PING \
149	)
150	#else /* !RAMENV */
151	#define CONFIG_COMMANDS (CONFIG__CMD_DFL \|\
152	CFG_CMD_MEMORY \|\
153	CFG_CMD_MISC \|\
154	CFG_CMD_AUTOSCRIPT \|\
155	CFG_CMD_IRQ \|\
156	CFG_CMD_ASKENV \|\
157	CFG_CMD_BDI \|\
158	CFG_CMD_RUN \|\
159	CFG_CMD_LOADS \|\
160	CFG_CMD_LOADB \|\
161	CFG_CMD_IMI \|\
162	CFG_CMD_NET \|\
163	CFG_CMD_CACHE \|\
164	CFG_CMD_IMLS \|\
165	CFG_CMD_FLASH \|\
166	CFG_CMD_PING \|\
167	CFG_CMD_ENV \|\
168	CFG_CMD_SAVES \
169	)
170
171	#endif
172
173	#else /* !FLASH */
174	#define CONFIG_COMMANDS (CONFIG__CMD_DFL \|\
175	CFG_CMD_MEMORY \|\
176	CFG_CMD_MISC \|\
177	CFG_CMD_AUTOSCRIPT \|\
178	CFG_CMD_IRQ \|\
179	CFG_CMD_ASKENV \|\
180	CFG_CMD_BDI \|\
181	CFG_CMD_RUN \|\
182	CFG_CMD_LOADS \|\
183	CFG_CMD_LOADB \|\
184	CFG_CMD_IMI \|\
185	CFG_CMD_NET \|\
186	CFG_CMD_CACHE \|\
187	CFG_CMD_PING \
188	)
189	#endif /* !FLASH */
190	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
191	#include <cmd_confdefs.h>
192
193	/* Miscellaneous configurable options */
194	#define CFG_PROMPT "U-Boot-mONStR> "
195	#define CFG_CBSIZE 512 /* size of console buffer */
196	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
197	#define CFG_MAXARGS 15 /* max number of command args */
198	#define CFG_LONGHELP
199	#define CFG_LOAD_ADDR 0x12000000 /* default load address */
200
201	#define CONFIG_BOOTDELAY 30
202	#define CONFIG_BOOTARGS "root=romfs"
203	#define CONFIG_HOSTNAME "ml401"
204	#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
205	#define CONFIG_IPADDR 192.168.0.3
206	#define CONFIG_SERVERIP 192.168.0.5
207	#define CONFIG_GATEWAYIP 192.168.0.1
208	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
209
210	/* architecture dependent code */
211	#define CFG_USR_EXCEP /* user exception */
212	#define CFG_HZ 1000
213
214	/* system ace */
215	/*#define CONFIG_SYSTEMACE
216	#define DEBUG_SYSTEMACE
217	#define CFG_SYSTEMACE_BASE 0xCF000000
218	#define CFG_SYSTEMACE_WIDTH 8
219	#define CONFIG_DOS_PARTITION
220	*/
221	#endif /* __CONFIG_H */