[people/ms/u-boot.git] / include / configs / ml401.h

/*
 * (C) Copyright 2007 Czech Technical University.
 *
 * Michal SIMEK <monstr@seznam.cz>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/xilinx/ml401/xparameters.h"

#define	CONFIG_MICROBLAZE	1	/* MicroBlaze CPU */
#define	CONFIG_ML401		1	/* ML401 Board */

/* uart */
#define	CONFIG_SERIAL_BASE	XILINX_UART_BASEADDR
#define	CONFIG_BAUDRATE		XILINX_UART_BAUDRATE
#define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }

/* setting reset address */
//#define	CFG_RESET_ADDRESS	TEXT_BASE

/* ethernet */
#define CONFIG_EMACLITE		1
#define XPAR_EMAC_0_DEVICE_ID	XPAR_OPB_ETHERNET_0_DEVICE_ID

/* gpio */
#define	CFG_GPIO_0		1
#define	CFG_GPIO_0_ADDR		XILINX_GPIO_BASEADDR

/* interrupt controller */
#define	CFG_INTC_0		1
#define	CFG_INTC_0_ADDR		XILINX_INTC_BASEADDR
#define	CFG_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS

/* timer */
#define	CFG_TIMER_0		1
#define	CFG_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
#define	CFG_TIMER_0_IRQ		XILINX_TIMER_IRQ
#define	FREQUENCE		XILINX_CLOCK_FREQ
#define	CFG_TIMER_0_PRELOAD	( FREQUENCE/1000 )

/* FSL */
#define	CFG_FSL_2
#define	FSL_INTR_2	1

/*
 * memory layout - Example
 * TEXT_BASE = 0x1200_0000;
 * CFG_SRAM_BASE = 0x1000_0000;
 * CFG_SRAM_SIZE = 0x0400_0000;
 *
 * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
 * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
 * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
 *
 * 0x1000_0000	CFG_SDRAM_BASE
 *					FREE
 * 0x1200_0000	TEXT_BASE
 *		U-BOOT code
 * 0x1202_0000
 *					FREE
 *
 *					STACK
 * 0x13F7_F000	CFG_MALLOC_BASE
 *					MALLOC_AREA	256kB	Alloc
 * 0x11FB_F000	CFG_MONITOR_BASE
 *					MONITOR_CODE	256kB	Env
 * 0x13FF_F000	CFG_GBL_DATA_OFFSET
 * 					GLOBAL_DATA	4kB	bd, gd
 * 0x1400_0000	CFG_SDRAM_BASE + CFG_SDRAM_SIZE
 */

/* ddr sdram - main memory */
#define	CFG_SDRAM_BASE		XILINX_RAM_START
#define	CFG_SDRAM_SIZE		XILINX_RAM_SIZE
#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
#define	CFG_MEMTEST_END		(CFG_SDRAM_BASE + 0x1000)

/* global pointer */
#define	CFG_GBL_DATA_SIZE	0x1000	/* size of global data */
/* start of global data */
#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) 

/* monitor code */
#define	SIZE			0x40000
#define	CFG_MONITOR_LEN		SIZE
#define	CFG_MONITOR_BASE	(CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
#define	CFG_MONITOR_END		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define	CFG_MALLOC_LEN		SIZE
#define	CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)

/* stack */
#define	CFG_INIT_SP_OFFSET	CFG_MONITOR_BASE

/*#define	RAMENV */
#define	FLASH

#ifdef FLASH
	#define	CFG_FLASH_BASE		XILINX_FLASH_START
	#define	CFG_FLASH_SIZE		XILINX_FLASH_SIZE
	#define	CFG_FLASH_CFI		1
	#define	CFG_FLASH_CFI_DRIVER	1
	#define	CFG_FLASH_EMPTY_INFO	1	/* ?empty sector */
	#define	CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
	#define	CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
	#define	CFG_FLASH_PROTECTION		/* hardware flash protection */

	#ifdef	RAMENV
		#define	CFG_ENV_IS_NOWHERE	1
		#define	CFG_ENV_SIZE		0x1000
		#define	CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SIZE)

	#else	/* !RAMENV */
		#define	CFG_ENV_IS_IN_FLASH	1
		#define	CFG_ENV_ADDR		0x40000
		#define	CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
		#define	CFG_ENV_SIZE		0x2000
	#endif /* !RAMBOOT */
#else /* !FLASH */
	/* ENV in RAM */
	#define	CFG_NO_FLASH		1
	#define	CFG_ENV_IS_NOWHERE	1
	#define	CFG_ENV_SIZE		0x1000
	#define	CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SIZE)
	#define	CFG_FLASH_PROTECTION		/* hardware flash protection */
#endif /* !FLASH */

#ifdef	FLASH
	#ifdef	RAMENV
	#define	CONFIG_COMMANDS	(CONFIG__CMD_DFL |\
				CFG_CMD_MEMORY |\
				CFG_CMD_MISC |\
				CFG_CMD_AUTOSCRIPT |\
				CFG_CMD_IRQ |\
				CFG_CMD_ASKENV |\
				CFG_CMD_BDI |\
				CFG_CMD_RUN |\
				CFG_CMD_LOADS |\
				CFG_CMD_LOADB |\
				CFG_CMD_IMI |\
				CFG_CMD_NET |\
				CFG_CMD_CACHE |\
				CFG_CMD_FAT |\
				CFG_CMD_EXT2 |\
				CFG_CMD_JFFS2 |\
				CFG_CMD_ECHO |\
				CFG_CMD_IMLS |\
				CFG_CMD_FLASH |\
				CFG_CMD_MFSL |\
				CFG_CMD_PING \
				)
	#else	/* !RAMENV */
	#define	CONFIG_COMMANDS	(CONFIG__CMD_DFL |\
				CFG_CMD_MEMORY |\
				CFG_CMD_MISC |\
				CFG_CMD_AUTOSCRIPT |\
				CFG_CMD_IRQ |\
				CFG_CMD_ASKENV |\
				CFG_CMD_BDI |\
				CFG_CMD_RUN |\
				CFG_CMD_LOADS |\
				CFG_CMD_LOADB |\
				CFG_CMD_IMI |\
				CFG_CMD_NET |\
				CFG_CMD_CACHE |\
				CFG_CMD_IMLS |\
				CFG_CMD_FLASH |\
				CFG_CMD_PING |\
				CFG_CMD_ENV |\
				CFG_CMD_FAT |\
				CFG_CMD_EXT2 |\
				CFG_CMD_JFFS2 |\
				CFG_CMD_ECHO |\
				CFG_CMD_MFSL |\
				CFG_CMD_SAVES \
				)

	#endif

#else	/* !FLASH */
	#define	CONFIG_COMMANDS	(CONFIG__CMD_DFL |\
				CFG_CMD_MEMORY |\
				CFG_CMD_MISC |\
				CFG_CMD_AUTOSCRIPT |\
				CFG_CMD_IRQ |\
				CFG_CMD_ASKENV |\
				CFG_CMD_BDI |\
				CFG_CMD_RUN |\
				CFG_CMD_LOADS |\
				CFG_CMD_FAT |\
				CFG_CMD_EXT2 |\
				CFG_CMD_LOADB |\
				CFG_CMD_IMI |\
				CFG_CMD_NET |\
				CFG_CMD_CACHE |\
				CFG_CMD_MFSL |\
				CFG_CMD_PING \
				)
#endif	/* !FLASH */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
/* JFFS2 partitions */
#define CONFIG_JFFS2_CMDLINE	/* mtdparts command line support */
#define MTDIDS_DEFAULT		"nor0=ml401-0"

/* default mtd partition table */
#define MTDPARTS_DEFAULT	"mtdparts=ml401-0:256k(u-boot),"\
				"256k(env),3m(kernel),1m(romfs),"\
				"1m(cramfs),-(jffs2)"
#endif

/* Miscellaneous configurable options */
#define	CFG_PROMPT	"U-Boot-mONStR> "
#define	CFG_CBSIZE	512	/* size of console buffer */
#define	CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
#define	CFG_MAXARGS	15	/* max number of command args */
#define	CFG_LONGHELP
#define	CFG_LOAD_ADDR	0x12000000 /* default load address */

#define	CONFIG_BOOTDELAY	30
#define	CONFIG_BOOTARGS		"root=romfs"
#define	CONFIG_HOSTNAME		"ml401"
#define	CONFIG_BOOTCOMMAND 	"base 0;tftp 11000000 image.img;bootm"
#define	CONFIG_IPADDR		192.168.0.3
#define	CONFIG_SERVERIP 	192.168.0.5
#define	CONFIG_GATEWAYIP 	192.168.0.1
#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD

/* architecture dependent code */
#define	CFG_USR_EXCEP	/* user exception */
#define CFG_HZ	1000

/* system ace */
#define	CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
#define	SYSTEMACE_CONFIG_FPGA
#define	CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
#define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
#define	CONFIG_DOS_PARTITION

#define	CONFIG_PREBOOT		"echo U-BOOT for ML401;setenv preboot;echo"

#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" /* hardware flash protection */\
					"nor0=ml401-0\0"\
					"mtdparts=mtdparts=ml401-0:"\
					"256k(u-boot),256k(env),3m(kernel),"\
					"1m(romfs),1m(cramfs),-(jffs2)\0"

#endif	/* __CONFIG_H */
Commit	Line	Data
76316a31 MS	1	/*
	2	* (C) Copyright 2007 Czech Technical University.
	3	*
	4	* Michal SIMEK <monstr@seznam.cz>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	#include "../board/xilinx/ml401/xparameters.h"
	29
	30	#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
	31	#define CONFIG_ML401 1 /* ML401 Board */
	32
	33	/* uart */
17980495 MS	34	#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR
17980495 MS	35	#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE
76316a31 MS	36	#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
	37
	38	/* setting reset address */
32556443	39	//#define CFG_RESET_ADDRESS TEXT_BASE
76316a31	40
17980495 MS	41	/* ethernet */
17980495 MS	42	#define CONFIG_EMACLITE 1
144876a3	43	#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
17980495	44
76316a31 MS	45	/* gpio */
76316a31 MS	46	#define CFG_GPIO_0 1
17980495	47	#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
76316a31 MS	48
	49	/* interrupt controller */
	50	#define CFG_INTC_0 1
17980495 MS	51	#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
17980495 MS	52	#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
76316a31 MS	53
	54	/* timer */
	55	#define CFG_TIMER_0 1
17980495 MS	56	#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
	57	#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
	58	#define FREQUENCE XILINX_CLOCK_FREQ
76316a31 MS	59	#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
76316a31 MS	60
19bf1fba MS	61	/* FSL */
	62	#define CFG_FSL_2
	63	#define FSL_INTR_2 1
	64
76316a31 MS	65	/*
	66	* memory layout - Example
	67	* TEXT_BASE = 0x1200_0000;
	68	* CFG_SRAM_BASE = 0x1000_0000;
	69	* CFG_SRAM_SIZE = 0x0400_0000;
	70	*
	71	* CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
	72	* CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
32556443	73	* CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
76316a31 MS	74	*
	75	* 0x1000_0000 CFG_SDRAM_BASE
	76	* FREE
	77	* 0x1200_0000 TEXT_BASE
	78	* U-BOOT code
	79	* 0x1202_0000
	80	* FREE
	81	*
	82	* STACK
17980495 MS	83	* 0x13F7_F000 CFG_MALLOC_BASE
17980495 MS	84	* MALLOC_AREA 256kB Alloc
76316a31	85	* 0x11FB_F000 CFG_MONITOR_BASE
17980495	86	* MONITOR_CODE 256kB Env
76316a31	87	* 0x13FF_F000 CFG_GBL_DATA_OFFSET
17980495	88	* GLOBAL_DATA 4kB bd, gd
76316a31 MS	89	* 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
	90	*/
	91
	92	/* ddr sdram - main memory */
17980495 MS	93	#define CFG_SDRAM_BASE XILINX_RAM_START
17980495 MS	94	#define CFG_SDRAM_SIZE XILINX_RAM_SIZE
76316a31 MS	95	#define CFG_MEMTEST_START CFG_SDRAM_BASE
	96	#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000)
	97
	98	/* global pointer */
	99	#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
32556443 MS	100	/* start of global data */
32556443 MS	101	#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
76316a31 MS	102
	103	/* monitor code */
	104	#define SIZE 0x40000
	105	#define CFG_MONITOR_LEN SIZE
	106	#define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
17980495	107	#define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
76316a31	108	#define CFG_MALLOC_LEN SIZE
17980495	109	#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
76316a31 MS	110
	111	/* stack */
	112	#define CFG_INIT_SP_OFFSET CFG_MONITOR_BASE
	113
	114	/#define RAMENV /
	115	#define FLASH
	116
	117	#ifdef FLASH
17980495 MS	118	#define CFG_FLASH_BASE XILINX_FLASH_START
17980495 MS	119	#define CFG_FLASH_SIZE XILINX_FLASH_SIZE
76316a31 MS	120	#define CFG_FLASH_CFI 1
	121	#define CFG_FLASH_CFI_DRIVER 1
	122	#define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */
	123	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	124	#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
144876a3	125	#define CFG_FLASH_PROTECTION /* hardware flash protection */
76316a31 MS	126
	127	#ifdef RAMENV
	128	#define CFG_ENV_IS_NOWHERE 1
	129	#define CFG_ENV_SIZE 0x1000
	130	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
	131
	132	#else /* !RAMENV */
	133	#define CFG_ENV_IS_IN_FLASH 1
	134	#define CFG_ENV_ADDR 0x40000
	135	#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
	136	#define CFG_ENV_SIZE 0x2000
	137	#endif /* !RAMBOOT */
	138	#else /* !FLASH */
	139	/* ENV in RAM */
	140	#define CFG_NO_FLASH 1
	141	#define CFG_ENV_IS_NOWHERE 1
	142	#define CFG_ENV_SIZE 0x1000
	143	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
144876a3	144	#define CFG_FLASH_PROTECTION /* hardware flash protection */
76316a31 MS	145	#endif /* !FLASH */
	146
	147	#ifdef FLASH
	148	#ifdef RAMENV
	149	#define CONFIG_COMMANDS (CONFIG__CMD_DFL \|\
	150	CFG_CMD_MEMORY \|\
	151	CFG_CMD_MISC \|\
	152	CFG_CMD_AUTOSCRIPT \|\
	153	CFG_CMD_IRQ \|\
	154	CFG_CMD_ASKENV \|\
	155	CFG_CMD_BDI \|\
	156	CFG_CMD_RUN \|\
	157	CFG_CMD_LOADS \|\
	158	CFG_CMD_LOADB \|\
	159	CFG_CMD_IMI \|\
	160	CFG_CMD_NET \|\
	161	CFG_CMD_CACHE \|\
32556443 MS	162	CFG_CMD_FAT \|\
32556443 MS	163	CFG_CMD_EXT2 \|\
144876a3 MS	164	CFG_CMD_JFFS2 \|\
144876a3 MS	165	CFG_CMD_ECHO \|\
76316a31 MS	166	CFG_CMD_IMLS \|\
76316a31 MS	167	CFG_CMD_FLASH \|\
ffc50f9b	168	CFG_CMD_MFSL \|\
76316a31 MS	169	CFG_CMD_PING \
	170	)
	171	#else /* !RAMENV */
	172	#define CONFIG_COMMANDS (CONFIG__CMD_DFL \|\
	173	CFG_CMD_MEMORY \|\
	174	CFG_CMD_MISC \|\
	175	CFG_CMD_AUTOSCRIPT \|\
	176	CFG_CMD_IRQ \|\
	177	CFG_CMD_ASKENV \|\
	178	CFG_CMD_BDI \|\
	179	CFG_CMD_RUN \|\
	180	CFG_CMD_LOADS \|\
	181	CFG_CMD_LOADB \|\
	182	CFG_CMD_IMI \|\
	183	CFG_CMD_NET \|\
	184	CFG_CMD_CACHE \|\
	185	CFG_CMD_IMLS \|\
	186	CFG_CMD_FLASH \|\
	187	CFG_CMD_PING \|\
	188	CFG_CMD_ENV \|\
32556443 MS	189	CFG_CMD_FAT \|\
32556443 MS	190	CFG_CMD_EXT2 \|\
144876a3 MS	191	CFG_CMD_JFFS2 \|\
144876a3 MS	192	CFG_CMD_ECHO \|\
ffc50f9b	193	CFG_CMD_MFSL \|\
76316a31 MS	194	CFG_CMD_SAVES \
	195	)
	196
	197	#endif
	198
	199	#else /* !FLASH */
	200	#define CONFIG_COMMANDS (CONFIG__CMD_DFL \|\
	201	CFG_CMD_MEMORY \|\
	202	CFG_CMD_MISC \|\
	203	CFG_CMD_AUTOSCRIPT \|\
	204	CFG_CMD_IRQ \|\
	205	CFG_CMD_ASKENV \|\
	206	CFG_CMD_BDI \|\
	207	CFG_CMD_RUN \|\
	208	CFG_CMD_LOADS \|\
32556443 MS	209	CFG_CMD_FAT \|\
32556443 MS	210	CFG_CMD_EXT2 \|\
76316a31 MS	211	CFG_CMD_LOADB \|\
	212	CFG_CMD_IMI \|\
	213	CFG_CMD_NET \|\
	214	CFG_CMD_CACHE \|\
ffc50f9b	215	CFG_CMD_MFSL \|\
76316a31 MS	216	CFG_CMD_PING \
	217	)
	218	#endif /* !FLASH */
	219	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	220	#include <cmd_confdefs.h>
	221
144876a3 MS	222	#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
	223	/* JFFS2 partitions */
	224	#define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */
	225	#define MTDIDS_DEFAULT "nor0=ml401-0"
	226
	227	/* default mtd partition table */
	228	#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\
	229	"256k(env),3m(kernel),1m(romfs),"\
	230	"1m(cramfs),-(jffs2)"
	231	#endif
	232
76316a31 MS	233	/* Miscellaneous configurable options */
	234	#define CFG_PROMPT "U-Boot-mONStR> "
	235	#define CFG_CBSIZE 512 /* size of console buffer */
	236	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
	237	#define CFG_MAXARGS 15 /* max number of command args */
	238	#define CFG_LONGHELP
	239	#define CFG_LOAD_ADDR 0x12000000 /* default load address */
	240
144876a3	241	#define CONFIG_BOOTDELAY 30
76316a31 MS	242	#define CONFIG_BOOTARGS "root=romfs"
	243	#define CONFIG_HOSTNAME "ml401"
	244	#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
	245	#define CONFIG_IPADDR 192.168.0.3
	246	#define CONFIG_SERVERIP 192.168.0.5
	247	#define CONFIG_GATEWAYIP 192.168.0.1
	248	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
	249
	250	/* architecture dependent code */
	251	#define CFG_USR_EXCEP /* user exception */
	252	#define CFG_HZ 1000
	253
	254	/* system ace */
32556443 MS	255	#define CONFIG_SYSTEMACE
	256	/* #define DEBUG_SYSTEMACE */
	257	#define SYSTEMACE_CONFIG_FPGA
	258	#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
	259	#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
	260	#define CONFIG_DOS_PARTITION
	261
144876a3 MS	262	#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo"
	263
	264	#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
	265	"nor0=ml401-0\0"\
	266	"mtdparts=mtdparts=ml401-0:"\
	267	"256k(u-boot),256k(env),3m(kernel),"\
	268	"1m(romfs),1m(cramfs),-(jffs2)\0"
	269
76316a31	270	#endif /* __CONFIG_H */