[people/ms/u-boot.git] / include / configs / mucmc52.h

/*
 * (C) Copyright 2008
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define	CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
#define	CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
#define	CONFIG_MUCMC52		1	/* MUCMC52 board			*/

#define	CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/

#define	BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define	BOOTFLAG_WARM		0x02	/* Software reboot			*/

#define	CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define	CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

#define	CONFIG_BOARD_EARLY_INIT_R

#define	CONFIG_LAST_STAGE_INIT

#define	CONFIG_HIGH_BATS	1	/* High BATs supported			*/
/*
 * Serial console configuration
 */
#define	CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
#define	CONFIG_BAUDRATE		38400	/* ... at 38400 bps	*/
#define	CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/* Partitions */
#define	CONFIG_DOS_PARTITION

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define	CONFIG_CMD_DATE
#define	CONFIG_CMD_DISPLAY
#define	CONFIG_CMD_DHCP
#define	CONFIG_CMD_EEPROM
#define	CONFIG_CMD_FAT
#define	CONFIG_CMD_I2C
#define	CONFIG_CMD_DTT
#define	CONFIG_CMD_IDE
#define	CONFIG_CMD_MII
#define	CONFIG_CMD_NFS
#define	CONFIG_CMD_PCI
#define	CONFIG_CMD_PING
#define	CONFIG_CMD_SNTP

#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */

#if (TEXT_BASE == 0xFFF00000) /* Boot low */
#   define	CFG_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define	CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define	CONFIG_PREBOOT	"echo;" \
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	""

#define	CONFIG_BOOTCOMMAND	"run net_nfs"

#define	CONFIG_MISC_INIT_R	1

/*
 * IPB Bus clocking configuration.
 */
#undef	CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * I2C configuration
 */
#define	CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define	CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define	CFG_I2C_SPEED		100000 /* 100 kHz */
#define	CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define	CFG_I2C_EEPROM_ADDR		0x58
#define	CFG_I2C_EEPROM_ADDR_LEN		1
#define	CFG_EEPROM_PAGE_WRITE_BITS	4
#define	CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
/* for LM81 */
#define	CFG_EEPROM_PAGE_WRITE_ENABLE

/*
 * RTC configuration
 */
#define	CONFIG_RTC_PCF8563
#define	CFG_I2C_RTC_ADDR		0x51

/* I2C SYSMON (LM75) */
#define	CONFIG_DTT_LM81			1	/* ON Semi's LM75		*/
#define	CONFIG_DTT_SENSORS		{0}	/* Sensor addresses		*/
#define	CFG_DTT_MAX_TEMP		70
#define	CFG_DTT_LOW_TEMP		-30
#define	CFG_DTT_HYSTERESIS		3

/*
 * Flash configuration
 */
#define	CFG_FLASH_BASE		0xFF800000

#define	CFG_FLASH_SIZE		0x00800000 /* 8 MByte */
#define	CFG_MAX_FLASH_SECT	67	/* max num of sects on one chip */

#define	CFG_ENV_ADDR		(TEXT_BASE+0x40000) /* second sector */
#define	CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define	CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define	CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

#define	CONFIG_FLASH_CFI_DRIVER
#define	CFG_FLASH_CFI
#define	CFG_FLASH_EMPTY_INFO
#define	CFG_FLASH_CFI_AMD_RESET

/*
 * Environment settings
 */
#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CFG_ENV_SIZE		0x4000
#define	CFG_ENV_SECT_SIZE	0x20000
#define	CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)

/*
 * Memory map
 */
#define	CFG_MBAR		0xF0000000
#define	CFG_SDRAM_BASE		0x00000000
#define	CFG_DEFAULT_MBAR	0x80000000
#define	CFG_DISPLAY_BASE	0x80600000
#define	CFG_STATUS1_BASE	0x80600200
#define	CFG_STATUS2_BASE	0x80600300
#define	CFG_PMI_UNI_BASE	0x80800000
#define	CFG_PMI_BROAD_BASE	0x80810000

/* Settings for XLB = 132 MHz */
#define	SDRAM_DDR	 1
#define	SDRAM_MODE      0x018D0000
#define	SDRAM_EMODE     0x40090000
#define	SDRAM_CONTROL   0x714f0f00
#define	SDRAM_CONFIG1   0x73722930
#define	SDRAM_CONFIG2   0x47770000
#define	SDRAM_TAPDELAY  0x10000000

/* Use ON-Chip SRAM until RAM will be available */
#define	CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define	CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
#else
#define	CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
#endif

#define	CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define	CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define	CFG_MONITOR_BASE	TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define	CFG_RAMBOOT	1
#endif

#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define	CFG_MALLOC_LEN		(512 << 10)	/* Reserve 128 kB for malloc()	*/
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define	CONFIG_MPC5xxx_FEC	1
#define	CONFIG_PHY_ADDR		0x00
#define	CONFIG_MII		1		/* MII PHY management		*/

/*
 * GPIO configuration
 */
#define	CFG_GPS_PORT_CONFIG	0x8D550644

/*use  Hardware WDT */
#define CONFIG_HW_WATCHDOG

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory	    */
#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define	CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS		16	/* max number of command args	*/
#define	CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

/* Enable an alternate, more extensive memory test */
#define	CFG_ALT_MEMTEST

#define	CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define	CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define	CFG_LOAD_ADDR		0x100000	/* default load address */

#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

/*
 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
 * which is normally part of the default commands (CFV_CMD_DFL)
 */
#define	CONFIG_LOOPW

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define	CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define	CFG_HID0_FINAL		HID0_ICE
#else
#define	CFG_HID0_INIT		0
#define	CFG_HID0_FINAL		0
#endif

#define	CFG_BOOTCS_START	CFG_FLASH_BASE
#define	CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#define	CFG_BOOTCS_CFG		0x0004FB00
#define	CFG_CS0_START		CFG_FLASH_BASE
#define	CFG_CS0_SIZE		CFG_FLASH_SIZE

/* 8Mbit SRAM @0x80100000 */
#define	CFG_CS1_START		0x80100000
#define	CFG_CS1_SIZE		0x00100000
#define	CFG_CS1_CFG		0x00019B00

/* FRAM 32Kbyte @0x80700000 */
#define	CFG_CS2_START		0x80700000
#define	CFG_CS2_SIZE		0x00008000
#define	CFG_CS2_CFG		0x00019800

/* Display H1, Status Inputs, EPLD @0x80600000 */
#define	CFG_CS3_START		0x80600000
#define	CFG_CS3_SIZE		0x00100000
#define	CFG_CS3_CFG		0x00019800

/* PMI Unicast 32Kbyte @0x80800000 */
#define	CFG_CS6_START		CFG_PMI_UNI_BASE
#define	CFG_CS6_SIZE		0x00008000
#define	CFG_CS6_CFG		0xFFFFF930

/* PMI Broadcast 32Kbyte @0x80810000 */
#define	CFG_CS7_START		CFG_PMI_BROAD_BASE
#define	CFG_CS7_SIZE		0x00008000
#define	CFG_CS7_CFG		0xFF00F930

#define	CFG_CS_BURST		0x00000000
#define	CFG_CS_DEADCYCLE	0x33333333

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define	CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define	CFG_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus	*/

#define	CONFIG_IDE_PREINIT	1

#define	CFG_ATA_IDE0_OFFSET	0x0000

#define	CFG_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define	CFG_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define	CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define	CFG_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers           */
#define	CFG_ATA_STRIDE          4

#define	CONFIG_ATAPI            1

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define	CONFIG_PCI		1
#define	CONFIG_PCI_PNP		1
#define	CONFIG_PCI_SCAN_SHOW	1
#define	CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define	CONFIG_PCI_MEM_BUS	0x40000000
#define	CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define	CONFIG_PCI_MEM_SIZE	0x10000000

#define	CONFIG_PCI_IO_BUS	0x50000000
#define	CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define	CONFIG_PCI_IO_SIZE	0x01000000

#define	CFG_ISA_IO		CONFIG_PCI_IO_BUS

/*---------------------------------------------------------------------*/
/* Display addresses						       */
/*---------------------------------------------------------------------*/

#define	CFG_DISP_CHR_RAM	(CFG_DISPLAY_BASE + 0x38)
#define	CFG_DISP_CWORD		(CFG_DISPLAY_BASE + 0x30)

#endif /* __CONFIG_H */
Commit	Line	Data
258c37b1 HS	1	/*
	2	* (C) Copyright 2008
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
	5	* (C) Copyright 2003-2005
	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*
	31	* High Level Configuration Options
	32	* (easy to change)
	33	*/
	34
	35	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	36	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	37	#define CONFIG_MUCMC52 1 /* MUCMC52 board */
	38
	39	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	40
	41	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	42	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	43
	44	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	45	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	46	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	47	#endif
	48
	49	#define CONFIG_BOARD_EARLY_INIT_R
	50
	51	#define CONFIG_LAST_STAGE_INIT
	52
	53	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
	54	/*
	55	* Serial console configuration
	56	*/
	57	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	58	#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
	59	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	60
	61	/* Partitions */
	62	#define CONFIG_DOS_PARTITION
	63
	64	/*
65	* Command line configuration.
66	*/
67	#include <config_cmd_default.h>
68
69	#define CONFIG_CMD_DATE
70	#define CONFIG_CMD_DISPLAY
71	#define CONFIG_CMD_DHCP
72	#define CONFIG_CMD_EEPROM
73	#define CONFIG_CMD_FAT
74	#define CONFIG_CMD_I2C
75	#define CONFIG_CMD_DTT
76	#define CONFIG_CMD_IDE
77	#define CONFIG_CMD_MII
78	#define CONFIG_CMD_NFS
79	#define CONFIG_CMD_PCI
80	#define CONFIG_CMD_PING
81	#define CONFIG_CMD_SNTP
82
83	#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
84
85	#if (TEXT_BASE == 0xFFF00000) /* Boot low */
86	# define CFG_LOWBOOT 1
87	#endif
88
89	/*
90	* Autobooting
91	*/
92	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
93
94	#define CONFIG_PREBOOT "echo;" \
95	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
96	"echo"
97
98	#undef CONFIG_BOOTARGS
99
100	#define CONFIG_EXTRA_ENV_SETTINGS \
101	"netdev=eth0\0" \
102	"nfsargs=setenv bootargs root=/dev/nfs rw " \
103	"nfsroot=${serverip}:${rootpath}\0" \
104	"ramargs=setenv bootargs root=/dev/ram rw\0" \
105	"addip=setenv bootargs ${bootargs} " \
106	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
107	":${hostname}:${netdev}:off panic=1\0" \
108	"flash_nfs=run nfsargs addip;" \
109	"bootm ${kernel_addr}\0" \
110	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
111	"rootpath=/opt/eldk/ppc_82xx\0" \
112	""
113
114	#define CONFIG_BOOTCOMMAND "run net_nfs"
115
116	#define CONFIG_MISC_INIT_R 1
117
118	/*
119	* IPB Bus clocking configuration.
120	*/
121	#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
122
123	/*
124	* I2C configuration
125	*/
126	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
127	#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
128
129	#define CFG_I2C_SPEED 100000 /* 100 kHz */
130	#define CFG_I2C_SLAVE 0x7F
131
132	/*
133	* EEPROM configuration
134	*/
135	#define CFG_I2C_EEPROM_ADDR 0x58
136	#define CFG_I2C_EEPROM_ADDR_LEN 1
137	#define CFG_EEPROM_PAGE_WRITE_BITS 4
138	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
139	/* for LM81 */
140	#define CFG_EEPROM_PAGE_WRITE_ENABLE
141
142	/*
143	* RTC configuration
144	*/
145	#define CONFIG_RTC_PCF8563
146	#define CFG_I2C_RTC_ADDR 0x51
147
148	/* I2C SYSMON (LM75) */
149	#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */
150	#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
151	#define CFG_DTT_MAX_TEMP 70
152	#define CFG_DTT_LOW_TEMP -30
153	#define CFG_DTT_HYSTERESIS 3
154
155	/*
156	* Flash configuration
157	*/
158	#define CFG_FLASH_BASE 0xFF800000
159
160	#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
161	#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
162
163	#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
164	#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
165	(= chip selects) */
166	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
167	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
168
169	#define CONFIG_FLASH_CFI_DRIVER
170	#define CFG_FLASH_CFI
171	#define CFG_FLASH_EMPTY_INFO
172	#define CFG_FLASH_CFI_AMD_RESET
173
174	/*
175	* Environment settings
176	*/
5a1aceb0	177	#define CONFIG_ENV_IS_IN_FLASH 1
258c37b1 HS	178	#define CFG_ENV_SIZE 0x4000
	179	#define CFG_ENV_SECT_SIZE 0x20000
	180	#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
	181	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	182
	183	/*
	184	* Memory map
	185	*/
	186	#define CFG_MBAR 0xF0000000
	187	#define CFG_SDRAM_BASE 0x00000000
	188	#define CFG_DEFAULT_MBAR 0x80000000
	189	#define CFG_DISPLAY_BASE 0x80600000
	190	#define CFG_STATUS1_BASE 0x80600200
	191	#define CFG_STATUS2_BASE 0x80600300
	192	#define CFG_PMI_UNI_BASE 0x80800000
	193	#define CFG_PMI_BROAD_BASE 0x80810000
	194
	195	/* Settings for XLB = 132 MHz */
	196	#define SDRAM_DDR 1
	197	#define SDRAM_MODE 0x018D0000
	198	#define SDRAM_EMODE 0x40090000
	199	#define SDRAM_CONTROL 0x714f0f00
	200	#define SDRAM_CONFIG1 0x73722930
	201	#define SDRAM_CONFIG2 0x47770000
	202	#define SDRAM_TAPDELAY 0x10000000
	203
	204	/* Use ON-Chip SRAM until RAM will be available */
	205	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	206	#ifdef CONFIG_POST
	207	/* preserve space for the post_word at end of on-chip SRAM */
	208	#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
	209	#else
	210	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
	211	#endif
	212
	213	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	214	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	215	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	216
	217	#define CFG_MONITOR_BASE TEXT_BASE
	218	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	219	# define CFG_RAMBOOT 1
	220	#endif
	221
	222	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	223	#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
	224	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	225
	226	/*
	227	* Ethernet configuration
	228	*/
	229	#define CONFIG_MPC5xxx_FEC 1
	230	#define CONFIG_PHY_ADDR 0x00
	231	#define CONFIG_MII 1 /* MII PHY management */
	232
	233	/*
	234	* GPIO configuration
	235	*/
	236	#define CFG_GPS_PORT_CONFIG 0x8D550644
	237
	238	/use Hardware WDT /
	239	#define CONFIG_HW_WATCHDOG
	240
	241	/*
242	* Miscellaneous configurable options
243	*/
244	#define CFG_LONGHELP /* undef to save memory */
245	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
246	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
247	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
248	#else
249	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
250	#endif
251	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
252	#define CFG_MAXARGS 16 /* max number of command args */
253	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
254
255	/* Enable an alternate, more extensive memory test */
256	#define CFG_ALT_MEMTEST
257
258	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
259	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
260
261	#define CFG_LOAD_ADDR 0x100000 /* default load address */
262
263	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
264
265	/*
266	* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
267	* which is normally part of the default commands (CFV_CMD_DFL)
268	*/
269	#define CONFIG_LOOPW
270
271	/*
272	* Various low-level settings
273	*/
274	#if defined(CONFIG_MPC5200)
275	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
276	#define CFG_HID0_FINAL HID0_ICE
277	#else
278	#define CFG_HID0_INIT 0
279	#define CFG_HID0_FINAL 0
280	#endif
281
282	#define CFG_BOOTCS_START CFG_FLASH_BASE
283	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
284	#define CFG_BOOTCS_CFG 0x0004FB00
285	#define CFG_CS0_START CFG_FLASH_BASE
286	#define CFG_CS0_SIZE CFG_FLASH_SIZE
287
288	/* 8Mbit SRAM @0x80100000 */
289	#define CFG_CS1_START 0x80100000
290	#define CFG_CS1_SIZE 0x00100000
291	#define CFG_CS1_CFG 0x00019B00
292
293	/* FRAM 32Kbyte @0x80700000 */
294	#define CFG_CS2_START 0x80700000
295	#define CFG_CS2_SIZE 0x00008000
296	#define CFG_CS2_CFG 0x00019800
297
298	/* Display H1, Status Inputs, EPLD @0x80600000 */
299	#define CFG_CS3_START 0x80600000
300	#define CFG_CS3_SIZE 0x00100000
301	#define CFG_CS3_CFG 0x00019800
302
303	/* PMI Unicast 32Kbyte @0x80800000 */
304	#define CFG_CS6_START CFG_PMI_UNI_BASE
305	#define CFG_CS6_SIZE 0x00008000
306	#define CFG_CS6_CFG 0xFFFFF930
307
308	/* PMI Broadcast 32Kbyte @0x80810000 */
309	#define CFG_CS7_START CFG_PMI_BROAD_BASE
310	#define CFG_CS7_SIZE 0x00008000
311	#define CFG_CS7_CFG 0xFF00F930
312
313	#define CFG_CS_BURST 0x00000000
314	#define CFG_CS_DEADCYCLE 0x33333333
315
316	/*-----------------------------------------------------------------------
317	* IDE/ATA stuff Supports IDE harddisk
318	*-----------------------------------------------------------------------
319	*/
320
321	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
322
323	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
324	#undef CONFIG_IDE_LED /* LED for ide not supported */
325
326	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
327	#define CFG_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
328
329	#define CONFIG_IDE_PREINIT 1
330
331	#define CFG_ATA_IDE0_OFFSET 0x0000
332
333	#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
334
335	/* Offset for data I/O */
336	#define CFG_ATA_DATA_OFFSET (0x0060)
337
338	/* Offset for normal register accesses */
339	#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
340
341	/* Offset for alternate registers */
342	#define CFG_ATA_ALT_OFFSET (0x005C)
343
344	/* Interval between registers */
345	#define CFG_ATA_STRIDE 4
346
347	#define CONFIG_ATAPI 1
348
349	/*
350	* PCI Mapping:
351	* 0x40000000 - 0x4fffffff - PCI Memory
352	* 0x50000000 - 0x50ffffff - PCI IO Space
353	*/
354	#define CONFIG_PCI 1
355	#define CONFIG_PCI_PNP 1
356	#define CONFIG_PCI_SCAN_SHOW 1
357	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
358
359	#define CONFIG_PCI_MEM_BUS 0x40000000
360	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
361	#define CONFIG_PCI_MEM_SIZE 0x10000000
362
363	#define CONFIG_PCI_IO_BUS 0x50000000
364	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
365	#define CONFIG_PCI_IO_SIZE 0x01000000
366
367	#define CFG_ISA_IO CONFIG_PCI_IO_BUS
368
369	/---------------------------------------------------------------------/
370	/* Display addresses */
371	/---------------------------------------------------------------------/
372
373	#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38)
374	#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30)
375
376	#endif /* __CONFIG_H */