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1 | /* |
2 | * (C) Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation; either version 2 of | |
7 | * the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #ifndef __CONFIG_H | |
16 | #define __CONFIG_H | |
17 | ||
0208a53f FE |
18 | #include <asm/arch/imx-regs.h> |
19 | ||
419adbfb FE |
20 | /* High Level Configuration Options */ |
21 | ||
d6d94e73 | 22 | #define CONFIG_MX25 |
419adbfb FE |
23 | #define CONFIG_SYS_HZ 1000 |
24 | #define CONFIG_SYS_TEXT_BASE 0x81200000 | |
af2a4093 | 25 | #define CONFIG_MXC_GPIO |
419adbfb FE |
26 | |
27 | #define CONFIG_DISPLAY_CPUINFO | |
28 | #define CONFIG_DISPLAY_BOARDINFO | |
29 | ||
30 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
31 | #define CONFIG_SETUP_MEMORY_TAGS | |
32 | #define CONFIG_INITRD_TAG | |
33 | ||
f39c008e FE |
34 | #define CONFIG_MACH_TYPE MACH_TYPE_MX25_3DS |
35 | ||
419adbfb FE |
36 | /* Size of malloc() pool */ |
37 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) | |
38 | ||
39 | /* Physical Memory Map */ | |
40 | ||
41 | #define CONFIG_NR_DRAM_BANKS 1 | |
42 | #define PHYS_SDRAM_1 0x80000000 | |
43 | #define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) | |
44 | ||
45 | #define CONFIG_BOARD_EARLY_INIT_F | |
e00c89df | 46 | #define CONFIG_BOARD_LATE_INIT |
419adbfb FE |
47 | |
48 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
0208a53f FE |
49 | #define CONFIG_SYS_INIT_RAM_ADDR IMX_RAM_BASE |
50 | #define CONFIG_SYS_INIT_RAM_SIZE IMX_RAM_SIZE | |
51 | ||
52 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
53 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
54 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
55 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
419adbfb FE |
56 | |
57 | /* Memory Test */ | |
58 | #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE/2) | |
59 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) | |
60 | ||
419adbfb FE |
61 | /* Serial Info */ |
62 | #define CONFIG_MXC_UART | |
40f6fffe | 63 | #define CONFIG_MXC_UART_BASE UART1_BASE |
419adbfb FE |
64 | #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ |
65 | #define CONFIG_BAUDRATE 115200 /* Default baud rate */ | |
419adbfb FE |
66 | |
67 | /* No NOR flash present */ | |
68 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) | |
69 | #define CONFIG_ENV_SIZE (8 * 1024) | |
419adbfb FE |
70 | |
71 | #define CONFIG_SYS_NO_FLASH | |
af2a4093 FE |
72 | #define CONFIG_ENV_IS_IN_MMC |
73 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
419adbfb FE |
74 | |
75 | /* U-Boot general configuration */ | |
76 | #define CONFIG_SYS_PROMPT "MX25PDK U-Boot > " | |
77 | #define CONFIG_AUTO_COMPLETE | |
78 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
79 | /* Print buffer sz */ | |
80 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
81 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
82 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
83 | /* Boot Argument Buffer Size */ | |
84 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
85 | #define CONFIG_CMDLINE_EDITING | |
86 | #define CONFIG_SYS_LONGHELP | |
87 | ||
88 | /* U-Boot commands */ | |
89 | #include <config_cmd_default.h> | |
b874df74 | 90 | #define CONFIG_OF_LIBFDT |
2dc0fe9e | 91 | #define CONFIG_CMD_BOOTZ |
419adbfb | 92 | #define CONFIG_CMD_CACHE |
af2a4093 FE |
93 | #define CONFIG_CMD_MMC |
94 | #define CONFIG_CMD_EXT2 | |
95 | #define CONFIG_CMD_FAT | |
419adbfb FE |
96 | |
97 | /* Ethernet */ | |
98 | #define CONFIG_FEC_MXC | |
99 | #define CONFIG_FEC_MXC_PHYADDR 0x1f | |
100 | #define CONFIG_MII | |
101 | #define CONFIG_CMD_NET | |
419adbfb FE |
102 | #define CONFIG_ENV_OVERWRITE |
103 | ||
af2a4093 FE |
104 | /* ESDHC driver */ |
105 | #define CONFIG_MMC | |
106 | #define CONFIG_GENERIC_MMC | |
107 | #define CONFIG_FSL_ESDHC | |
108 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
109 | #define CONFIG_SYS_FSL_ESDHC_NUM 1 | |
110 | ||
e00c89df | 111 | /* PMIC Configs */ |
cabe240b FE |
112 | #define CONFIG_POWER |
113 | #define CONFIG_POWER_I2C | |
114 | #define CONFIG_POWER_FSL | |
e00c89df FE |
115 | #define CONFIG_PMIC_FSL_MC34704 |
116 | #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54 | |
117 | ||
af2a4093 FE |
118 | #define CONFIG_DOS_PARTITION |
119 | ||
e00c89df FE |
120 | /* I2C Configs */ |
121 | #define CONFIG_CMD_I2C | |
122 | #define CONFIG_HARD_I2C | |
123 | #define CONFIG_I2C_MXC | |
124 | #define CONFIG_SYS_I2C_BASE IMX_I2C_BASE | |
125 | #define CONFIG_SYS_I2C_SPEED 100000 | |
126 | ||
127 | /* Ethernet Configs */ | |
128 | ||
129 | #define CONFIG_CMD_PING | |
130 | #define CONFIG_CMD_DHCP | |
131 | #define CONFIG_CMD_MII | |
132 | #define CONFIG_CMD_NET | |
133 | ||
d941e6b6 | 134 | #define CONFIG_BOOTDELAY 1 |
419adbfb FE |
135 | |
136 | #define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */ | |
137 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
138 | ||
139 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
140 | "script=boot.scr\0" \ | |
141 | "uimage=uImage\0" \ | |
142 | "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ | |
143 | "root=/dev/nfs " \ | |
144 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
145 | "bootcmd=run netargs; dhcp ${uimage}; bootm\0" \ | |
146 | ||
147 | #endif /* __CONFIG_H */ |