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938080dc JL |
1 | /* |
2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. | |
3 | * Jason Liu <r64343@freescale.com> | |
4 | * | |
5 | * Configuration settings for Freescale MX53 low cost board. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #ifndef __CONFIG_H | |
24 | #define __CONFIG_H | |
25 | ||
26 | #define CONFIG_MX53 | |
27 | ||
28 | #define CONFIG_SYS_MX5_HCLK 24000000 | |
29 | #define CONFIG_SYS_MX5_CLK32 32768 | |
938080dc JL |
30 | #define CONFIG_DISPLAY_BOARDINFO |
31 | ||
9df82896 FE |
32 | #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO |
33 | ||
938080dc JL |
34 | #include <asm/arch/imx-regs.h> |
35 | ||
36 | #define CONFIG_CMDLINE_TAG | |
938080dc JL |
37 | #define CONFIG_SETUP_MEMORY_TAGS |
38 | #define CONFIG_INITRD_TAG | |
39 | ||
40 | /* Size of malloc() pool */ | |
41 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) | |
42 | ||
43 | #define CONFIG_BOARD_EARLY_INIT_F | |
e7e33722 | 44 | #define CONFIG_BOARD_LATE_INIT |
938080dc | 45 | #define CONFIG_MXC_GPIO |
54cd1dee | 46 | #define CONFIG_REVISION_TAG |
938080dc JL |
47 | |
48 | #define CONFIG_MXC_UART | |
40f6fffe | 49 | #define CONFIG_MXC_UART_BASE UART1_BASE |
938080dc JL |
50 | |
51 | /* MMC Configs */ | |
52 | #define CONFIG_FSL_ESDHC | |
53 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
54 | #define CONFIG_SYS_FSL_ESDHC_NUM 2 | |
55 | ||
56 | #define CONFIG_MMC | |
57 | #define CONFIG_CMD_MMC | |
58 | #define CONFIG_GENERIC_MMC | |
59 | #define CONFIG_CMD_FAT | |
f92e4e6c | 60 | #define CONFIG_CMD_EXT2 |
938080dc JL |
61 | #define CONFIG_DOS_PARTITION |
62 | ||
63 | /* Eth Configs */ | |
64 | #define CONFIG_HAS_ETH1 | |
938080dc JL |
65 | #define CONFIG_MII |
66 | #define CONFIG_DISCOVER_PHY | |
67 | ||
68 | #define CONFIG_FEC_MXC | |
69 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
70 | #define CONFIG_FEC_MXC_PHYADDR 0x1F | |
71 | ||
72 | #define CONFIG_CMD_PING | |
73 | #define CONFIG_CMD_DHCP | |
74 | #define CONFIG_CMD_MII | |
75 | #define CONFIG_CMD_NET | |
76 | ||
45cf6ada WG |
77 | /* USB Configs */ |
78 | #define CONFIG_CMD_USB | |
79 | #define CONFIG_CMD_FAT | |
80 | #define CONFIG_USB_EHCI | |
81 | #define CONFIG_USB_EHCI_MX5 | |
82 | #define CONFIG_USB_STORAGE | |
83 | #define CONFIG_USB_HOST_ETHER | |
84 | #define CONFIG_USB_ETHER_ASIX | |
85 | #define CONFIG_USB_ETHER_SMSC95XX | |
86 | #define CONFIG_MXC_USB_PORT 1 | |
87 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
88 | #define CONFIG_MXC_USB_FLAGS 0 | |
89 | ||
e7e33722 FE |
90 | /* I2C Configs */ |
91 | #define CONFIG_HARD_I2C | |
92 | #define CONFIG_I2C_MXC | |
93 | #define CONFIG_SYS_I2C_MX53_PORT1 | |
94 | #define CONFIG_SYS_I2C_SPEED 100000 | |
95 | #define CONFIG_SYS_I2C_SLAVE 0xfe | |
96 | ||
97 | /* PMIC Controller */ | |
98 | #define CONFIG_PMIC | |
99 | #define CONFIG_PMIC_I2C | |
100 | #define CONFIG_DIALOG_PMIC | |
5b547f3c | 101 | #define CONFIG_PMIC_FSL |
e7e33722 | 102 | #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 |
5b547f3c | 103 | #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 |
e7e33722 | 104 | |
938080dc JL |
105 | /* allow to overwrite serial and ethaddr */ |
106 | #define CONFIG_ENV_OVERWRITE | |
107 | #define CONFIG_CONS_INDEX 1 | |
108 | #define CONFIG_BAUDRATE 115200 | |
109 | #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} | |
110 | ||
111 | /* Command definition */ | |
112 | #include <config_cmd_default.h> | |
113 | ||
114 | #undef CONFIG_CMD_IMLS | |
115 | ||
116 | #define CONFIG_BOOTDELAY 3 | |
117 | ||
28b119e9 | 118 | #define CONFIG_ETHPRIME "FEC0" |
938080dc JL |
119 | |
120 | #define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ | |
121 | #define CONFIG_SYS_TEXT_BASE 0x77800000 | |
122 | ||
123 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
124 | "script=boot.scr\0" \ | |
125 | "uimage=uImage\0" \ | |
126 | "mmcdev=0\0" \ | |
127 | "mmcpart=2\0" \ | |
128 | "mmcroot=/dev/mmcblk0p3 rw\0" \ | |
129 | "mmcrootfstype=ext3 rootwait\0" \ | |
130 | "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ | |
131 | "root=${mmcroot} " \ | |
132 | "rootfstype=${mmcrootfstype}\0" \ | |
133 | "loadbootscript=" \ | |
134 | "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | |
135 | "bootscript=echo Running bootscript from mmc ...; " \ | |
136 | "source\0" \ | |
137 | "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ | |
138 | "mmcboot=echo Booting from mmc ...; " \ | |
139 | "run mmcargs; " \ | |
140 | "bootm\0" \ | |
141 | "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ | |
142 | "root=/dev/nfs " \ | |
143 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
144 | "netboot=echo Booting from net ...; " \ | |
145 | "run netargs; " \ | |
146 | "dhcp ${uimage}; bootm\0" \ | |
147 | ||
148 | #define CONFIG_BOOTCOMMAND \ | |
149 | "if mmc rescan ${mmcdev}; then " \ | |
150 | "if run loadbootscript; then " \ | |
151 | "run bootscript; " \ | |
152 | "else " \ | |
153 | "if run loaduimage; then " \ | |
154 | "run mmcboot; " \ | |
155 | "else run netboot; " \ | |
156 | "fi; " \ | |
157 | "fi; " \ | |
158 | "else run netboot; fi" | |
159 | ||
160 | #define CONFIG_ARP_TIMEOUT 200UL | |
161 | ||
162 | /* Miscellaneous configurable options */ | |
163 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
164 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
165 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
166 | #define CONFIG_SYS_PROMPT "MX53LOCO U-Boot > " | |
167 | #define CONFIG_AUTO_COMPLETE | |
168 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
169 | ||
170 | /* Print Buffer Size */ | |
171 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
172 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
173 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
174 | ||
175 | #define CONFIG_SYS_MEMTEST_START 0x70000000 | |
176 | #define CONFIG_SYS_MEMTEST_END 0x70010000 | |
177 | ||
178 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
179 | ||
180 | #define CONFIG_SYS_HZ 1000 | |
181 | #define CONFIG_CMDLINE_EDITING | |
182 | ||
183 | /* Stack sizes */ | |
184 | #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ | |
185 | ||
186 | /* Physical Memory Map */ | |
187 | #define CONFIG_NR_DRAM_BANKS 2 | |
188 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR | |
189 | #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) | |
190 | #define PHYS_SDRAM_2 CSD1_BASE_ADDR | |
191 | #define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) | |
192 | #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) | |
193 | ||
194 | #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) | |
195 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) | |
196 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) | |
197 | ||
198 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
199 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
200 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
201 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
202 | ||
203 | /* FLASH and environment organization */ | |
204 | #define CONFIG_SYS_NO_FLASH | |
205 | ||
206 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) | |
207 | #define CONFIG_ENV_SIZE (8 * 1024) | |
208 | #define CONFIG_ENV_IS_IN_MMC | |
209 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
210 | ||
211 | #define CONFIG_OF_LIBFDT | |
938080dc | 212 | |
f92e4e6c SB |
213 | #define CONFIG_CMD_SATA |
214 | #ifdef CONFIG_CMD_SATA | |
215 | #define CONFIG_DWC_AHSATA | |
216 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 | |
217 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
218 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR | |
219 | #define CONFIG_LBA48 | |
220 | #define CONFIG_LIBATA | |
221 | #endif | |
222 | ||
938080dc | 223 | #endif /* __CONFIG_H */ |