[people/ms/u-boot.git] / include / configs / omap1610h2.h

/*
 * (C) Copyright 2004
 * Texas Instruments.
 * Kshitij Gupta <kshitij@ti.com>
 * Configuration settings for the TI OMAP 1610 H2 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP1610		1	/* which is in a 1610 */
#define CONFIG_H2_OMAP1610	1	/* on an H2 Board */
#define CONFIG_MACH_OMAP_H2		/* Select board mach-type */

/* input clock of PLL */
/* the OMAP1610 H2 has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ	12000000

#undef CONFIG_USE_IRQ	/* we don't need IRQ/FIQ stuff */

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

/*
 * Hardware drivers
 */
#define CONFIG_DRIVER_LAN91C96
#define CONFIG_LAN91C96_BASE 0x04000300
#define CONFIG_LAN91C96_EXT_PHY

/*
 * NS16550 Configuration
 */
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	(-4)
#define CFG_NS16550_CLK	(48000000)		/* can be 12M/32Khz or 48Mhz */
#define CFG_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart */

/*
 * select serial console configuration
 */
#define CONFIG_SERIAL1	1	/* we use SERIAL 1 on OMAP1610 H2 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE	115200
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH


#include <configs/omap1510.h>

#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTARGS	"console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=dhcp"
#define CONFIG_BOOTCOMMAND      "bootp;tftp;bootm"
#define CFG_AUTOLOAD            "n"             /* No autoload */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	1	/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP	/* undef to save memory */
#define CFG_PROMPT	"OMAP1610 H2 # "	/* Monitor Command Prompt */
#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */

#define CFG_MEMTEST_START	0x10000000	/* memtest works on */
#define CFG_MEMTEST_END	0x12000000	/* 32 MB in DRAM */

#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */

#define CFG_LOAD_ADDR	0x10000000	/* default load address */

/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
 * DPLL1. This time is further subdivided by a local divisor.
 */
#define CFG_TIMERBASE	0xFFFEC500	/* use timer 1 */
#define CFG_PVT	7	/* 2^(pvt+1), divide by 256 */
#define CFG_HZ	((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */

#define PHYS_FLASH_1_BM1	0x00000000	/* Flash Bank #1 if booting from flash */
#define PHYS_FLASH_1_BM0	0x0C000000	/* Flash Bank #1 if booting from RAM */

#ifdef CONFIG_CS_AUTOBOOT			/* Determine CS assignment in runtime */

#ifndef __ASSEMBLY__
extern unsigned long omap_flash_base;		/* set in flash__init */
#endif
#define CFG_FLASH_BASE		omap_flash_base

#elif defined(CONFIG_CS0_BOOT)

#define CFG_FLASH_BASE		PHYS_FLASH_1_BM0

#else

#define CFG_FLASH_BASE		PHYS_FLASH_1_BM1

#endif

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define PHYS_FLASH_SIZE	0x02000000	/* 32MB */
#define CFG_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */
/* addr of environment */
#define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + 0x020000)

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE	0x20000	/* Total Size of Environment Sector */
#define CONFIG_ENV_OFFSET	0x20000	/* environment starts here */

#endif							/* __CONFIG_H */
Commit	Line	Data
63e73c9a WD	1	/*
	2	* (C) Copyright 2004
	3	* Texas Instruments.
	4	* Kshitij Gupta <kshitij@ti.com>
	5	* Configuration settings for the TI OMAP 1610 H2 board.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
63e73c9a WD	29	/*
	30	* High Level Configuration Options
	31	* (easy to change)
	32	*/
	33	#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
	34	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	35	#define CONFIG_OMAP1610 1 /* which is in a 1610 */
	36	#define CONFIG_H2_OMAP1610 1 /* on an H2 Board */
a1f4a3dd	37	#define CONFIG_MACH_OMAP_H2 /* Select board mach-type */
63e73c9a WD	38
	39	/* input clock of PLL */
	40	/* the OMAP1610 H2 has 12MHz input clock */
	41	#define CONFIG_SYS_CLK_FREQ 12000000
	42
	43	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	44
	45	#define CONFIG_MISC_INIT_R
	46
	47	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	48	#define CONFIG_SETUP_MEMORY_TAGS 1
08b6aa61	49	#define CONFIG_INITRD_TAG 1
63e73c9a WD	50
	51	/*
	52	* Size of malloc() pool
	53	*/
0e8d1586	54	#define CFG_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
63e73c9a WD	55	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	56
	57	/*
	58	* Hardware drivers
	59	*/
	60	#define CONFIG_DRIVER_LAN91C96
	61	#define CONFIG_LAN91C96_BASE 0x04000300
	62	#define CONFIG_LAN91C96_EXT_PHY
	63
	64	/*
	65	* NS16550 Configuration
	66	*/
	67	#define CFG_NS16550
	68	#define CFG_NS16550_SERIAL
	69	#define CFG_NS16550_REG_SIZE (-4)
	70	#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
	71	#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart */
028ab6b5	72
63e73c9a WD	73	/*
	74	* select serial console configuration
	75	*/
	76	#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 H2 */
	77
	78	/* allow to overwrite serial and ethaddr */
	79	#define CONFIG_ENV_OVERWRITE
	80	#define CONFIG_CONS_INDEX 1
	81	#define CONFIG_BAUDRATE 115200
	82	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	83
a5cb2309 JL	84
	85	/*
	86	* Command line configuration.
	87	*/
	88	#include <config_cmd_default.h>
	89
	90	#define CONFIG_CMD_DHCP
	91
	92
d3b8c1a7 JL	93	/*
	94	* BOOTP options
	95	*/
	96	#define CONFIG_BOOTP_SUBNETMASK
	97	#define CONFIG_BOOTP_GATEWAY
	98	#define CONFIG_BOOTP_HOSTNAME
	99	#define CONFIG_BOOTP_BOOTPATH
	100
63e73c9a	101
63e73c9a WD	102	#include <configs/omap1510.h>
	103
	104	#define CONFIG_BOOTDELAY 3
08b6aa61	105	#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=dhcp"
855a496f WD	106	#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
855a496f WD	107	#define CFG_AUTOLOAD "n" /* No autoload */
63e73c9a	108
a5cb2309	109	#if defined(CONFIG_CMD_KGDB)
63e73c9a WD	110	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
	111	#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
	112	#endif
	113
	114	/*
	115	* Miscellaneous configurable options
	116	*/
	117	#define CFG_LONGHELP /* undef to save memory */
	118	#define CFG_PROMPT "OMAP1610 H2 # " /* Monitor Command Prompt */
	119	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	120	/* Print Buffer Size */
	121	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
	122	#define CFG_MAXARGS 16 /* max number of command args */
	123	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	124
	125	#define CFG_MEMTEST_START 0x10000000 /* memtest works on */
	126	#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
	127
	128	#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
	129
	130	#define CFG_LOAD_ADDR 0x10000000 /* default load address */
	131
	132	/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
	133	* DPLL1. This time is further subdivided by a local divisor.
	134	*/
	135	#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */
	136	#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
	137	#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
	138
	139	/*-----------------------------------------------------------------------
	140	* Stack sizes
	141	*
	142	* The stack sizes are set up in start.S using the settings below
	143	*/
	144	#define CONFIG_STACKSIZE (1281024) / regular stack */
	145	#ifdef CONFIG_USE_IRQ
	146	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	147	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	148	#endif
	149
	150	/*-----------------------------------------------------------------------
	151	* Physical Memory Map
	152	*/
3ff02c27 WD	153	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
3ff02c27 WD	154	#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
63e73c9a WD	155	#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
63e73c9a WD	156
3ff02c27 WD	157	#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */
	158	#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */
	159
	160	#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */
ca0e7748	161
3ff02c27 WD	162	#ifndef __ASSEMBLY__
3ff02c27 WD	163	extern unsigned long omap_flash_base; /* set in flash__init */
63e73c9a	164	#endif
3ff02c27 WD	165	#define CFG_FLASH_BASE omap_flash_base
	166
	167	#elif defined(CONFIG_CS0_BOOT)
	168
	169	#define CFG_FLASH_BASE PHYS_FLASH_1_BM0
63e73c9a	170
3ff02c27 WD	171	#else
	172
	173	#define CFG_FLASH_BASE PHYS_FLASH_1_BM1
	174
	175	#endif
63e73c9a WD	176
	177	/*-----------------------------------------------------------------------
	178	* FLASH and environment organization
	179	*/
	180	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	181	#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
	182	#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
	183	/* addr of environment */
0e8d1586	184	#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x020000)
63e73c9a WD	185
	186	/* timeout values are in ticks */
	187	#define CFG_FLASH_ERASE_TOUT (20CFG_HZ) / Timeout for Flash Erase */
	188	#define CFG_FLASH_WRITE_TOUT (20CFG_HZ) / Timeout for Flash Write */
	189
5a1aceb0	190	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	191	#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
0e8d1586 JCPV	192	#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
63e73c9a WD	193
63e73c9a WD	194	#endif /* __CONFIG_H */