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6f21347d WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Texas Instruments. | |
4 | * Kshitij Gupta <kshitij@ti.com> | |
5 | * Configuation settings for the TI OMAP Innovator board. | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | /* | |
30 | * High Level Configuration Options | |
31 | * (easy to change) | |
32 | */ | |
33 | #define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ | |
34 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ | |
35 | #define CONFIG_OMAP1610 1 /* which is in a 1610 */ | |
36 | #define CONFIG_INNOVATOROMAP1610 1 /* a Innovator Board */ | |
a1f4a3dd | 37 | #define CONFIG_MACH_OMAP_INNOVATOR /* Select board mach-type */ |
6f21347d WD |
38 | |
39 | /* input clock of PLL */ | |
40 | /* the OMAP1610 Innovator has 12MHz input clock */ | |
41 | #define CONFIG_SYS_CLK_FREQ 12000000 | |
42 | ||
43 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
44 | ||
45 | #define CONFIG_MISC_INIT_R | |
46 | ||
47 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
48 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
49 | ||
50 | /* | |
51 | * Size of malloc() pool | |
52 | */ | |
6d0f6bcf | 53 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
6f21347d WD |
54 | |
55 | /* | |
56 | * Hardware drivers | |
57 | */ | |
58 | /* | |
59 | */ | |
ac6b362a NM |
60 | #define CONFIG_NET_MULTI |
61 | #define CONFIG_LAN91C96 | |
6f21347d WD |
62 | #define CONFIG_LAN91C96_BASE 0x04000300 |
63 | #define CONFIG_LAN91C96_EXT_PHY | |
64 | ||
65 | /* | |
66 | * NS16550 Configuration | |
67 | */ | |
6d0f6bcf JCPV |
68 | #define CONFIG_SYS_NS16550 |
69 | #define CONFIG_SYS_NS16550_SERIAL | |
70 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
71 | #define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ | |
72 | #define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ | |
6f21347d WD |
73 | |
74 | /* | |
75 | * select serial console configuration | |
76 | */ | |
a8c7c708 | 77 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 Innovator */ |
6f21347d WD |
78 | |
79 | /* allow to overwrite serial and ethaddr */ | |
80 | #define CONFIG_ENV_OVERWRITE | |
81 | #define CONFIG_CONS_INDEX 1 | |
82 | #define CONFIG_BAUDRATE 115200 | |
6d0f6bcf | 83 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
6f21347d | 84 | |
a5cb2309 JL |
85 | |
86 | /* | |
87 | * Command line configuration. | |
88 | */ | |
89 | #include <config_cmd_default.h> | |
90 | ||
91 | #define CONFIG_CMD_DHCP | |
92 | ||
93 | ||
d3b8c1a7 JL |
94 | /* |
95 | * BOOTP options | |
96 | */ | |
97 | #define CONFIG_BOOTP_SUBNETMASK | |
98 | #define CONFIG_BOOTP_GATEWAY | |
99 | #define CONFIG_BOOTP_HOSTNAME | |
100 | #define CONFIG_BOOTP_BOOTPATH | |
101 | ||
6f21347d | 102 | |
6f21347d WD |
103 | #include <configs/omap1510.h> |
104 | ||
105 | #define CONFIG_BOOTDELAY 3 | |
106 | #define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ | |
107 | root=/dev/nfs rw nfsroot=157.87.82.48:\ | |
108 | /home/a0875451/mwd/myfs/target ip=dhcp" | |
109 | #define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ | |
110 | #define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ | |
111 | #define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ | |
112 | #define CONFIG_BOOTFILE "uImage" /* file to load */ | |
113 | ||
a5cb2309 | 114 | #if defined(CONFIG_CMD_KGDB) |
6f21347d WD |
115 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
116 | #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ | |
117 | #endif | |
118 | ||
119 | /* | |
120 | * Miscellaneous configurable options | |
121 | */ | |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
123 | #define CONFIG_SYS_PROMPT "OMAP1610 Innovator # " /* Monitor Command Prompt */ | |
124 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
6f21347d | 125 | /* Print Buffer Size */ |
6d0f6bcf JCPV |
126 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
127 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
128 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
6f21347d | 129 | |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ |
131 | #define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ | |
6f21347d | 132 | |
6d0f6bcf | 133 | #define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ |
6f21347d | 134 | |
42d1f039 | 135 | /* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by |
6f21347d WD |
136 | * DPLL1. This time is further subdivided by a local divisor. |
137 | */ | |
6d0f6bcf | 138 | #define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ |
81472d89 LM |
139 | #define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ |
140 | #define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) | |
6f21347d WD |
141 | |
142 | /*----------------------------------------------------------------------- | |
143 | * Stack sizes | |
144 | * | |
145 | * The stack sizes are set up in start.S using the settings below | |
146 | */ | |
147 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
148 | #ifdef CONFIG_USE_IRQ | |
149 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
150 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
151 | #endif | |
152 | ||
153 | /*----------------------------------------------------------------------- | |
154 | * Physical Memory Map | |
155 | */ | |
3ff02c27 WD |
156 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
157 | #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ | |
6f21347d WD |
158 | #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
159 | ||
3ff02c27 WD |
160 | #define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */ |
161 | #define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */ | |
162 | ||
163 | #ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */ | |
ca0e7748 | 164 | |
3ff02c27 WD |
165 | #ifndef __ASSEMBLY__ |
166 | extern unsigned long omap_flash_base; /* set in flash__init */ | |
63e73c9a | 167 | #endif |
6d0f6bcf | 168 | #define CONFIG_SYS_FLASH_BASE omap_flash_base |
3ff02c27 WD |
169 | |
170 | #elif defined(CONFIG_CS0_BOOT) | |
171 | ||
6d0f6bcf | 172 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM0 |
6f21347d | 173 | |
3ff02c27 WD |
174 | #else |
175 | ||
6d0f6bcf | 176 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM1 |
3ff02c27 WD |
177 | |
178 | #endif | |
6f21347d WD |
179 | |
180 | /*----------------------------------------------------------------------- | |
181 | * FLASH and environment organization | |
182 | */ | |
6d0f6bcf | 183 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
6f21347d | 184 | #define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ |
6d0f6bcf | 185 | #define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ |
6f21347d | 186 | /* addr of environment */ |
6d0f6bcf | 187 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000) |
6f21347d WD |
188 | |
189 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
190 | #define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
191 | #define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
6f21347d | 192 | |
5a1aceb0 | 193 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
194 | #define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ |
195 | #define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */ | |
6f21347d WD |
196 | |
197 | #endif /* __CONFIG_H */ |