[people/ms/u-boot.git] / include / configs / omap3_beagle.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * Configuration settings for the TI OMAP3530 Beagle board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3430		1	/* which is in a 3430 */
#define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#undef CONFIG_USE_IRQ				/* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
						/* initial data */

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 on Beagle Rev 2 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_MMC			1
#define CONFIG_OMAP3_MMC		1
#define CONFIG_DOS_PARTITION		1

/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR		1

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define MTDIDS_DEFAULT			"nand0=nand"
#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
					"1920k(u-boot),128k(u-boot-env),"\
					"4m(kernel),-(fs)"

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/
#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
#undef CONFIG_CMD_NFS		/* NFS support			*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* Environment information */
#define CONFIG_BOOTDELAY		10

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyS2,115200n8\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext3 rootwait\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=jffs2\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapfb.debug=y " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapfb.debug=y " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmc init; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#define CONFIG_AUTO_COMPLETE		1
/*
 * Miscellaneous configurable options
 */
#define V_PROMPT			"OMAP3 beagleboard.org # "

#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		V_PROMPT
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
								/* works on */
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/* SDRAM Bank Allocation method */
#define SDRC_R_B_C		1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
						/* one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_SYS_FLASH_BASE		boot_flash_base

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_NAND		1
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
#define CONFIG_ENV_OFFSET		boot_flash_off
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
					CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#ifndef __ASSEMBLY__
extern struct gpmc *gpmc_cfg;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif

#endif /* __CONFIG_H */
Commit	Line	Data
f904cdbb DB	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	*
	7	* Configuration settings for the TI OMAP3530 Beagle board.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
f904cdbb DB	30
	31	/*
	32	* High Level Configuration Options
	33	*/
	34	#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
	35	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	36	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
	37	#define CONFIG_OMAP3430 1 /* which is in a 3430 */
	38	#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
	39
	40	#include <asm/arch/cpu.h> /* get chip and board defs */
	41	#include <asm/arch/omap3.h>
	42
6a6b62e3 SP	43	/*
	44	* Display CPU and Board information
	45	*/
	46	#define CONFIG_DISPLAY_CPUINFO 1
	47	#define CONFIG_DISPLAY_BOARDINFO 1
	48
f904cdbb DB	49	/* Clock Defines */
	50	#define V_OSCK 26000000 /* Clock output from T2 */
	51	#define V_SCLK (V_OSCK >> 1)
	52
	53	#undef CONFIG_USE_IRQ /* no support for IRQs */
	54	#define CONFIG_MISC_INIT_R
	55
	56	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	57	#define CONFIG_SETUP_MEMORY_TAGS 1
	58	#define CONFIG_INITRD_TAG 1
	59	#define CONFIG_REVISION_TAG 1
	60
	61	/*
	62	* Size of malloc() pool
	63	*/
9c44ddcc	64	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
f904cdbb	65	/* Sector */
9c44ddcc	66	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
f904cdbb DB	67	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
	68	/* initial data */
	69
	70	/*
	71	* Hardware drivers
	72	*/
	73
	74	/*
	75	* NS16550 Configuration
	76	*/
	77	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	78
	79	#define CONFIG_SYS_NS16550
	80	#define CONFIG_SYS_NS16550_SERIAL
	81	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	82	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	83
	84	/*
	85	* select serial console configuration
	86	*/
	87	#define CONFIG_CONS_INDEX 3
	88	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	89	#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
	90
	91	/* allow to overwrite serial and ethaddr */
	92	#define CONFIG_ENV_OVERWRITE
	93	#define CONFIG_BAUDRATE 115200
	94	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	95	115200}
	96	#define CONFIG_MMC 1
	97	#define CONFIG_OMAP3_MMC 1
	98	#define CONFIG_DOS_PARTITION 1
	99
30563a04 NM	100	/* DDR - I use Micron DDR */
	101	#define CONFIG_OMAP3_MICRON_DDR 1
	102
f904cdbb DB	103	/* commands to include */
	104	#include <config_cmd_default.h>
	105
	106	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	107	#define CONFIG_CMD_FAT /* FAT support */
	108	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
917cfc70	109	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
942556a9	110	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
917cfc70 NM	111	#define MTDIDS_DEFAULT "nand0=nand"
	112	#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
	113	"1920k(u-boot),128k(u-boot-env),"\
	114	"4m(kernel),-(fs)"
f904cdbb DB	115
	116	#define CONFIG_CMD_I2C /* I2C serial bus support */
	117	#define CONFIG_CMD_MMC /* MMC support */
	118	#define CONFIG_CMD_NAND /* NAND support */
	119
	120	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	121	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	122	#undef CONFIG_CMD_IMI /* iminfo */
	123	#undef CONFIG_CMD_IMLS /* List all found images */
	124	#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	125	#undef CONFIG_CMD_NFS /* NFS support */
	126
	127	#define CONFIG_SYS_NO_FLASH
0297ec7e	128	#define CONFIG_HARD_I2C 1
f904cdbb DB	129	#define CONFIG_SYS_I2C_SPEED 100000
	130	#define CONFIG_SYS_I2C_SLAVE 1
	131	#define CONFIG_SYS_I2C_BUS 0
	132	#define CONFIG_SYS_I2C_BUS_SELECT 1
	133	#define CONFIG_DRIVER_OMAP34XX_I2C 1
	134
2c155130 TR	135	/*
	136	* TWL4030
	137	*/
	138	#define CONFIG_TWL4030_POWER 1
	139	#define CONFIG_TWL4030_LED 1
	140
f904cdbb DB	141	/*
	142	* Board NAND Info.
	143	*/
	144	#define CONFIG_NAND_OMAP_GPMC
	145	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	146	/* to access nand */
	147	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	148	/* to access nand at */
	149	/* CS0 */
	150	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	151
	152	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	153	/* devices */
f904cdbb DB	154	#define CONFIG_JFFS2_NAND
	155	/* nand device jffs2 lives on */
	156	#define CONFIG_JFFS2_DEV "nand0"
	157	/* start of jffs2 partition */
	158	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	159	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
	160	/* partition */
	161
	162	/* Environment information */
	163	#define CONFIG_BOOTDELAY 10
	164
	165	#define CONFIG_EXTRA_ENV_SETTINGS \
	166	"loadaddr=0x82000000\0" \
	167	"console=ttyS2,115200n8\0" \
13d2cb98 SS	168	"vram=12M\0" \
	169	"dvimode=1024x768MR-16@60\0" \
	170	"defaultdisplay=dvi\0" \
	171	"mmcroot=/dev/mmcblk0p2 rw\0" \
	172	"mmcrootfstype=ext3 rootwait\0" \
	173	"nandroot=/dev/mtdblock4 rw\0" \
	174	"nandrootfstype=jffs2\0" \
f904cdbb	175	"mmcargs=setenv bootargs console=${console} " \
13d2cb98 SS	176	"vram=${vram} " \
	177	"omapfb.mode=dvi:${dvimode} " \
	178	"omapfb.debug=y " \
	179	"omapdss.def_disp=${defaultdisplay} " \
	180	"root=${mmcroot} " \
	181	"rootfstype=${mmcrootfstype}\0" \
f904cdbb	182	"nandargs=setenv bootargs console=${console} " \
13d2cb98 SS	183	"vram=${vram} " \
	184	"omapfb.mode=dvi:${dvimode} " \
	185	"omapfb.debug=y " \
	186	"omapdss.def_disp=${defaultdisplay} " \
	187	"root=${nandroot} " \
	188	"rootfstype=${nandrootfstype}\0" \
f904cdbb DB	189	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
f904cdbb DB	190	"bootscript=echo Running bootscript from mmc ...; " \
74de7aef	191	"source ${loadaddr}\0" \
f904cdbb DB	192	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	193	"mmcboot=echo Booting from mmc ...; " \
	194	"run mmcargs; " \
	195	"bootm ${loadaddr}\0" \
	196	"nandboot=echo Booting from nand ...; " \
	197	"run nandargs; " \
	198	"nand read ${loadaddr} 280000 400000; " \
	199	"bootm ${loadaddr}\0" \
	200
	201	#define CONFIG_BOOTCOMMAND \
a85693b3	202	"if mmc init; then " \
f904cdbb DB	203	"if run loadbootscript; then " \
	204	"run bootscript; " \
	205	"else " \
	206	"if run loaduimage; then " \
	207	"run mmcboot; " \
	208	"else run nandboot; " \
	209	"fi; " \
	210	"fi; " \
	211	"else run nandboot; fi"
	212
	213	#define CONFIG_AUTO_COMPLETE 1
	214	/*
	215	* Miscellaneous configurable options
	216	*/
	217	#define V_PROMPT "OMAP3 beagleboard.org # "
	218
	219	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	220	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	221	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	222	#define CONFIG_SYS_PROMPT V_PROMPT
	223	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	224	/* Print Buffer Size */
	225	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	226	sizeof(CONFIG_SYS_PROMPT) + 16)
	227	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	228	/* Boot Argument Buffer Size */
	229	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	230
	231	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
	232	/* works on */
	233	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	234	0x01F00000) /* 31MB */
	235
f904cdbb DB	236	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	237	/* load address */
	238
	239	/*
d3a513c2 MP	240	* OMAP3 has 12 GP timers, they can be driven by the system clock
	241	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	242	* This rate is divided by a local divisor.
f904cdbb	243	*/
f904cdbb	244	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
d3a513c2 MP	245	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
d3a513c2 MP	246	#define CONFIG_SYS_HZ 1000
f904cdbb DB	247
	248	/*-----------------------------------------------------------------------
	249	* Stack sizes
	250	*
	251	* The stack sizes are set up in start.S using the settings below
	252	*/
9c44ddcc	253	#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
f904cdbb	254	#ifdef CONFIG_USE_IRQ
9c44ddcc SP	255	#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
9c44ddcc SP	256	#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
f904cdbb DB	257	#endif
	258
	259	/*-----------------------------------------------------------------------
	260	* Physical Memory Map
	261	*/
	262	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	263	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
9c44ddcc	264	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
f904cdbb DB	265	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	266
	267	/* SDRAM Bank Allocation method */
	268	#define SDRC_R_B_C 1
	269
	270	/*-----------------------------------------------------------------------
	271	* FLASH and environment organization
	272	*/
	273
	274	/* ** PISMO SUPPORT * */
	275
	276	/* Configure the PISMO */
	277	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	278	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	279
	280	#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
	281	/* one chip */
	282	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
9c44ddcc	283	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
f904cdbb DB	284
	285	#define CONFIG_SYS_FLASH_BASE boot_flash_base
	286
	287	/* Monitor at start of flash */
	288	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	289	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	290
	291	#define CONFIG_ENV_IS_IN_NAND 1
	292	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
	293	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	294
	295	#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
	296	#define CONFIG_ENV_OFFSET boot_flash_off
	297	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
	298
	299	/*-----------------------------------------------------------------------
	300	* CFI FLASH driver setup
	301	*/
	302	/* timeout values are in ticks */
	303	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	304	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	305
	306	/* Flash banks JFFS2 should use */
	307	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	308	CONFIG_SYS_MAX_NAND_DEVICE)
	309	#define CONFIG_SYS_JFFS2_MEM_NAND
	310	/* use flash_info[2] */
	311	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
	312	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	313
	314	#ifndef __ASSEMBLY__
97a099ea	315	extern struct gpmc *gpmc_cfg;
f904cdbb DB	316	extern unsigned int boot_flash_base;
	317	extern volatile unsigned int boot_flash_env_addr;
	318	extern unsigned int boot_flash_off;
	319	extern unsigned int boot_flash_sec;
	320	extern unsigned int boot_flash_type;
	321	#endif
	322
f904cdbb	323	#endif /* __CONFIG_H */