[people/ms/u-boot.git] / include / configs / omap3_beagle.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * Configuration settings for the TI OMAP3530 Beagle board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#undef CONFIG_USE_IRQ				/* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_OF_LIBFDT		1

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 on Beagle Rev 2 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/* Status LED */
#define CONFIG_STATUS_LED		1
#define CONFIG_BOARD_SPECIFIC_LED	1
#define STATUS_LED_BIT			0x01
#define STATUS_LED_STATE		STATUS_LED_ON
#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_BIT1			0x02
#define STATUS_LED_STATE1		STATUS_LED_ON
#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_BOOT			STATUS_LED_BIT
#define STATUS_LED_GREEN		STATUS_LED_BIT1

/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR		1

/* Enable Multi Bus support for I2C */
#define CONFIG_I2C_MULTI_BUS		1

/* Probe all devices */
#define CONFIG_SYS_I2C_NOPROBES		{{0x0, 0x0}}

/* USB */
#define CONFIG_MUSB_UDC			1
#define CONFIG_USB_OMAP3		1
#define CONFIG_TWL4030_USB		1

/* USB device configuration */
#define CONFIG_USB_DEVICE		1
#define CONFIG_USB_TTY			1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1

/* USB EHCI */
#define CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_ETHER_ASIX


/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define MTDIDS_DEFAULT			"nand0=nand"
#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
					"1920k(u-boot),128k(u-boot-env),"\
					"4m(kernel),-(fs)"

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_USB_STORAGE	/* USB storage support		*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_LED		/* LED support			*/
#define CONFIG_CMD_NET      /* bootp, tftpboot, rarpboot    */
#define CONFIG_CMD_NFS      /* NFS support          */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SETEXPR	/* Evaluate expressions		*/

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_I2C_MULTI_BUS		1
#define CONFIG_DRIVER_OMAP34XX_I2C	1
#define CONFIG_VIDEO_OMAP3	/* DSS Support			*/

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_QUIET_TEST	1
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* Environment information */
#define CONFIG_BOOTDELAY		2

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x80200000\0" \
	"rdaddr=0x81000000\0" \
	"usbtty=cdc_acm\0" \
	"bootfile=uImage.beagle\0" \
	"console=tty02,115200n8\0" \
	"mpurate=auto\0" \
	"buddy=none "\
	"optargs=\0" \
	"camera=none\0" \
	"vram=12M\0" \
	"dvimode=640x480MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext3 rootwait\0" \
	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
	"nandrootfstype=ubifs\0" \
	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
	"ramrootfstype=ext2\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"mpurate=${mpurate} " \
		"buddy=${buddy} "\
		"camera=${camera} "\
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"mpurate=${mpurate} " \
		"buddy=${buddy} "\
		"camera=${camera} "\
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"bootenv=uEnv.txt\0" \
	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
	"importbootenv=echo Importing environment from mmc ...; " \
		"env import -t $loadaddr $filesize\0" \
	"ramargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"mpurate=${mpurate} " \
		"buddy=${buddy} "\
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${ramroot} " \
		"rootfstype=${ramrootfstype}\0" \
	"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
	"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \
	"ramboot=echo Booting from ramdisk ...; " \
		"run ramargs; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmc rescan ${mmcdev}; then " \
		"if userbutton; then " \
			"setenv bootenv user.txt;" \
		"fi;" \
		"echo SD/MMC found on device ${mmcdev};" \
		"if run loadbootenv; then " \
			"echo Loaded environment from ${bootenv};" \
			"run importbootenv;" \
		"fi;" \
		"if test -n $uenvcmd; then " \
			"echo Running uenvcmd ...;" \
			"run uenvcmd;" \
		"fi;" \
		"if run loaduimage; then " \
			"run mmcboot;" \
		"fi;" \
	"fi;" \
	"run nandboot;" \

#define CONFIG_AUTO_COMPLETE		1
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		"OMAP3 beagleboard.org # "
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_ALT_MEMTEST		1
#define CONFIG_SYS_MEMTEST_START	(0x82000000)		/* memtest */
								/* defaults */
#define CONFIG_SYS_MEMTEST_END		(0x87FFFFFF) 		/* 128MB */
#define CONFIG_SYS_MEMTEST_SCRATCH	(0x81000000)	/* dummy address */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_NAND		1
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

#define CONFIG_OMAP3_SPI

#define CONFIG_SYS_CACHELINE_SIZE	64

#endif /* __CONFIG_H */
Commit	Line	Data
f904cdbb DB	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	*
	7	* Configuration settings for the TI OMAP3530 Beagle board.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
f904cdbb DB	30
	31	/*
	32	* High Level Configuration Options
	33	*/
f904cdbb DB	34	#define CONFIG_OMAP 1 /* in a TI OMAP core */
f904cdbb DB	35	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
f904cdbb DB	36	#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
f904cdbb DB	37
cae377b5 VH	38	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5 VH	39
f904cdbb DB	40	#include <asm/arch/cpu.h> /* get chip and board defs */
	41	#include <asm/arch/omap3.h>
	42
6a6b62e3 SP	43	/*
	44	* Display CPU and Board information
	45	*/
	46	#define CONFIG_DISPLAY_CPUINFO 1
	47	#define CONFIG_DISPLAY_BOARDINFO 1
	48
f904cdbb DB	49	/* Clock Defines */
	50	#define V_OSCK 26000000 /* Clock output from T2 */
	51	#define V_SCLK (V_OSCK >> 1)
	52
	53	#undef CONFIG_USE_IRQ /* no support for IRQs */
	54	#define CONFIG_MISC_INIT_R
	55
b485556b	56	#define CONFIG_OF_LIBFDT 1
b485556b	57
f904cdbb DB	58	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	59	#define CONFIG_SETUP_MEMORY_TAGS 1
	60	#define CONFIG_INITRD_TAG 1
	61	#define CONFIG_REVISION_TAG 1
	62
	63	/*
	64	* Size of malloc() pool
	65	*/
9c44ddcc	66	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
f904cdbb	67	/* Sector */
9c44ddcc	68	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
f904cdbb DB	69
	70	/*
	71	* Hardware drivers
	72	*/
	73
	74	/*
	75	* NS16550 Configuration
	76	*/
	77	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	78
	79	#define CONFIG_SYS_NS16550
	80	#define CONFIG_SYS_NS16550_SERIAL
	81	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	82	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	83
	84	/*
	85	* select serial console configuration
	86	*/
	87	#define CONFIG_CONS_INDEX 3
	88	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	89	#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
	90
	91	/* allow to overwrite serial and ethaddr */
	92	#define CONFIG_ENV_OVERWRITE
	93	#define CONFIG_BAUDRATE 115200
	94	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	95	115200}
0cd31144	96	#define CONFIG_GENERIC_MMC 1
f904cdbb	97	#define CONFIG_MMC 1
0cd31144	98	#define CONFIG_OMAP_HSMMC 1
f904cdbb DB	99	#define CONFIG_DOS_PARTITION 1
f904cdbb DB	100
70d8c944 JK	101	/* Status LED */
	102	#define CONFIG_STATUS_LED 1
	103	#define CONFIG_BOARD_SPECIFIC_LED 1
	104	#define STATUS_LED_BIT 0x01
	105	#define STATUS_LED_STATE STATUS_LED_ON
	106	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
	107	#define STATUS_LED_BIT1 0x02
	108	#define STATUS_LED_STATE1 STATUS_LED_ON
	109	#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
	110	#define STATUS_LED_BOOT STATUS_LED_BIT
	111	#define STATUS_LED_GREEN STATUS_LED_BIT1
	112
30563a04 NM	113	/* DDR - I use Micron DDR */
	114	#define CONFIG_OMAP3_MICRON_DDR 1
	115
f74fc4ae JK	116	/* Enable Multi Bus support for I2C */
	117	#define CONFIG_I2C_MULTI_BUS 1
	118
	119	/* Probe all devices */
8c4e0ca6	120	#define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}}
f74fc4ae	121
25374bfb TR	122	/* USB */
	123	#define CONFIG_MUSB_UDC 1
	124	#define CONFIG_USB_OMAP3 1
	125	#define CONFIG_TWL4030_USB 1
	126
	127	/* USB device configuration */
	128	#define CONFIG_USB_DEVICE 1
	129	#define CONFIG_USB_TTY 1
	130	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
25374bfb	131
d90859a6 AH	132	/* USB EHCI */
	133	#define CONFIG_CMD_USB
	134	#define CONFIG_USB_EHCI
	135	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
2162439a KK	136	#define CONFIG_USB_HOST_ETHER
2162439a KK	137	#define CONFIG_USB_ETHER_SMSC95XX
54b62d59	138	#define CONFIG_USB_ETHER_ASIX
2162439a	139
d90859a6	140
f904cdbb DB	141	/* commands to include */
	142	#include <config_cmd_default.h>
	143
95c6f6d3	144	#define CONFIG_CMD_CACHE
f904cdbb DB	145	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	146	#define CONFIG_CMD_FAT /* FAT support */
	147	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
917cfc70	148	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
942556a9	149	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
917cfc70 NM	150	#define MTDIDS_DEFAULT "nand0=nand"
	151	#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
	152	"1920k(u-boot),128k(u-boot-env),"\
	153	"4m(kernel),-(fs)"
f904cdbb DB	154
	155	#define CONFIG_CMD_I2C /* I2C serial bus support */
	156	#define CONFIG_CMD_MMC /* MMC support */
d90859a6	157	#define CONFIG_USB_STORAGE /* USB storage support */
f904cdbb	158	#define CONFIG_CMD_NAND /* NAND support */
70d8c944	159	#define CONFIG_CMD_LED /* LED support */
2162439a KK	160	#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	161	#define CONFIG_CMD_NFS /* NFS support */
	162	#define CONFIG_CMD_PING
54b62d59	163	#define CONFIG_CMD_DHCP
933d3701	164	#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
f904cdbb DB	165
	166	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	167	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	168	#undef CONFIG_CMD_IMI /* iminfo */
	169	#undef CONFIG_CMD_IMLS /* List all found images */
f904cdbb DB	170
f904cdbb DB	171	#define CONFIG_SYS_NO_FLASH
0297ec7e	172	#define CONFIG_HARD_I2C 1
f904cdbb DB	173	#define CONFIG_SYS_I2C_SPEED 100000
	174	#define CONFIG_SYS_I2C_SLAVE 1
	175	#define CONFIG_SYS_I2C_BUS 0
	176	#define CONFIG_SYS_I2C_BUS_SELECT 1
ca5f80ae	177	#define CONFIG_I2C_MULTI_BUS 1
f904cdbb	178	#define CONFIG_DRIVER_OMAP34XX_I2C 1
25a4d017	179	#define CONFIG_VIDEO_OMAP3 /* DSS Support */
f904cdbb	180
2c155130 TR	181	/*
	182	* TWL4030
	183	*/
	184	#define CONFIG_TWL4030_POWER 1
	185	#define CONFIG_TWL4030_LED 1
	186
f904cdbb DB	187	/*
	188	* Board NAND Info.
	189	*/
60c23173	190	#define CONFIG_SYS_NAND_QUIET_TEST 1
f904cdbb DB	191	#define CONFIG_NAND_OMAP_GPMC
	192	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	193	/* to access nand */
	194	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	195	/* to access nand at */
	196	/* CS0 */
	197	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	198
	199	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	200	/* devices */
f904cdbb DB	201	#define CONFIG_JFFS2_NAND
	202	/* nand device jffs2 lives on */
	203	#define CONFIG_JFFS2_DEV "nand0"
	204	/* start of jffs2 partition */
	205	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	206	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
	207	/* partition */
	208
	209	/* Environment information */
4c37e8de	210	#define CONFIG_BOOTDELAY 2
f904cdbb DB	211
f904cdbb DB	212	#define CONFIG_EXTRA_ENV_SETTINGS \
f4b36ea9 JK	213	"loadaddr=0x80200000\0" \
f4b36ea9 JK	214	"rdaddr=0x81000000\0" \
25374bfb	215	"usbtty=cdc_acm\0" \
e6829308	216	"bootfile=uImage.beagle\0" \
73ce5003	217	"console=tty02,115200n8\0" \
f6e593bb	218	"mpurate=auto\0" \
b1660314	219	"buddy=none "\
c522eac4 JK	220	"optargs=\0" \
c522eac4 JK	221	"camera=none\0" \
13d2cb98	222	"vram=12M\0" \
f4b36ea9	223	"dvimode=640x480MR-16@60\0" \
13d2cb98	224	"defaultdisplay=dvi\0" \
0cd31144	225	"mmcdev=0\0" \
13d2cb98 SS	226	"mmcroot=/dev/mmcblk0p2 rw\0" \
13d2cb98 SS	227	"mmcrootfstype=ext3 rootwait\0" \
3c6e50d7 SS	228	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
3c6e50d7 SS	229	"nandrootfstype=ubifs\0" \
f4b36ea9 JK	230	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
f4b36ea9 JK	231	"ramrootfstype=ext2\0" \
f904cdbb	232	"mmcargs=setenv bootargs console=${console} " \
c522eac4	233	"${optargs} " \
5af32460	234	"mpurate=${mpurate} " \
b1660314	235	"buddy=${buddy} "\
c522eac4	236	"camera=${camera} "\
13d2cb98 SS	237	"vram=${vram} " \
13d2cb98 SS	238	"omapfb.mode=dvi:${dvimode} " \
13d2cb98 SS	239	"omapdss.def_disp=${defaultdisplay} " \
	240	"root=${mmcroot} " \
	241	"rootfstype=${mmcrootfstype}\0" \
f904cdbb	242	"nandargs=setenv bootargs console=${console} " \
c522eac4	243	"${optargs} " \
5af32460	244	"mpurate=${mpurate} " \
b1660314	245	"buddy=${buddy} "\
c522eac4	246	"camera=${camera} "\
13d2cb98 SS	247	"vram=${vram} " \
13d2cb98 SS	248	"omapfb.mode=dvi:${dvimode} " \
13d2cb98 SS	249	"omapdss.def_disp=${defaultdisplay} " \
	250	"root=${nandroot} " \
	251	"rootfstype=${nandrootfstype}\0" \
f835ea71 JK	252	"bootenv=uEnv.txt\0" \
f835ea71 JK	253	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
cf073e49 AH	254	"importbootenv=echo Importing environment from mmc ...; " \
cf073e49 AH	255	"env import -t $loadaddr $filesize\0" \
f4b36ea9 JK	256	"ramargs=setenv bootargs console=${console} " \
	257	"${optargs} " \
	258	"mpurate=${mpurate} " \
	259	"buddy=${buddy} "\
	260	"vram=${vram} " \
	261	"omapfb.mode=dvi:${dvimode} " \
	262	"omapdss.def_disp=${defaultdisplay} " \
	263	"root=${ramroot} " \
	264	"rootfstype=${ramrootfstype}\0" \
	265	"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
e5549f0f KK	266	"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
e5549f0f KK	267	"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \
f904cdbb DB	268	"mmcboot=echo Booting from mmc ...; " \
	269	"run mmcargs; " \
	270	"bootm ${loadaddr}\0" \
	271	"nandboot=echo Booting from nand ...; " \
	272	"run nandargs; " \
	273	"nand read ${loadaddr} 280000 400000; " \
	274	"bootm ${loadaddr}\0" \
f4b36ea9 JK	275	"ramboot=echo Booting from ramdisk ...; " \
	276	"run ramargs; " \
	277	"bootm ${loadaddr}\0" \
f904cdbb DB	278
f904cdbb DB	279	#define CONFIG_BOOTCOMMAND \
0cd31144	280	"if mmc rescan ${mmcdev}; then " \
f835ea71 JK	281	"if userbutton; then " \
	282	"setenv bootenv user.txt;" \
	283	"fi;" \
cf073e49 AH	284	"echo SD/MMC found on device ${mmcdev};" \
cf073e49 AH	285	"if run loadbootenv; then " \
f835ea71	286	"echo Loaded environment from ${bootenv};" \
cf073e49 AH	287	"run importbootenv;" \
	288	"fi;" \
	289	"if test -n $uenvcmd; then " \
	290	"echo Running uenvcmd ...;" \
	291	"run uenvcmd;" \
	292	"fi;" \
	293	"if run loaduimage; then " \
	294	"run mmcboot;" \
	295	"fi;" \
	296	"fi;" \
	297	"run nandboot;" \
f904cdbb DB	298
	299	#define CONFIG_AUTO_COMPLETE 1
	300	/*
	301	* Miscellaneous configurable options
	302	*/
f904cdbb DB	303	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	304	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	305	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
1270ec13	306	#define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
f62b1257	307	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
f904cdbb DB	308	/* Print Buffer Size */
	309	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	310	sizeof(CONFIG_SYS_PROMPT) + 16)
933d3701	311	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
f904cdbb DB	312	/* Boot Argument Buffer Size */
	313	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	314
780a97f8 JK	315	#define CONFIG_SYS_ALT_MEMTEST 1
	316	#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
	317	/* defaults */
	318	#define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */
	319	#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
f904cdbb	320
f904cdbb DB	321	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	322	/* load address */
	323
	324	/*
d3a513c2 MP	325	* OMAP3 has 12 GP timers, they can be driven by the system clock
	326	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	327	* This rate is divided by a local divisor.
f904cdbb	328	*/
f904cdbb	329	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
d3a513c2 MP	330	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
d3a513c2 MP	331	#define CONFIG_SYS_HZ 1000
f904cdbb DB	332
	333	/*-----------------------------------------------------------------------
	334	* Stack sizes
	335	*
	336	* The stack sizes are set up in start.S using the settings below
	337	*/
9c44ddcc	338	#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
f904cdbb DB	339
	340	/*-----------------------------------------------------------------------
	341	* Physical Memory Map
	342	*/
	343	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	344	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
9c44ddcc	345	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
f904cdbb DB	346	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
f904cdbb DB	347
f904cdbb DB	348	/*-----------------------------------------------------------------------
	349	* FLASH and environment organization
	350	*/
	351
	352	/* ** PISMO SUPPORT * */
	353
	354	/* Configure the PISMO */
	355	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	356	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	357
9c44ddcc	358	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
f904cdbb	359
6cbec7b3 LC	360	#if defined(CONFIG_CMD_NAND)
	361	#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
	362	#endif
f904cdbb DB	363
	364	/* Monitor at start of flash */
	365	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	366	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	367
	368	#define CONFIG_ENV_IS_IN_NAND 1
	369	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
	370	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	371
6cbec7b3 LC	372	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
6cbec7b3 LC	373	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
f904cdbb DB	374	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
f904cdbb DB	375
561142af	376	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
31bfcf1c SS	377	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	378	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	379	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	380	CONFIG_SYS_INIT_RAM_SIZE - \
	381	GENERATED_GBL_DATA_SIZE)
561142af	382
53736baa DB	383	#define CONFIG_OMAP3_SPI
53736baa DB	384
8e40852f A	385	#define CONFIG_SYS_CACHELINE_SIZE 64
8e40852f A	386
f904cdbb	387	#endif /* __CONFIG_H */